RMUL2025/lib/cmsis_svd/data/STMicro/STM32G081.svd

<?xml version="1.0" encoding="utf-8" standalone="no"?>
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Copyright (c) 2022 STMicroelectronics.

 SPDX-License-Identifier: Apache-2.0

 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
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 http://www.apache.org/licenses/LICENSE-2.0

 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
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<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  <name>STM32G081</name>
  <version>1.4</version>
  <description>STM32G081</description>
  <cpu>
    <name>CM0</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <nvicPrioBits>4</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <size>0x20</size>
  <resetValue>0x0</resetValue>
  <resetMask>0xFFFFFFFF</resetMask>
  <peripherals>
    <peripheral>
      <name>IWDG</name>
      <description>Independent watchdog</description>
      <groupName>IWDG</groupName>
      <baseAddress>0x40003000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>KR</name>
          <displayName>KR</displayName>
          <description>Key register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>KEY</name>
              <description>Key value (write only, read
              0x0000)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PR</name>
          <displayName>PR</displayName>
          <description>Prescaler register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PR</name>
              <description>Prescaler divider</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RLR</name>
          <displayName>RLR</displayName>
          <description>Reload register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>RL</name>
              <description>Watchdog counter reload
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>Status register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WVU</name>
              <description>Watchdog counter window value
              update</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RVU</name>
              <description>Watchdog counter reload value
              update</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PVU</name>
              <description>Watchdog prescaler value
              update</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>WINR</name>
          <displayName>WINR</displayName>
          <description>Window register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>WIN</name>
              <description>Watchdog counter window
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR</name>
          <displayName>HWCFGR</displayName>
          <description>hardware configuration
          register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000071</resetValue>
          <fields>
            <field>
              <name>WINDOW</name>
              <description>Support of Window function</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>PR_DEFAULT</name>
              <description>Prescaler default value</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000023</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00120041</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>WWDG</name>
      <description>System window watchdog</description>
      <groupName>WWDG</groupName>
      <baseAddress>0x40002C00</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>WWDG</name>
        <description>Window watchdog interrupt</description>
        <value>0</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000007F</resetValue>
          <fields>
            <field>
              <name>WDGA</name>
              <description>Activation bit</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>T</name>
              <description>7-bit counter (MSB to LSB)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFR</name>
          <displayName>CFR</displayName>
          <description>Configuration register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000007F</resetValue>
          <fields>
            <field>
              <name>WDGTB</name>
              <description>Timer base</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>EWI</name>
              <description>Early wakeup interrupt</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>W</name>
              <description>7-bit window value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>Status register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EWIF</name>
              <description>Early wakeup interrupt
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>FLASH</name>
      <description>Flash</description>
      <groupName>Flash</groupName>
      <baseAddress>0x40022000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>FLASH</name>
        <description>Flash global interrupt</description>
        <value>3</value>
      </interrupt>
      <registers>
        <register>
          <name>ACR</name>
          <displayName>ACR</displayName>
          <description>Access control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000600</resetValue>
          <fields>
            <field>
              <name>LATENCY</name>
              <description>Latency</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>PRFTEN</name>
              <description>Prefetch enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ICEN</name>
              <description>Instruction cache enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ICRST</name>
              <description>Instruction cache reset</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EMPTY</name>
              <description>Flash User area empty</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_SWEN</name>
              <description>Debug access software
              enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR</name>
          <displayName>KEYR</displayName>
          <description>Flash key register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>KEYR</name>
              <description>KEYR</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OPTKEYR</name>
          <displayName>OPTKEYR</displayName>
          <description>Option byte key register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OPTKEYR</name>
              <description>Option byte key</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>Status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EOP</name>
              <description>End of operation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPERR</name>
              <description>Operation error</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PROGERR</name>
              <description>Programming error</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WRPERR</name>
              <description>Write protected error</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PGAERR</name>
              <description>Programming alignment
              error</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SIZERR</name>
              <description>Size error</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PGSERR</name>
              <description>Programming sequence error</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MISERR</name>
              <description>Fast programming data miss
              error</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FASTERR</name>
              <description>Fast programming error</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RDERR</name>
              <description>PCROP read error</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPTVERR</name>
              <description>Option and Engineering bits loading
              validity error</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BSY</name>
              <description>Busy</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CFGBSY</name>
              <description>Programming or erase configuration
              busy.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Flash control register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xC0000000</resetValue>
          <fields>
            <field>
              <name>PG</name>
              <description>Programming</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PER</name>
              <description>Page erase</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MER</name>
              <description>Mass erase</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PNB</name>
              <description>Page number</description>
              <bitOffset>3</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
            <field>
              <name>STRT</name>
              <description>Start</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPTSTRT</name>
              <description>Options modification start</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FSTPG</name>
              <description>Fast programming</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EOPIE</name>
              <description>End of operation interrupt
              enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ERRIE</name>
              <description>Error interrupt enable</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RDERRIE</name>
              <description>PCROP read error interrupt
              enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OBL_LAUNCH</name>
              <description>Force the option byte
              loading</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SEC_PROT</name>
              <description>Securable memory area protection
              enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPTLOCK</name>
              <description>Options Lock</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LOCK</name>
              <description>FLASH_CR Lock</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ECCR</name>
          <displayName>ECCR</displayName>
          <description>Flash ECC register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ADDR_ECC</name>
              <description>ECC fail address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SYSF_ECC</name>
              <description>ECC fail for Corrected ECC Error or
              Double ECC Error in info block</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ECCIE</name>
              <description>ECC correction interrupt
              enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ECCC</name>
              <description>ECC correction</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ECCD</name>
              <description>ECC detection</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OPTR</name>
          <displayName>OPTR</displayName>
          <description>Flash option register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>RDP</name>
              <description>Read protection level</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>BOREN</name>
              <description>BOR reset Level</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BORF_LEV</name>
              <description>These bits contain the VDD supply level
              threshold that activates the reset</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>BORR_LEV</name>
              <description>These bits contain the VDD supply level
              threshold that releases the reset.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>nRST_STOP</name>
              <description>nRST_STOP</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>nRST_STDBY</name>
              <description>nRST_STDBY</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>nRSTS_HDW</name>
              <description>nRSTS_HDW</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDWG_SW</name>
              <description>Independent watchdog
              selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IWDG_STOP</name>
              <description>Independent watchdog counter freeze in
              Stop mode</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IWDG_STDBY</name>
              <description>Independent watchdog counter freeze in
              Standby mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WWDG_SW</name>
              <description>Window watchdog selection</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RAM_PARITY_CHECK</name>
              <description>SRAM parity check control</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>nBOOT_SEL</name>
              <description>nBOOT_SEL</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>nBOOT1</name>
              <description>Boot configuration</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>nBOOT0</name>
              <description>nBOOT0 option bit</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NRST_MODE</name>
              <description>NRST_MODE</description>
              <bitOffset>27</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>IRHEN</name>
              <description>Internal reset holder enable
              bit</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PCROP1ASR</name>
          <displayName>PCROP1ASR</displayName>
          <description>Flash PCROP zone A Start address
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>PCROP1A_STRT</name>
              <description>PCROP1A area start offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PCROP1AER</name>
          <displayName>PCROP1AER</displayName>
          <description>Flash PCROP zone A End address
          register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>PCROP1A_END</name>
              <description>PCROP1A area end offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>PCROP_RDP</name>
              <description>PCROP area preserved when RDP level
              decreased</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>WRP1AR</name>
          <displayName>WRP1AR</displayName>
          <description>Flash WRP area A address
          register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>WRP1A_STRT</name>
              <description>WRP area A start offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
            <field>
              <name>WRP1A_END</name>
              <description>WRP area A end offset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>WRP1BR</name>
          <displayName>WRP1BR</displayName>
          <description>Flash WRP area B address
          register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>WRP1B_STRT</name>
              <description>WRP area B start offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
            <field>
              <name>WRP1B_END</name>
              <description>WRP area B end offset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PCROP1BSR</name>
          <displayName>PCROP1BSR</displayName>
          <description>Flash PCROP zone B Start address
          register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>PCROP1B_STRT</name>
              <description>PCROP1B area start offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PCROP1BER</name>
          <displayName>PCROP1BER</displayName>
          <description>Flash PCROP zone B End address
          register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>PCROP1B_END</name>
              <description>PCROP1B area end offset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SECR</name>
          <displayName>SECR</displayName>
          <description>Flash Security register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xF0000000</resetValue>
          <fields>
            <field>
              <name>SEC_SIZE</name>
              <description>Securable memory area size</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
            <field>
              <name>BOOT_LOCK</name>
              <description>used to force boot from user
              area</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DBG</name>
      <description>Debug support</description>
      <groupName>DBG</groupName>
      <baseAddress>0x40015800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>IDCODE</name>
          <displayName>IDCODE</displayName>
          <description>MCU Device ID Code Register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0</resetValue>
          <fields>
            <field>
              <name>DEV_ID</name>
              <description>Device Identifier</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>REV_ID</name>
              <description>Revision Identifier</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Debug MCU Configuration
          Register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0</resetValue>
          <fields>
            <field>
              <name>DBG_STOP</name>
              <description>Debug Stop Mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_STANDBY</name>
              <description>Debug Standby Mode</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_FZ1</name>
          <displayName>APB_FZ1</displayName>
          <description>DBG APB freeze register 1</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0</resetValue>
          <fields>
            <field>
              <name>DBG_TIMER2_STOP</name>
              <description>Debug Timer 2 stopped when Core is
              halted</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM3_STOP</name>
              <description>TIM3 counter stopped when core is
              halted</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIMER6_STOP</name>
              <description>Debug Timer 6 stopped when Core is
              halted</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM7_STOP</name>
              <description>TIM7 counter stopped when core is
              halted</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_RTC_STOP</name>
              <description>Debug RTC stopped when Core is
              halted</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_WWDG_STOP</name>
              <description>Debug Window Wachdog stopped when Core
              is halted</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_IWDG_STOP</name>
              <description>Debug Independent Wachdog stopped when
              Core is halted</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_I2C1_STOP</name>
              <description>I2C1 SMBUS timeout mode stopped when
              core is halted</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_LPTIM2_STOP</name>
              <description>Clocking of LPTIMER2 counter when the
              core is halted</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_LPTIM1_STOP</name>
              <description>Clocking of LPTIMER1 counter when the
              core is halted</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_FZ2</name>
          <displayName>APB_FZ2</displayName>
          <description>DBG APB freeze register 2</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0</resetValue>
          <fields>
            <field>
              <name>DBG_TIM1_STOP</name>
              <description>DBG_TIM1_STOP</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM14_STOP</name>
              <description>DBG_TIM14_STOP</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM15_STOP</name>
              <description>DBG_TIM15_STOP</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM16_STOP</name>
              <description>DBG_TIM16_STOP</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBG_TIM17_STOP</name>
              <description>DBG_TIM17_STOP</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>RCC</name>
      <description>Reset and clock control</description>
      <groupName>RCC</groupName>
      <baseAddress>0x40021000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>RCC</name>
        <description>RCC global interrupt</description>
        <value>4</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Clock control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000063</resetValue>
          <fields>
            <field>
              <name>HSION</name>
              <description>HSI16 clock enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIKERON</name>
              <description>HSI16 always enable for peripheral
              kernels</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIRDY</name>
              <description>HSI16 clock ready flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIDIV</name>
              <description>HSI16 clock division
              factor</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>HSEON</name>
              <description>HSE clock enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSERDY</name>
              <description>HSE clock ready flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSEBYP</name>
              <description>HSE crystal oscillator
              bypass</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CSSON</name>
              <description>Clock security system
              enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLON</name>
              <description>PLL enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLRDY</name>
              <description>PLL clock ready flag</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICSCR</name>
          <displayName>ICSCR</displayName>
          <description>Internal clock sources calibration
          register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x10000000</resetValue>
          <fields>
            <field>
              <name>HSICAL</name>
              <description>HSI16 clock calibration</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>HSITRIM</name>
              <description>HSI16 clock trimming</description>
              <bitOffset>8</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CFGR</name>
          <displayName>CFGR</displayName>
          <description>Clock configuration register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MCOPRE</name>
              <description>Microcontroller clock output
              prescaler</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MCOSEL</name>
              <description>Microcontroller clock
              output</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPRE</name>
              <description>APB prescaler</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HPRE</name>
              <description>AHB prescaler</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWS</name>
              <description>System clock switch status</description>
              <bitOffset>3</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SW</name>
              <description>System clock switch</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PLLSYSCFGR</name>
          <displayName>PLLSYSCFGR</displayName>
          <description>PLL configuration register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00001000</resetValue>
          <fields>
            <field>
              <name>PLLSRC</name>
              <description>PLL input clock source</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PLLM</name>
              <description>Division factor M of the PLL input clock
              divider</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>PLLN</name>
              <description>PLL frequency multiplication factor
              N</description>
              <bitOffset>8</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
            <field>
              <name>PLLPEN</name>
              <description>PLLPCLK clock output
              enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLP</name>
              <description>PLL VCO division factor P for PLLPCLK
              clock output</description>
              <bitOffset>17</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>PLLQEN</name>
              <description>PLLQCLK clock output
              enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLQ</name>
              <description>PLL VCO division factor Q for PLLQCLK
              clock output</description>
              <bitOffset>25</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>PLLREN</name>
              <description>PLLRCLK clock output
              enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLR</name>
              <description>PLL VCO division factor R for PLLRCLK
              clock output</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CIER</name>
          <displayName>CIER</displayName>
          <description>Clock interrupt enable
          register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LSIRDYIE</name>
              <description>LSI ready interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSERDYIE</name>
              <description>LSE ready interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIRDYIE</name>
              <description>HSI ready interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSERDYIE</name>
              <description>HSE ready interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLSYSRDYIE</name>
              <description>PLL ready interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CIFR</name>
          <displayName>CIFR</displayName>
          <description>Clock interrupt flag register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LSIRDYF</name>
              <description>LSI ready interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSERDYF</name>
              <description>LSE ready interrupt flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIRDYF</name>
              <description>HSI ready interrupt flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSERDYF</name>
              <description>HSE ready interrupt flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLSYSRDYF</name>
              <description>PLL ready interrupt flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CSSF</name>
              <description>Clock security system interrupt
              flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSECSSF</name>
              <description>LSE Clock security system interrupt
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CICR</name>
          <displayName>CICR</displayName>
          <description>Clock interrupt clear register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LSIRDYC</name>
              <description>LSI ready interrupt clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSERDYC</name>
              <description>LSE ready interrupt clear</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSIRDYC</name>
              <description>HSI ready interrupt clear</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HSERDYC</name>
              <description>HSE ready interrupt clear</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PLLSYSRDYC</name>
              <description>PLL ready interrupt clear</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CSSC</name>
              <description>Clock security system interrupt
              clear</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSECSSC</name>
              <description>LSE Clock security system interrupt
              clear</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AHBRSTR</name>
          <displayName>AHBRSTR</displayName>
          <description>AHB peripheral reset register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMARST</name>
              <description>DMA1 reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FLASHRST</name>
              <description>FLITF reset</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CRCRST</name>
              <description>CRC reset</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AESRST</name>
              <description>AES hardware accelerator
              reset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RNGRST</name>
              <description>Random number generator
              reset</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IOPRSTR</name>
          <displayName>IOPRSTR</displayName>
          <description>GPIO reset register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IOPARST</name>
              <description>I/O port A reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPBRST</name>
              <description>I/O port B reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPCRST</name>
              <description>I/O port C reset</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPDRST</name>
              <description>I/O port D reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPFRST</name>
              <description>I/O port F reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBRSTR1</name>
          <displayName>APBRSTR1</displayName>
          <description>APB peripheral reset register
          1</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM2RST</name>
              <description>TIM2 timer reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM3RST</name>
              <description>TIM3 timer reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM6RST</name>
              <description>TIM6 timer reset</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM7RST</name>
              <description>TIM7 timer reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI2RST</name>
              <description>SPI2 reset</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART2RST</name>
              <description>USART2 reset</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART3RST</name>
              <description>USART3 reset</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART4RST</name>
              <description>USART4 reset</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPUART1RST</name>
              <description>LPUART1 reset</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C1RST</name>
              <description>I2C1 reset</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C2RST</name>
              <description>I2C2 reset</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CECRST</name>
              <description>HDMI CEC reset</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD1RST</name>
              <description>UCPD1 reset</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD2RST</name>
              <description>UCPD2 reset</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBGRST</name>
              <description>Debug support reset</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PWRRST</name>
              <description>Power interface reset</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DAC1RST</name>
              <description>DAC1 interface reset</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM2RST</name>
              <description>Low Power Timer 2 reset</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM1RST</name>
              <description>Low Power Timer 1 reset</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBRSTR2</name>
          <displayName>APBRSTR2</displayName>
          <description>APB peripheral reset register
          2</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SYSCFGRST</name>
              <description>SYSCFG, COMP and VREFBUF
              reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1RST</name>
              <description>TIM1 timer reset</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI1RST</name>
              <description>SPI1 reset</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART1RST</name>
              <description>USART1 reset</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM14RST</name>
              <description>TIM14 timer reset</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM15RST</name>
              <description>TIM15 timer reset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM16RST</name>
              <description>TIM16 timer reset</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM17RST</name>
              <description>TIM17 timer reset</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADCRST</name>
              <description>ADC reset</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IOPENR</name>
          <displayName>IOPENR</displayName>
          <description>GPIO clock enable register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IOPAEN</name>
              <description>I/O port A clock enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPBEN</name>
              <description>I/O port B clock enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPCEN</name>
              <description>I/O port C clock enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPDEN</name>
              <description>I/O port D clock enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPFEN</name>
              <description>I/O port F clock enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AHBENR</name>
          <displayName>AHBENR</displayName>
          <description>AHB peripheral clock enable
          register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAEN</name>
              <description>DMA clock enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FLASHEN</name>
              <description>Flash memory interface clock
              enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CRCEN</name>
              <description>CRC clock enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AESEN</name>
              <description>AES hardware accelerator</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RNGEN</name>
              <description>Random number generator clock
              enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBENR1</name>
          <displayName>APBENR1</displayName>
          <description>APB peripheral clock enable register
          1</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM2EN</name>
              <description>TIM2 timer clock enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM3EN</name>
              <description>TIM3 timer clock enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM6EN</name>
              <description>TIM6 timer clock enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM7EN</name>
              <description>TIM7 timer clock enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTCAPBEN</name>
              <description>RTC APB clock enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WWDGEN</name>
              <description>WWDG clock enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI2EN</name>
              <description>SPI2 clock enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART2EN</name>
              <description>USART2 clock enable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART3EN</name>
              <description>USART3 clock enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART4EN</name>
              <description>USART4 clock enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPUART1EN</name>
              <description>LPUART1 clock enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C1EN</name>
              <description>I2C1 clock enable</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C2EN</name>
              <description>I2C2 clock enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CECEN</name>
              <description>HDMI CEC clock enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD1EN</name>
              <description>UCPD1 clock enable</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD2EN</name>
              <description>UCPD2 clock enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBGEN</name>
              <description>Debug support clock enable</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PWREN</name>
              <description>Power interface clock
              enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DAC1EN</name>
              <description>DAC1 interface clock
              enable</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM2EN</name>
              <description>LPTIM2 clock enable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM1EN</name>
              <description>LPTIM1 clock enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBENR2</name>
          <displayName>APBENR2</displayName>
          <description>APB peripheral clock enable register
          2</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SYSCFGEN</name>
              <description>SYSCFG, COMP and VREFBUF clock
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1EN</name>
              <description>TIM1 timer clock enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI1EN</name>
              <description>SPI1 clock enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART1EN</name>
              <description>USART1 clock enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM14EN</name>
              <description>TIM14 timer clock enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM15EN</name>
              <description>TIM15 timer clock enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM16EN</name>
              <description>TIM16 timer clock enable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM17EN</name>
              <description>TIM16 timer clock enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADCEN</name>
              <description>ADC clock enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IOPSMENR</name>
          <displayName>IOPSMENR</displayName>
          <description>GPIO in Sleep mode clock enable
          register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IOPASMEN</name>
              <description>I/O port A clock enable during Sleep
              mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPBSMEN</name>
              <description>I/O port B clock enable during Sleep
              mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPCSMEN</name>
              <description>I/O port C clock enable during Sleep
              mode</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPDSMEN</name>
              <description>I/O port D clock enable during Sleep
              mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IOPFSMEN</name>
              <description>I/O port F clock enable during Sleep
              mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AHBSMENR</name>
          <displayName>AHBSMENR</displayName>
          <description>AHB peripheral clock enable in Sleep mode
          register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMASMEN</name>
              <description>DMA clock enable during Sleep
              mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FLASHSMEN</name>
              <description>Flash memory interface clock enable
              during Sleep mode</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SRAMSMEN</name>
              <description>SRAM clock enable during Sleep
              mode</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CRCSMEN</name>
              <description>CRC clock enable during Sleep
              mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AESSMEN</name>
              <description>AES hardware accelerator clock enable
              during Sleep mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RNGSMEN</name>
              <description>Random number generator clock enable
              during Sleep mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBSMENR1</name>
          <displayName>APBSMENR1</displayName>
          <description>APB peripheral clock enable in Sleep mode
          register 1</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM2SMEN</name>
              <description>TIM2 timer clock enable during Sleep
              mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM3SMEN</name>
              <description>TIM3 timer clock enable during Sleep
              mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM6SMEN</name>
              <description>TIM6 timer clock enable during Sleep
              mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM7SMEN</name>
              <description>TIM7 timer clock enable during Sleep
              mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTCAPBSMEN</name>
              <description>RTC APB clock enable during Sleep
              mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WWDGSMEN</name>
              <description>WWDG clock enable during Sleep
              mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI2SMEN</name>
              <description>SPI2 clock enable during Sleep
              mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART2SMEN</name>
              <description>USART2 clock enable during Sleep
              mode</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART3SMEN</name>
              <description>USART3 clock enable during Sleep
              mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART4SMEN</name>
              <description>USART4 clock enable during Sleep
              mode</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPUART1SMEN</name>
              <description>LPUART1 clock enable during Sleep
              mode</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C1SMEN</name>
              <description>I2C1 clock enable during Sleep
              mode</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C2SMEN</name>
              <description>I2C2 clock enable during Sleep
              mode</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CECSMEN</name>
              <description>HDMI CEC clock enable during Sleep
              mode</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD1SMEN</name>
              <description>UCPD1 clock enable during Sleep
              mode</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD2SMEN</name>
              <description>UCPD2 clock enable during Sleep
              mode</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DBGSMEN</name>
              <description>Debug support clock enable during Sleep
              mode</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PWRSMEN</name>
              <description>Power interface clock enable during
              Sleep mode</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DAC1SMEN</name>
              <description>DAC1 interface clock enable during Sleep
              mode</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM2SMEN</name>
              <description>Low Power Timer 2 clock enable during
              Sleep mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM1SMEN</name>
              <description>Low Power Timer 1 clock enable during
              Sleep mode</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>APBSMENR2</name>
          <displayName>APBSMENR2</displayName>
          <description>APB peripheral clock enable in Sleep mode
          register 2</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SYSCFGSMEN</name>
              <description>SYSCFG, COMP and VREFBUF clock enable
              during Sleep mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1SMEN</name>
              <description>TIM1 timer clock enable during Sleep
              mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPI1SMEN</name>
              <description>SPI1 clock enable during Sleep
              mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART1SMEN</name>
              <description>USART1 clock enable during Sleep
              mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM14SMEN</name>
              <description>TIM14 timer clock enable during Sleep
              mode</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM15SMEN</name>
              <description>TIM15 timer clock enable during Sleep
              mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM16SMEN</name>
              <description>TIM16 timer clock enable during Sleep
              mode</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM17SMEN</name>
              <description>TIM16 timer clock enable during Sleep
              mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADCSMEN</name>
              <description>ADC clock enable during Sleep
              mode</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCIPR</name>
          <displayName>CCIPR</displayName>
          <description>Peripherals independent clock configuration
          register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>USART1SEL</name>
              <description>USART1 clock source
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>USART2SEL</name>
              <description>USART2 clock source
              selection</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CECSEL</name>
              <description>HDMI CEC clock source
              selection</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPUART1SEL</name>
              <description>LPUART1 clock source
              selection</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>I2C1SEL</name>
              <description>I2C1 clock source
              selection</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>I2S2SEL</name>
              <description>I2S1 clock source
              selection</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>LPTIM1SEL</name>
              <description>LPTIM1 clock source
              selection</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>LPTIM2SEL</name>
              <description>LPTIM2 clock source
              selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TIM1SEL</name>
              <description>TIM1 clock source
              selection</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM15SEL</name>
              <description>TIM15 clock source
              selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RNGSEL</name>
              <description>RNG clock source selection</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>RNGDIV</name>
              <description>Division factor of RNG clock
              divider</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ADCSEL</name>
              <description>ADCs clock source
              selection</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BDCR</name>
          <displayName>BDCR</displayName>
          <description>RTC domain control register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LSEON</name>
              <description>LSE oscillator enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSERDY</name>
              <description>LSE oscillator ready</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSEBYP</name>
              <description>LSE oscillator bypass</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSEDRV</name>
              <description>LSE oscillator drive
              capability</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>LSECSSON</name>
              <description>CSS on LSE enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSECSSD</name>
              <description>CSS on LSE failure
              Detection</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTCSEL</name>
              <description>RTC clock source selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>RTCEN</name>
              <description>RTC clock enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BDRST</name>
              <description>RTC domain software reset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSCOEN</name>
              <description>Low-speed clock output (LSCO)
              enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSCOSEL</name>
              <description>Low-speed clock output
              selection</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CSR</name>
          <displayName>CSR</displayName>
          <description>Control/status register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LSION</name>
              <description>LSI oscillator enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSIRDY</name>
              <description>LSI oscillator ready</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RMVF</name>
              <description>Remove reset flags</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OBLRSTF</name>
              <description>Option byte loader reset
              flag</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINRSTF</name>
              <description>Pin reset flag</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PWRRSTF</name>
              <description>BOR or POR/PDR flag</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SFTRSTF</name>
              <description>Software reset flag</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IWDGRSTF</name>
              <description>Independent window watchdog reset
              flag</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WWDGRSTF</name>
              <description>Window watchdog reset flag</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPWRRSTF</name>
              <description>Low-power reset flag</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>PWR</name>
      <description>Power control</description>
      <groupName>PWR</groupName>
      <baseAddress>0x40007000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>PVD</name>
        <description>Power voltage detector interrupt</description>
        <value>1</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>Power control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000200</resetValue>
          <fields>
            <field>
              <name>LPR</name>
              <description>Low-power run</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>VOS</name>
              <description>Voltage scaling range
              selection</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DBP</name>
              <description>Disable backup domain write
              protection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPD_LPSLP</name>
              <description>Flash memory powered down during
              Low-power sleep mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPD_LPRUN</name>
              <description>Flash memory powered down during
              Low-power run mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPD_STOP</name>
              <description>Flash memory powered down during Stop
              mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPMS</name>
              <description>Low-power mode selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>Power control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PVDE</name>
              <description>Power voltage detector
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PVDFT</name>
              <description>Power voltage detector falling threshold
              selection</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>PVDRT</name>
              <description>Power voltage detector rising threshold
              selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR3</name>
          <displayName>CR3</displayName>
          <description>Power control register 3</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0X00008000</resetValue>
          <fields>
            <field>
              <name>EWUP1</name>
              <description>Enable Wakeup pin WKUP1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EWUP2</name>
              <description>Enable Wakeup pin WKUP2</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EWUP4</name>
              <description>Enable Wakeup pin WKUP4</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EWUP5</name>
              <description>Enable WKUP5 wakeup pin</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EWUP6</name>
              <description>Enable WKUP6 wakeup pin</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RRS</name>
              <description>SRAM retention in Standby
              mode</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ULPEN</name>
              <description>Enable the periodical sampling mode for
              PDR detection</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>APC</name>
              <description>Apply pull-up and pull-down
              configuration</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EIWUL</name>
              <description>Enable internal wakeup
              line</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR4</name>
          <displayName>CR4</displayName>
          <description>Power control register 4</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WP1</name>
              <description>Wakeup pin WKUP1 polarity</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WP2</name>
              <description>Wakeup pin WKUP2 polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WP4</name>
              <description>Wakeup pin WKUP4 polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WP5</name>
              <description>Wakeup pin WKUP5 polarity</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WP6</name>
              <description>WKUP6 wakeup pin polarity</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>VBE</name>
              <description>VBAT battery charging
              enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>VBRS</name>
              <description>VBAT battery charging resistor
              selection</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR1</name>
          <displayName>SR1</displayName>
          <description>Power status register 1</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WUF1</name>
              <description>Wakeup flag 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF2</name>
              <description>Wakeup flag 2</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF4</name>
              <description>Wakeup flag 4</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF5</name>
              <description>Wakeup flag 5</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF6</name>
              <description>Wakeup flag 6</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBF</name>
              <description>Standby flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUFI</name>
              <description>Wakeup flag internal</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR2</name>
          <displayName>SR2</displayName>
          <description>Power status register 2</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PVDO</name>
              <description>Power voltage detector
              output</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>VOSF</name>
              <description>Voltage scaling flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>REGLPF</name>
              <description>Low-power regulator flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>REGLPS</name>
              <description>Low-power regulator
              started</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FLASH_RDY</name>
              <description>Flash ready flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SCR</name>
          <displayName>SCR</displayName>
          <description>Power status clear register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CSBF</name>
              <description>Clear standby flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUF6</name>
              <description>Clear wakeup flag 6</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUF5</name>
              <description>Clear wakeup flag 5</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUF4</name>
              <description>Clear wakeup flag 4</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUF2</name>
              <description>Clear wakeup flag 2</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUF1</name>
              <description>Clear wakeup flag 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUCRA</name>
          <displayName>PUCRA</displayName>
          <description>Power Port A pull-up control
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PU15</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU14</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU13</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU12</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU11</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU10</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU9</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU8</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU7</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU6</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU5</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU4</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU3</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU2</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU1</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU0</name>
              <description>Port A pull-up bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PDCRA</name>
          <displayName>PDCRA</displayName>
          <description>Power Port A pull-down control
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PD15</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD14</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD13</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD12</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD11</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD10</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD9</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD8</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD7</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD6</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD5</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD4</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD3</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD2</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD1</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD0</name>
              <description>Port A pull-down bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUCRB</name>
          <displayName>PUCRB</displayName>
          <description>Power Port B pull-up control
          register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PU15</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU14</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU13</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU12</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU11</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU10</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU9</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU8</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU7</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU6</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU5</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU4</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU3</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU2</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU1</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU0</name>
              <description>Port B pull-up bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PDCRB</name>
          <displayName>PDCRB</displayName>
          <description>Power Port B pull-down control
          register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PD15</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD14</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD13</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD12</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD11</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD10</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD9</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD8</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD7</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD6</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD5</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD4</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD3</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD2</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD1</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD0</name>
              <description>Port B pull-down bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUCRC</name>
          <displayName>PUCRC</displayName>
          <description>Power Port C pull-up control
          register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PU15</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU14</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU13</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU12</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU11</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU10</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU9</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU8</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU7</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU6</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU5</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU4</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU3</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU2</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU1</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU0</name>
              <description>Port C pull-up bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PDCRC</name>
          <displayName>PDCRC</displayName>
          <description>Power Port C pull-down control
          register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PD15</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD14</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD13</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD12</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD11</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD10</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD9</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD8</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD7</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD6</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD5</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD4</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD3</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD2</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD1</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD0</name>
              <description>Port C pull-down bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUCRD</name>
          <displayName>PUCRD</displayName>
          <description>Power Port D pull-up control
          register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PU9</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU8</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU6</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU5</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU4</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU3</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU2</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU1</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU0</name>
              <description>Port D pull-up bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PDCRD</name>
          <displayName>PDCRD</displayName>
          <description>Power Port D pull-down control
          register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PD9</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD8</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD6</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD5</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD4</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD3</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD2</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD1</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD0</name>
              <description>Port D pull-down bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUCRF</name>
          <displayName>PUCRF</displayName>
          <description>Power Port F pull-up control
          register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PU2</name>
              <description>Port F pull-up bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU1</name>
              <description>Port F pull-up bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PU0</name>
              <description>Port F pull-up bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PDCRF</name>
          <displayName>PDCRF</displayName>
          <description>Power Port F pull-down control
          register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PD2</name>
              <description>Port F pull-down bit y
              (y=0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD1</name>
              <description>Port F pull-down bit y
              (y=0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PD0</name>
              <description>Port F pull-down bit y
              (y=0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DMA</name>
      <description>DMA controller</description>
      <groupName>DMA</groupName>
      <baseAddress>0x40020000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>DMA_Channel1</name>
        <description>DMA channel 1 interrupt</description>
        <value>9</value>
      </interrupt>
      <interrupt>
        <name>DMA_Channel2_3</name>
        <description>DMA channel 2 &amp; 3 interrupts</description>
        <value>10</value>
      </interrupt>
      <registers>
        <register>
          <name>ISR</name>
          <displayName>ISR</displayName>
          <description>low interrupt status register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>GIF0</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF1</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF2</name>
              <description>Channel half transfer flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF3</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF4</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF5</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF6</name>
              <description>Channel half transfer flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF7</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF8</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF9</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF10</name>
              <description>Channel half transfer flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF11</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF12</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF13</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF14</name>
              <description>Channel half transfer flag</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF15</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF16</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF17</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF18</name>
              <description>Channel half transfer flag</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF19</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF20</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF21</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF22</name>
              <description>Channel half transfer flag</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF23</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GIF24</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIF25</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIF26</name>
              <description>Channel half transfer flag</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIF27</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IFCR</name>
          <displayName>IFCR</displayName>
          <description>high interrupt status register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CGIF0</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF1</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF2</name>
              <description>Channel half transfer flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF3</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF4</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF5</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF6</name>
              <description>Channel half transfer flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF7</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF8</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF9</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF10</name>
              <description>Channel half transfer flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF11</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF12</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF13</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF14</name>
              <description>Channel half transfer flag</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF15</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF16</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF17</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF18</name>
              <description>Channel half transfer flag</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF19</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF20</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF21</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF22</name>
              <description>Channel half transfer flag</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF23</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CGIF24</name>
              <description>Channel global interrupt
              flag</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTCIF25</name>
              <description>Channel transfer complete
              flag</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHTIF26</name>
              <description>Channel half transfer flag</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTEIF27</name>
              <description>Channel transfer error
              flag</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR2</name>
          <displayName>CCR2</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR3</name>
          <displayName>CCR3</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR4</name>
          <displayName>CCR4</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR5</name>
          <displayName>CCR5</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR6</name>
          <displayName>CCR6</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR7</name>
          <displayName>CCR7</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>Channel enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer complete interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HTIE</name>
              <description>Half transfer interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEIE</name>
              <description>Transfer error interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Data transfer direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CIRC</name>
              <description>Circular mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PINC</name>
              <description>Peripheral increment mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MINC</name>
              <description>Memory increment mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PSIZE</name>
              <description>Peripheral size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MSIZE</name>
              <description>Memory size</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PL</name>
              <description>Channel priority level</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MEM2MEM</name>
              <description>Memory to memory mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR1</name>
          <displayName>CNDTR1</displayName>
          <description>DMA channel x number of data
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR2</name>
          <displayName>CNDTR2</displayName>
          <description>DMA channel x number of data
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR3</name>
          <displayName>CNDTR3</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR4</name>
          <displayName>CNDTR4</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR5</name>
          <displayName>CNDTR5</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR6</name>
          <displayName>CNDTR6</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNDTR7</name>
          <displayName>CNDTR7</displayName>
          <description>DMA channel x configuration
          register</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NDT</name>
              <description>Number of data to transfer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR1</name>
          <displayName>CPAR1</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR2</name>
          <displayName>CPAR2</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR3</name>
          <displayName>CPAR3</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR4</name>
          <displayName>CPAR4</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR5</name>
          <displayName>CPAR5</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR6</name>
          <displayName>CPAR6</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CPAR7</name>
          <displayName>CPAR7</displayName>
          <description>DMA channel x peripheral address
          register</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PA</name>
              <description>Peripheral address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR1</name>
          <displayName>CMAR1</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR2</name>
          <displayName>CMAR2</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR3</name>
          <displayName>CMAR3</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR4</name>
          <displayName>CMAR4</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR5</name>
          <displayName>CMAR5</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR6</name>
          <displayName>CMAR6</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMAR7</name>
          <displayName>CMAR7</displayName>
          <description>DMA channel x memory address
          register</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MA</name>
              <description>Memory address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DMAMUX</name>
      <description>DMAMUX</description>
      <groupName>DMAMUX</groupName>
      <baseAddress>0x40020800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>DMA_Channel4_5_6_7</name>
        <description>DMA channel 4, 5, 6 &amp; 7 and
        DMAMUX</description>
        <value>11</value>
      </interrupt>
      <registers>
        <register>
          <name>DMAMUX_C0CR</name>
          <displayName>DMAMUX_C0CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C1CR</name>
          <displayName>DMAMUX_C1CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C2CR</name>
          <displayName>DMAMUX_C2CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C3CR</name>
          <displayName>DMAMUX_C3CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C4CR</name>
          <displayName>DMAMUX_C4CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C5CR</name>
          <displayName>DMAMUX_C5CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_C6CR</name>
          <displayName>DMAMUX_C6CR</displayName>
          <description>DMAMux - DMA request line multiplexer
          channel x control register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAREQ_ID</name>
              <description>Input DMA request line
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SOIE</name>
              <description>Interrupt enable at synchronization
              event overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EGE</name>
              <description>Event generation
              enable/disable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SE</name>
              <description>Synchronous operating mode
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPOL</name>
              <description>Synchronization event type selector
              Defines the synchronization event on the selected
              synchronization input:</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>NBREQ</name>
              <description>Number of DMA requests to forward
              Defines the number of DMA requests forwarded before
              output event is generated. In synchronous mode, it
              also defines the number of DMA requests to forward
              after a synchronization event, then stop forwarding.
              The actual number of DMA requests forwarded is
              NBREQ+1. Note: This field can only be written when
              both SE and EGE bits are reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>SYNC_ID</name>
              <description>Synchronization input
              selected</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RG0CR</name>
          <displayName>DMAMUX_RG0CR</displayName>
          <description>DMAMux - DMA request generator channel x
          control register</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SIG_ID</name>
              <description>DMA request trigger input
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OIE</name>
              <description>Interrupt enable at trigger event
              overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GE</name>
              <description>DMA request generator channel
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GPOL</name>
              <description>DMA request generator trigger event type
              selection Defines the trigger event on the selected
              DMA request trigger input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>GNBREQ</name>
              <description>Number of DMA requests to generate
              Defines the number of DMA requests generated after a
              trigger event, then stop generating. The actual
              number of generated DMA requests is GNBREQ+1. Note:
              This field can only be written when GE bit is
              reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RG1CR</name>
          <displayName>DMAMUX_RG1CR</displayName>
          <description>DMAMux - DMA request generator channel x
          control register</description>
          <addressOffset>0x104</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SIG_ID</name>
              <description>DMA request trigger input
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OIE</name>
              <description>Interrupt enable at trigger event
              overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GE</name>
              <description>DMA request generator channel
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GPOL</name>
              <description>DMA request generator trigger event type
              selection Defines the trigger event on the selected
              DMA request trigger input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>GNBREQ</name>
              <description>Number of DMA requests to generate
              Defines the number of DMA requests generated after a
              trigger event, then stop generating. The actual
              number of generated DMA requests is GNBREQ+1. Note:
              This field can only be written when GE bit is
              reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RG2CR</name>
          <displayName>DMAMUX_RG2CR</displayName>
          <description>DMAMux - DMA request generator channel x
          control register</description>
          <addressOffset>0x108</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SIG_ID</name>
              <description>DMA request trigger input
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OIE</name>
              <description>Interrupt enable at trigger event
              overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GE</name>
              <description>DMA request generator channel
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GPOL</name>
              <description>DMA request generator trigger event type
              selection Defines the trigger event on the selected
              DMA request trigger input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>GNBREQ</name>
              <description>Number of DMA requests to generate
              Defines the number of DMA requests generated after a
              trigger event, then stop generating. The actual
              number of generated DMA requests is GNBREQ+1. Note:
              This field can only be written when GE bit is
              reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RG3CR</name>
          <displayName>DMAMUX_RG3CR</displayName>
          <description>DMAMux - DMA request generator channel x
          control register</description>
          <addressOffset>0x10C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SIG_ID</name>
              <description>DMA request trigger input
              selected</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OIE</name>
              <description>Interrupt enable at trigger event
              overrun</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GE</name>
              <description>DMA request generator channel
              enable/disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GPOL</name>
              <description>DMA request generator trigger event type
              selection Defines the trigger event on the selected
              DMA request trigger input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>GNBREQ</name>
              <description>Number of DMA requests to generate
              Defines the number of DMA requests generated after a
              trigger event, then stop generating. The actual
              number of generated DMA requests is GNBREQ+1. Note:
              This field can only be written when GE bit is
              reset.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RGSR</name>
          <displayName>DMAMUX_RGSR</displayName>
          <description>DMAMux - DMA request generator status
          register</description>
          <addressOffset>0x140</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OF</name>
              <description>Trigger event overrun flag The flag is
              set when a trigger event occurs on DMA request
              generator channel x, while the DMA request generator
              counter value is lower than GNBREQ. The flag is
              cleared by writing 1 to the corresponding COFx bit in
              DMAMUX_RGCFR register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_RGCFR</name>
          <displayName>DMAMUX_RGCFR</displayName>
          <description>DMAMux - DMA request generator clear flag
          register</description>
          <addressOffset>0x144</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>COF</name>
              <description>Clear trigger event overrun flag Upon
              setting, this bit clears the corresponding overrun
              flag OFx in the DMAMUX_RGCSR register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_CSR</name>
          <displayName>DMAMUX_CSR</displayName>
          <description>DMAMUX request line multiplexer interrupt
          channel status register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SOF</name>
              <description>Synchronization overrun event
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_CFR</name>
          <displayName>DMAMUX_CFR</displayName>
          <description>DMAMUX request line multiplexer interrupt
          clear flag register</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CSOF</name>
              <description>Clear synchronization overrun event
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_SIDR</name>
          <displayName>DMAMUX_SIDR</displayName>
          <description>DMAMUX size identification
          register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_IPIDR</name>
          <displayName>DMAMUX_IPIDR</displayName>
          <description>DMAMUX IP identification
          register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00100011</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>IP identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_VERR</name>
          <displayName>DMAMUX_VERR</displayName>
          <description>DMAMUX version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000011</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor IP revision</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major IP revision</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_HWCFGR1</name>
          <displayName>DMAMUX_HWCFGR1</displayName>
          <description>DMAMUX hardware configuration 1
          register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x04173907</resetValue>
          <fields>
            <field>
              <name>NUM_DMA_STREAMS</name>
              <description>number of DMA request line multiplexer
              (output) channels</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>NUM_DMA_PERIPH_REQ</name>
              <description>number of DMA request lines from
              peripherals</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>NUM_DMA_TRIG</name>
              <description>number of synchronization
              inputs</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>NUM_DMA_REQGEN</name>
              <description>number of DMA request generator
              channels</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAMUX_HWCFGR2</name>
          <displayName>DMAMUX_HWCFGR2</displayName>
          <description>DMAMUX hardware configuration 2
          register</description>
          <addressOffset>0x3EC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000017</resetValue>
          <fields>
            <field>
              <name>NUM_DMA_EXT_REQ</name>
              <description>Number of DMA request trigger
              inputs</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>GPIOA</name>
      <description>General-purpose I/Os</description>
      <groupName>GPIO</groupName>
      <baseAddress>0x50000000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>MODER</name>
          <displayName>MODER</displayName>
          <description>GPIO port mode register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xEBFFFFFF</resetValue>
          <fields>
            <field>
              <name>MODER15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OTYPER</name>
          <displayName>OTYPER</displayName>
          <description>GPIO port output type register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OT15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OSPEEDR</name>
          <displayName>OSPEEDR</displayName>
          <description>GPIO port output speed
          register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0C000000</resetValue>
          <fields>
            <field>
              <name>OSPEEDR15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUPDR</name>
          <displayName>PUPDR</displayName>
          <description>GPIO port pull-up/pull-down
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x24000000</resetValue>
          <fields>
            <field>
              <name>PUPDR15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IDR</name>
          <displayName>IDR</displayName>
          <description>GPIO port input data register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IDR15</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR14</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR13</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR12</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR11</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR10</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR9</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR8</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR7</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR6</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR5</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR4</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR3</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR2</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR1</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR0</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ODR</name>
          <displayName>ODR</displayName>
          <description>GPIO port output data register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ODR15</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR14</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR13</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR12</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR11</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR10</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR9</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR8</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR7</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR6</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR5</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR4</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR3</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR2</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR1</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR0</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BSRR</name>
          <displayName>BSRR</displayName>
          <description>GPIO port bit set/reset
          register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BR15</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR14</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR13</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR12</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR11</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR10</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR9</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR8</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR7</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR6</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR5</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR4</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR3</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR2</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR1</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR0</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS15</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS14</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS13</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS12</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS11</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS10</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS9</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS8</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS7</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS6</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS5</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS4</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS3</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS2</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS1</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS0</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>LCKR</name>
          <displayName>LCKR</displayName>
          <description>GPIO port configuration lock
          register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LCKK</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK15</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK14</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK13</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK12</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK11</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK10</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK9</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK8</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK7</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK6</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK5</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK4</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK3</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK2</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK1</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK0</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AFRL</name>
          <displayName>AFRL</displayName>
          <description>GPIO alternate function low
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AFSEL7</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL6</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL5</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL4</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL3</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL2</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL1</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL0</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AFRH</name>
          <displayName>AFRH</displayName>
          <description>GPIO alternate function high
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AFSEL15</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL14</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL13</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL12</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL11</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL10</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL9</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL8</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BRR</name>
          <displayName>BRR</displayName>
          <description>port bit reset register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BR0</name>
              <description>Port Reset bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR1</name>
              <description>Port Reset bit</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR2</name>
              <description>Port Reset bit</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR3</name>
              <description>Port Reset bit</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR4</name>
              <description>Port Reset bit</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR5</name>
              <description>Port Reset bit</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR6</name>
              <description>Port Reset bit</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR7</name>
              <description>Port Reset bit</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR8</name>
              <description>Port Reset bit</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR9</name>
              <description>Port Reset bit</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR10</name>
              <description>Port Reset bit</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR11</name>
              <description>Port Reset bit</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR12</name>
              <description>Port Reset bit</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR13</name>
              <description>Port Reset bit</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR14</name>
              <description>Port Reset bit</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR15</name>
              <description>Port Reset bit</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>GPIOB</name>
      <description>General-purpose I/Os</description>
      <groupName>GPIO</groupName>
      <baseAddress>0x50000400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>MODER</name>
          <displayName>MODER</displayName>
          <description>GPIO port mode register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>MODER15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODER0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OTYPER</name>
          <displayName>OTYPER</displayName>
          <description>GPIO port output type register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OT15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OT0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OSPEEDR</name>
          <displayName>OSPEEDR</displayName>
          <description>GPIO port output speed
          register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OSPEEDR15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSPEEDR0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PUPDR</name>
          <displayName>PUPDR</displayName>
          <description>GPIO port pull-up/pull-down
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PUPDR15</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR14</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR13</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR12</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR11</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR10</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR9</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR8</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR7</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR6</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR5</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR4</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR3</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR2</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR1</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PUPDR0</name>
              <description>Port x configuration bits (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IDR</name>
          <displayName>IDR</displayName>
          <description>GPIO port input data register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IDR15</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR14</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR13</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR12</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR11</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR10</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR9</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR8</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR7</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR6</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR5</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR4</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR3</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR2</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR1</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDR0</name>
              <description>Port input data (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ODR</name>
          <displayName>ODR</displayName>
          <description>GPIO port output data register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ODR15</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR14</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR13</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR12</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR11</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR10</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR9</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR8</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR7</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR6</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR5</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR4</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR3</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR2</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR1</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ODR0</name>
              <description>Port output data (y =
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BSRR</name>
          <displayName>BSRR</displayName>
          <description>GPIO port bit set/reset
          register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BR15</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR14</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR13</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR12</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR11</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR10</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR9</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR8</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR7</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR6</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR5</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR4</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR3</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR2</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR1</name>
              <description>Port x reset bit y (y =
              0..15)</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR0</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS15</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS14</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS13</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS12</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS11</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS10</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS9</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS8</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS7</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS6</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS5</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS4</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS3</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS2</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS1</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BS0</name>
              <description>Port x set bit y (y=
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>LCKR</name>
          <displayName>LCKR</displayName>
          <description>GPIO port configuration lock
          register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LCKK</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK15</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK14</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK13</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK12</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK11</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK10</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK9</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK8</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK7</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK6</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK5</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK4</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK3</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK2</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK1</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LCK0</name>
              <description>Port x lock bit y (y=
              0..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AFRL</name>
          <displayName>AFRL</displayName>
          <description>GPIO alternate function low
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AFSEL7</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL6</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL5</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL4</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL3</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL2</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL1</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL0</name>
              <description>Alternate function selection for port x
              bit y (y = 0..7)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AFRH</name>
          <displayName>AFRH</displayName>
          <description>GPIO alternate function high
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AFSEL15</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL14</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL13</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL12</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL11</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL10</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL9</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>AFSEL8</name>
              <description>Alternate function selection for port x
              bit y (y = 8..15)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BRR</name>
          <displayName>BRR</displayName>
          <description>port bit reset register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BR0</name>
              <description>Port Reset bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR1</name>
              <description>Port Reset bit</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR2</name>
              <description>Port Reset bit</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR3</name>
              <description>Port Reset bit</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR4</name>
              <description>Port Reset bit</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR5</name>
              <description>Port Reset bit</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR6</name>
              <description>Port Reset bit</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR7</name>
              <description>Port Reset bit</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR8</name>
              <description>Port Reset bit</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR9</name>
              <description>Port Reset bit</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR10</name>
              <description>Port Reset bit</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR11</name>
              <description>Port Reset bit</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR12</name>
              <description>Port Reset bit</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR13</name>
              <description>Port Reset bit</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR14</name>
              <description>Port Reset bit</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR15</name>
              <description>Port Reset bit</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="GPIOB">
      <name>GPIOC</name>
      <baseAddress>0x50000800</baseAddress>
    </peripheral>
    <peripheral derivedFrom="GPIOB">
      <name>GPIOD</name>
      <baseAddress>0x50000C00</baseAddress>
    </peripheral>
    <peripheral derivedFrom="GPIOB">
      <name>GPIOF</name>
      <baseAddress>0x50001400</baseAddress>
    </peripheral>
    <peripheral>
      <name>AES</name>
      <description>Advanced encryption standard hardware
      accelerator 1</description>
      <groupName>AES</groupName>
      <baseAddress>0x40026000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>AES_RNG</name>
        <description>AES and RNG global interrupts</description>
        <value>31</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>NPBLB</name>
              <description>Number of padding bytes in last block of
              payload</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>KEYSIZE</name>
              <description>Key size selection</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHMOD2</name>
              <description>AES chaining mode Bit2</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GCMPH</name>
              <description>Used only for GCM, CCM and GMAC
              algorithms and has no effect when other algorithms
              are selected</description>
              <bitOffset>13</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DMAOUTEN</name>
              <description>Enable DMA management of data output
              phase</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAINEN</name>
              <description>Enable DMA management of data input
              phase</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ERRIE</name>
              <description>Error interrupt enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCFIE</name>
              <description>CCF flag interrupt enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ERRC</name>
              <description>Error clear</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCFC</name>
              <description>Computation Complete Flag
              Clear</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CHMOD10</name>
              <description>AES chaining mode Bit1
              Bit0</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MODE</name>
              <description>AES operating mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DATATYPE</name>
              <description>Data type selection (for data in and
              data out to/from the cryptographic
              block)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>EN</name>
              <description>AES enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BUSY</name>
              <description>Busy flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WRERR</name>
              <description>Write error flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RDERR</name>
              <description>Read error flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCF</name>
              <description>Computation complete flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DINR</name>
          <displayName>DINR</displayName>
          <description>data input register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_DINR</name>
              <description>Data Input Register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DOUTR</name>
          <displayName>DOUTR</displayName>
          <description>data output register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_DOUTR</name>
              <description>Data output register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR0</name>
          <displayName>KEYR0</displayName>
          <description>key register 0</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR0</name>
              <description>Data Output Register (LSB key
              [31:0])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR1</name>
          <displayName>KEYR1</displayName>
          <description>key register 1</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR1</name>
              <description>AES key register (key
              [63:32])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR2</name>
          <displayName>KEYR2</displayName>
          <description>key register 2</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR2</name>
              <description>AES key register (key
              [95:64])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR3</name>
          <displayName>KEYR3</displayName>
          <description>key register 3</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR3</name>
              <description>AES key register (MSB key
              [127:96])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IVR0</name>
          <displayName>IVR0</displayName>
          <description>initialization vector register
          0</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_IVR0</name>
              <description>initialization vector register (LSB IVR
              [31:0])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IVR1</name>
          <displayName>IVR1</displayName>
          <description>initialization vector register
          1</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_IVR1</name>
              <description>Initialization Vector Register (IVR
              [63:32])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IVR2</name>
          <displayName>IVR2</displayName>
          <description>initialization vector register
          2</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_IVR2</name>
              <description>Initialization Vector Register (IVR
              [95:64])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IVR3</name>
          <displayName>IVR3</displayName>
          <description>initialization vector register
          3</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_IVR3</name>
              <description>Initialization Vector Register (MSB IVR
              [127:96])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR4</name>
          <displayName>KEYR4</displayName>
          <description>key register 4</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR4</name>
              <description>AES key register (MSB key
              [159:128])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR5</name>
          <displayName>KEYR5</displayName>
          <description>key register 5</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR5</name>
              <description>AES key register (MSB key
              [191:160])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR6</name>
          <displayName>KEYR6</displayName>
          <description>key register 6</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR6</name>
              <description>AES key register (MSB key
              [223:192])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>KEYR7</name>
          <displayName>KEYR7</displayName>
          <description>key register 7</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_KEYR7</name>
              <description>AES key register (MSB key
              [255:224])</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP0R</name>
          <displayName>SUSP0R</displayName>
          <description>AES suspend register 0</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP0R</name>
              <description>AES suspend register 0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP1R</name>
          <displayName>SUSP1R</displayName>
          <description>AES suspend register 1</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP1R</name>
              <description>AES suspend register 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP2R</name>
          <displayName>SUSP2R</displayName>
          <description>AES suspend register 2</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP2R</name>
              <description>AES suspend register 2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP3R</name>
          <displayName>SUSP3R</displayName>
          <description>AES suspend register 3</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP3R</name>
              <description>AES suspend register 3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP4R</name>
          <displayName>SUSP4R</displayName>
          <description>AES suspend register 4</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP4R</name>
              <description>AES suspend register 4</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP5R</name>
          <displayName>SUSP5R</displayName>
          <description>AES suspend register 5</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP5R</name>
              <description>AES suspend register 5</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP6R</name>
          <displayName>SUSP6R</displayName>
          <description>AES suspend register 6</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP6R</name>
              <description>AES suspend register 6</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SUSP7R</name>
          <displayName>SUSP7R</displayName>
          <description>AES suspend register 7</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>AES_SUSP7R</name>
              <description>AES suspend register 7</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFR</name>
          <displayName>HWCFR</displayName>
          <description>AES hardware configuration
          register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>CFG4</name>
              <description>HW Generic 4</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG3</name>
              <description>HW Generic 3</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG2</name>
              <description>HW Generic 2</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG1</name>
              <description>HW Generic 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>AES version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>MAJREV</name>
              <description>Major revision</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MINREV</name>
              <description>Minor revision</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>AES identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00170023</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>Identification code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>AES size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00170023</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>Size Identification code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>RNG</name>
      <description>Random number generator</description>
      <groupName>RNG</groupName>
      <baseAddress>0x40025000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RNGEN</name>
              <description>Random number generator
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IE</name>
              <description>Interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CED</name>
              <description>Clock error detection</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BYP</name>
              <description>Bypass mode enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SEIS</name>
              <description>Seed error interrupt
              status</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CEIS</name>
              <description>Clock error interrupt
              status</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SECS</name>
              <description>Seed error current status</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CECS</name>
              <description>Clock error current status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DRDY</name>
              <description>Data ready</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DR</name>
          <displayName>DR</displayName>
          <description>data register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RNDATA</name>
              <description>Random data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>CRC</name>
      <description>Cyclic redundancy check calculation
      unit</description>
      <groupName>CRC</groupName>
      <baseAddress>0x40023000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>CEC</name>
        <description>CEC global interrupt</description>
        <value>30</value>
      </interrupt>
      <registers>
        <register>
          <name>DR</name>
          <displayName>DR</displayName>
          <description>Data register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>DR</name>
              <description>Data register bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IDR</name>
          <displayName>IDR</displayName>
          <description>Independent data register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IDR</name>
              <description>General-purpose 32-bit data register
              bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>REV_OUT</name>
              <description>Reverse output data</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REV_IN</name>
              <description>Reverse input data</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>POLYSIZE</name>
              <description>Polynomial size</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET</name>
              <description>RESET bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INIT</name>
          <displayName>INIT</displayName>
          <description>Initial CRC value</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>CRC_INIT</name>
              <description>Programmable initial CRC
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>POL</name>
          <displayName>POL</displayName>
          <description>polynomial</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x04C11DB7</resetValue>
          <fields>
            <field>
              <name>POL</name>
              <description>Programmable polynomial</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>EXTI</name>
      <description>External interrupt/event
      controller</description>
      <groupName>EXTI</groupName>
      <baseAddress>0x40021800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>EXTI0_1</name>
        <description>EXTI line 0 &amp; 1 interrupt</description>
        <value>5</value>
      </interrupt>
      <interrupt>
        <name>EXTI2_3</name>
        <description>EXTI line 2 &amp; 3 interrupt</description>
        <value>6</value>
      </interrupt>
      <interrupt>
        <name>EXTI4_15</name>
        <description>EXTI line 4 to 15 interrupt</description>
        <value>7</value>
      </interrupt>
      <registers>
        <register>
          <name>RTSR1</name>
          <displayName>RTSR1</displayName>
          <description>EXTI rising trigger selection
          register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TR0</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR1</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR2</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR3</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR4</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR5</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR6</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR7</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR8</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR9</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR10</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR11</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR12</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR13</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR14</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR15</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR16</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR17</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR18</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>FTSR1</name>
          <displayName>FTSR1</displayName>
          <description>EXTI falling trigger selection
          register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TR0</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR1</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR2</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR3</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR4</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR5</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR6</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR7</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR8</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR9</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR10</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR11</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR12</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR13</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR14</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR15</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR16</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR17</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TR18</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SWIER1</name>
          <displayName>SWIER1</displayName>
          <description>EXTI software interrupt event
          register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SWIER0</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER1</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER2</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER3</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER4</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER5</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER6</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER7</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER8</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER9</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER10</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER11</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER12</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER13</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER14</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER15</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER16</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER17</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWIER18</name>
              <description>Rising trigger event configuration bit
              of Configurable Event input</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RPR1</name>
          <displayName>RPR1</displayName>
          <description>EXTI rising edge pending
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RPIF0</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF1</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF2</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF3</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF4</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF5</name>
              <description>configurable event inputs x rising edge
              Pending bit</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF6</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF7</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF8</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF9</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF10</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF11</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF12</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF13</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF14</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF15</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF16</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF17</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RPIF18</name>
              <description>configurable event inputs x rising edge
              Pending bit.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>FPR1</name>
          <displayName>FPR1</displayName>
          <description>EXTI falling edge pending
          register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>FPIF0</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF1</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF2</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF3</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF4</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF5</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF6</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF7</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF8</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF9</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF10</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF11</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF12</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF13</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF14</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF15</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF16</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF17</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FPIF18</name>
              <description>configurable event inputs x falling edge
              pending bit.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EXTICR1</name>
          <displayName>EXTICR1</displayName>
          <description>EXTI external interrupt selection
          register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI0_7</name>
              <description>GPIO port selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI8_15</name>
              <description>GPIO port selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI16_23</name>
              <description>GPIO port selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI24_31</name>
              <description>GPIO port selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EXTICR2</name>
          <displayName>EXTICR2</displayName>
          <description>EXTI external interrupt selection
          register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI0_7</name>
              <description>GPIO port selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI8_15</name>
              <description>GPIO port selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI16_23</name>
              <description>GPIO port selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI24_31</name>
              <description>GPIO port selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EXTICR3</name>
          <displayName>EXTICR3</displayName>
          <description>EXTI external interrupt selection
          register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI0_7</name>
              <description>GPIO port selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI8_15</name>
              <description>GPIO port selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI16_23</name>
              <description>GPIO port selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI24_31</name>
              <description>GPIO port selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EXTICR4</name>
          <displayName>EXTICR4</displayName>
          <description>EXTI external interrupt selection
          register</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI0_7</name>
              <description>GPIO port selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI8_15</name>
              <description>GPIO port selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI16_23</name>
              <description>GPIO port selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>EXTI24_31</name>
              <description>GPIO port selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IMR1</name>
          <displayName>IMR1</displayName>
          <description>EXTI CPU wakeup with interrupt mask
          register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFF80000</resetValue>
          <fields>
            <field>
              <name>IM0</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM1</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM2</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM3</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM4</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM5</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM6</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM7</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM8</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM9</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM10</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM11</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM12</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM13</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM14</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM15</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM16</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM17</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM18</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM19</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM20</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM21</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM22</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM23</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM24</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM25</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM26</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM27</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM28</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM29</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM30</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM31</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EMR1</name>
          <displayName>EMR1</displayName>
          <description>EXTI CPU wakeup with event mask
          register</description>
          <alternateRegister>IMR1</alternateRegister>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EM0</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM1</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM2</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM3</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM4</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM5</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM6</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM7</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM8</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM9</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM10</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM11</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM12</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM13</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM14</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM15</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM16</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM17</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM18</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM19</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM21</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM23</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM25</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM26</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM27</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM28</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM29</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM30</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM31</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IMR2</name>
          <displayName>IMR2</displayName>
          <description>EXTI CPU wakeup with interrupt mask
          register</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>IM32</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IM33</name>
              <description>CPU wakeup with interrupt mask on event
              input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EMR2</name>
          <displayName>EMR2</displayName>
          <description>EXTI CPU wakeup with event mask
          register</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EM32</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EM33</name>
              <description>CPU wakeup with event mask on event
              input</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR7</name>
          <displayName>HWCFGR7</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3D8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CPUEVENT</name>
              <description>HW configuration CPU event
              generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR6</name>
          <displayName>HWCFGR6</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3DC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>CPUEVENT</name>
              <description>HW configuration CPU event
              generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR5</name>
          <displayName>HWCFGR5</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3E0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFEAFFFFF</resetValue>
          <fields>
            <field>
              <name>CPUEVENT</name>
              <description>HW configuration CPU event
              generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR4</name>
          <displayName>HWCFGR4</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3E4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EVENT_TRG</name>
              <description>HW configuration event trigger
              type</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR3</name>
          <displayName>HWCFGR3</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3E8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EVENT_TRG</name>
              <description>HW configuration event trigger
              type</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR2</name>
          <displayName>HWCFGR2</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3EC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0007FFFF</resetValue>
          <fields>
            <field>
              <name>EVENT_TRG</name>
              <description>HW configuration event trigger
              type</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR1</name>
          <displayName>HWCFGR1</displayName>
          <description>Hardware configuration
          registers</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00051021</resetValue>
          <fields>
            <field>
              <name>NBIOPORT</name>
              <description>HW configuration of number of IO
              ports</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>CPUEVTEN</name>
              <description>HW configuration of CPU event output
              enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>NBCPUS</name>
              <description>configuration number of
              CPUs</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>NBEVENTS</name>
              <description>configuration number of
              event</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>AES version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000030</resetValue>
          <fields>
            <field>
              <name>MAJREV</name>
              <description>Major revision</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MINREV</name>
              <description>Minor revision</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>AES identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x000E0001</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>Identification code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>AES size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>Size Identification code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>TIM16</name>
      <description>General purpose timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40014400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM16</name>
        <description>TIM16 global interrupt</description>
        <value>21</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CEN</name>
              <description>Counter enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CKD</name>
              <description>Clock division</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>OIS1N</name>
              <description>Output Idle state 1</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS1</name>
              <description>Output Idle state 1</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCDS</name>
              <description>Capture/compare DMA
              selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCUS</name>
              <description>Capture/compare control update
              selection</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCPC</name>
              <description>Capture/compare preloaded
              control</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>COMDE</name>
              <description>COM DMA request enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1DE</name>
              <description>Capture/Compare 1 DMA request
              enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDE</name>
              <description>Update DMA request enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BIE</name>
              <description>Break interrupt enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMIE</name>
              <description>COM interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IE</name>
              <description>Capture/Compare 1 interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1OF</name>
              <description>Capture/Compare 1 overcapture
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BIF</name>
              <description>Break interrupt flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMIF</name>
              <description>COM interrupt flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IF</name>
              <description>Capture/compare 1 interrupt
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BG</name>
              <description>Break generation</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMG</name>
              <description>Capture/Compare control update
              generation</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1G</name>
              <description>Capture/compare 1
              generation</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UG</name>
              <description>Update generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Output</name>
          <displayName>CCMR1_Output</displayName>
          <description>capture/compare mode register (output
          mode)</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OC1M_2</name>
              <description>Output Compare 1 mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M</name>
              <description>Output Compare 1 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC1PE</name>
              <description>Output Compare 1 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1FE</name>
              <description>Output Compare 1 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Input</name>
          <displayName>CCMR1_Input</displayName>
          <description>capture/compare mode register 1 (input
          mode)</description>
          <alternateRegister>CCMR1_Output</alternateRegister>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IC1F</name>
              <description>Input capture 1 filter</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>IC1PSC</name>
              <description>Input capture 1 prescaler</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCER</name>
          <displayName>CCER</displayName>
          <description>capture/compare enable
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1NP</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1NE</name>
              <description>Capture/Compare 1 complementary output
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1P</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1E</name>
              <description>Capture/Compare 1 output
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UIFCPY</name>
              <description>UIF Copy</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RCR</name>
          <displayName>RCR</displayName>
          <description>repetition counter register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>REP</name>
              <description>Repetition counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>capture/compare register 1</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR1</name>
              <description>Capture/Compare 1 value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BDTR</name>
          <displayName>BDTR</displayName>
          <description>break and dead-time register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DTG</name>
              <description>Dead-time generator setup</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>LOCK</name>
              <description>Lock configuration</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSSI</name>
              <description>Off-state selection for Idle
              mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OSSR</name>
              <description>Off-state selection for Run
              mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKE</name>
              <description>Break enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKP</name>
              <description>Break polarity</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AOE</name>
              <description>Automatic output enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MOE</name>
              <description>Main output enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKF</name>
              <description>Break filter</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>BKDSRM</name>
              <description>Break Disarm</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKBID</name>
              <description>Break Bidirectional</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DCR</name>
          <displayName>DCR</displayName>
          <description>DMA control register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DBL</name>
              <description>DMA burst length</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>DBA</name>
              <description>DMA base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAR</name>
          <displayName>DMAR</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DMAB</name>
              <description>DMA register for burst
              accesses</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AF1</name>
          <displayName>AF1</displayName>
          <description>TIM17 option register 1</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BKINE</name>
              <description>BRK BKIN input enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP1E</name>
              <description>BRK COMP1 enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP2E</name>
              <description>BRK COMP2 enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKDFBK1E</name>
              <description>BRK DFSDM_BREAK1 enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKINP</name>
              <description>BRK BKIN input polarity</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP1P</name>
              <description>BRK COMP1 input polarity</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP2P</name>
              <description>BRK COMP2 input polarit</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TISEL</name>
          <displayName>TISEL</displayName>
          <description>input selection register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TI1SEL</name>
              <description>selects input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="TIM16">
      <name>TIM17</name>
      <baseAddress>0x40014800</baseAddress>
      <interrupt>
        <name>TIM17</name>
        <description>TIM17 global interrupt</description>
        <value>22</value>
      </interrupt>
    </peripheral>
    <peripheral>
      <name>TIM15</name>
      <description>General purpose timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40014000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM15</name>
        <description>Timer 15 global interrupt</description>
        <value>20</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CEN</name>
              <description>Counter enable
Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Counter disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Counter enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>UEV enabled. The Update (UEV) event is generated by one of the following events:</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source
This bit is set and cleared by software to select the UEV event sources.
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Any of the following events generate an update interrupt if enabled. These events can be: </description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Only counter overflow/underflow generates an update interrupt if enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Counter is not stopped at update event</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Counter stops counting at the next update event (clearing the bit CEN)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>TIMx_ARR register is not buffered</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>TIMx_ARR register is buffered</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CKD</name>
              <description>Clock division
This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>tDTS = tCK_INT</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>tDTS = 2*tCK_INT</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>tDTS = 4*tCK_INT</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Reserved, do not program this value</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CCPC</name>
              <description>Capture/compare preloaded control
Note: This bit acts only on channels that have a complementary output.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CCxE, CCxNE and OCxM bits are not preloaded</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CCUS</name>
              <description>Capture/compare control update selection
Note: This bit acts only on channels that have a complementary output.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CCDS</name>
              <description>Capture/compare DMA selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CCx DMA request sent when CCx event occurs</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CCx DMA requests sent when update event occurs</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MMS</name>
              <description>Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>Compare - OC1REFC signal is used as trigger output (TRGO).</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Compare - OC2REFC signal is used as trigger output (TRGO).</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TI1S</name>
              <description>TI1 selection</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>The TIMx_CH1 pin is connected to TI1 input</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OIS1</name>
              <description>Output Idle state 1 (OC1 output)
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC1=0 (after a dead-time if OC1N is implemented) when MOE=0</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC1=1 (after a dead-time if OC1N is implemented) when MOE=0</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OIS1N</name>
              <description>Output Idle state 1 (OC1N output)
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC1N=0 after a dead-time when MOE=0</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC1N=1 after a dead-time when MOE=0</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OIS2</name>
              <description>Output idle state 2 (OC2 output)
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC2=0 when MOE=0</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC2=1 when MOE=0</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SMCR</name>
          <displayName>SMCR</displayName>
          <description>slave mode control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>SMS1</name>
              <description>Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.</description>
                  <value>0x8</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TS1</name>
              <description>Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
Other: Reserved
See  for more details on ITRx meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Internal Trigger 0 (ITR0)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Internal Trigger 1 (ITR1)</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>Internal Trigger 2 (ITR2)</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Internal Trigger 3 (ITR3)</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>TI1 Edge Detector (TI1F_ED)</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Filtered Timer Input 1 (TI1FP1)</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>Filtered Timer Input 2 (TI2FP2)</description>
                  <value>0x6</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSM</name>
              <description>Master/slave mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SMS2</name>
              <description>Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.</description>
                  <value>0x8</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TS2</name>
              <description>Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
Other: Reserved
See  for more details on ITRx meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Internal Trigger 0 (ITR0)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Internal Trigger 1 (ITR1)</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>Internal Trigger 2 (ITR2)</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Internal Trigger 3 (ITR3)</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>TI1 Edge Detector (TI1F_ED)</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Filtered Timer Input 1 (TI1FP1)</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>Filtered Timer Input 2 (TI2FP2)</description>
                  <value>0x6</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Update interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Update interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1IE</name>
              <description>Capture/Compare 1 interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC1 interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC1 interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2IE</name>
              <description>Capture/Compare 2 interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC2 interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC2 interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COMIE</name>
              <description>COM interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COM interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COM interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIE</name>
              <description>Trigger interrupt enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Trigger interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Trigger interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BIE</name>
              <description>Break interrupt enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Break interrupt disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Break interrupt enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>UDE</name>
              <description>Update DMA request enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Update DMA request disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Update DMA request enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1DE</name>
              <description>Capture/Compare 1 DMA request enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC1 DMA request disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC1 DMA request enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2DE</name>
              <description>Capture/Compare 2 DMA request enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC2 DMA request disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC2 DMA request enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COMDE</name>
              <description>COM DMA request enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COM DMA request disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COM DMA request enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TDE</name>
              <description>Trigger DMA request enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Trigger DMA request disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Trigger DMA request enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No update occurred.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Update interrupt pending. This bit is set by hardware when the registers are updated:</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1IF</name>
              <description>Capture/Compare 1 interrupt flag
This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only).
If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No compare match / No input capture occurred</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>A compare match or an input capture occurred</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2IF</name>
              <description>Capture/Compare 2 interrupt flag
refer to CC1IF description</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMIF</name>
              <description>COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No COM event occurred</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COM interrupt pending</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIF</name>
              <description>Trigger interrupt flag
This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No trigger event occurred</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Trigger interrupt pending</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BIF</name>
              <description>Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No break event occurred</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>An active level has been detected on the break input</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1OF</name>
              <description>Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No overcapture has been detected</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2OF</name>
              <description>Capture/Compare 2 overcapture flag
Refer to CC1OF description</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UG</name>
              <description>Update generation
This bit can be set by software, it is automatically cleared by hardware.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1G</name>
              <description>Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>A capture/compare event is generated on channel 1:</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2G</name>
              <description>Capture/Compare 2 generation
Refer to CC1G description</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>COMG</name>
              <description>Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
Note: This bit acts only on channels that have a complementary output.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TG</name>
              <description>Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BG</name>
              <description>Break generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No action</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Output</name>
          <displayName>CCMR1_Output</displayName>
          <description>capture/compare mode register (output
          mode)</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC1 channel is configured as output.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TI1.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TI2.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OC1FE</name>
              <description>Output Compare 1 fast enable
This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OC1PE</name>
              <description>Output Compare 1 preload enable
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OC1M1</name>
              <description>Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.
On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.
The OC1M[3] bit is not contiguous, located in bit 16.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>Force inactive level - OC1REF is forced low.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Force active level - OC1REF is forced high.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active.</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x9</name>
                  <description>Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xC</name>
                  <description>Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xD</name>
                  <description>Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.</description>
                  <value>0xD</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC2 channel is configured as output.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TI2.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TI1.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OC2FE</name>
              <description>Output Compare 2 fast enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OC2PE</name>
              <description>Output Compare 2 preload enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OC2M1</name>
              <description>Output Compare 2 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OC1M2</name>
              <description>Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.
On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.
The OC1M[3] bit is not contiguous, located in bit 16.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>Force inactive level - OC1REF is forced low.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>Force active level - OC1REF is forced high.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active.</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x9</name>
                  <description>Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xC</name>
                  <description>Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xD</name>
                  <description>Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.</description>
                  <value>0xD</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OC2M2</name>
              <description>Output Compare 2 mode</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Input</name>
          <displayName>CCMR1_Input</displayName>
          <description>capture/compare mode register 1 (input
          mode)</description>
          <alternateRegister>CCMR1_Output</alternateRegister>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC1 channel is configured as output</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TI1</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TI2</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>IC1PSC</name>
              <description>Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>no prescaler, capture is done each time an edge is detected on the capture input</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>capture is done once every 2 events</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>capture is done once every 4 events</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>capture is done once every 8 events</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>IC1F</name>
              <description>Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No filter, sampling is done at fDTS</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>fSAMPLING=fCK_INT, N=2</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>fSAMPLING=fCK_INT, N=4</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>fSAMPLING=fCK_INT, N=8</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>fSAMPLING=fDTS/2, N=6</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>fSAMPLING=fDTS/2, N=8</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>fSAMPLING=fDTS/4, N=6</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>fSAMPLING=fDTS/4, N=8</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>fSAMPLING=fDTS/8, N=6</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x9</name>
                  <description>fSAMPLING=fDTS/8, N=8</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xA</name>
                  <description>fSAMPLING=fDTS/16, N=5</description>
                  <value>0xA</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xB</name>
                  <description>fSAMPLING=fDTS/16, N=6</description>
                  <value>0xB</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xC</name>
                  <description>fSAMPLING=fDTS/16, N=8</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xD</name>
                  <description>fSAMPLING=fDTS/32, N=5</description>
                  <value>0xD</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xE</name>
                  <description>fSAMPLING=fDTS/32, N=6</description>
                  <value>0xE</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xF</name>
                  <description>fSAMPLING=fDTS/32, N=8</description>
                  <value>0xF</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>CC2 channel is configured as output</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TI2</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TI1</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>IC2PSC</name>
              <description>Input capture 2 prescaler</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IC2F</name>
              <description>Input capture 2 filter</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CCER</name>
          <displayName>CCER</displayName>
          <description>capture/compare enable
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1E</name>
              <description>Capture/Compare 1 output enable
When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to  for details.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Capture mode disabled / OC1 is not active (see below)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Capture mode enabled / OC1 signal is output on the corresponding output pin</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1P</name>
              <description>Capture/Compare 1 output polarity
When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
CC1NP=0, CC1P=0:	non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).
CC1NP=0, CC1P=1:	inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
CC1NP=1, CC1P=1:	non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode.
CC1NP=1, CC1P=0: this configuration is reserved, it must not be used.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1NE</name>
              <description>Capture/Compare 1 complementary output enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC1NP</name>
              <description>Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to CC1P description.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC1N active high</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC1N active low</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC2E</name>
              <description>Capture/Compare 2 output enable
Refer to CC1E description</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CC2P</name>
              <description>Capture/Compare 2 output polarity
Refer to CC1P description</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CC2NP</name>
              <description>Capture/Compare 2 complementary output polarity
Refer to CC1NP description</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UIFCPY</name>
              <description>UIF Copy</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000FFFF</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RCR</name>
          <displayName>RCR</displayName>
          <description>repetition counter register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>REP</name>
              <description>Repetition counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>capture/compare register 1</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR1</name>
              <description>Capture/Compare 1 value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR2</name>
          <displayName>CCR2</displayName>
          <description>capture/compare register 2</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR2</name>
              <description>Capture/Compare 2 value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BDTR</name>
          <displayName>BDTR</displayName>
          <description>break and dead-time register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DTG</name>
              <description>Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx =&gt; DT=DTG[7:0]x tdtg with tdtg=tDTS
DTG[7:5]=10x =&gt; DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
DTG[7:5]=110 =&gt; DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
DTG[7:5]=111 =&gt; DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOCK</name>
              <description>Lock configuration
These bits offer a write protection against software errors.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>LOCK OFF - No bit is write protected</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OSSI</name>
              <description>Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OSSR</name>
              <description>Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). </description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKE</name>
              <description>Break enable
1; Break inputs (BRK and CCS clock failure event) enabled
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Break inputs (BRK and CCS clock failure event) disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKP</name>
              <description>Break polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Break input BRK is active low</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Break input BRK is active high</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>AOE</name>
              <description>Automatic output enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>MOE can be set only by software</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>MOE can be set by software or automatically at the next update event (if the break input is not be active)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MOE</name>
              <description>Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKF</name>
              <description>Break filter
This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>No filter, BRK acts asynchronously</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>fSAMPLING=fCK_INT, N=2</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>fSAMPLING=fCK_INT, N=4</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x3</name>
                  <description>fSAMPLING=fCK_INT, N=8</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x4</name>
                  <description>fSAMPLING=fDTS/2, N=6</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x5</name>
                  <description>fSAMPLING=fDTS/2, N=8</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x6</name>
                  <description>fSAMPLING=fDTS/4, N=6</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x7</name>
                  <description>fSAMPLING=fDTS/4, N=8</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x8</name>
                  <description>fSAMPLING=fDTS/8, N=6</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x9</name>
                  <description>fSAMPLING=fDTS/8, N=8</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xA</name>
                  <description>fSAMPLING=fDTS/16, N=5</description>
                  <value>0xA</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xB</name>
                  <description>fSAMPLING=fDTS/16, N=6</description>
                  <value>0xB</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xC</name>
                  <description>fSAMPLING=fDTS/16, N=8</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xD</name>
                  <description>fSAMPLING=fDTS/32, N=5</description>
                  <value>0xD</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xE</name>
                  <description>fSAMPLING=fDTS/32, N=6</description>
                  <value>0xE</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0xF</name>
                  <description>fSAMPLING=fDTS/32, N=8</description>
                  <value>0xF</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKDSRM</name>
              <description>Break Disarm
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Break input BRK is armed</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Break input BRK is disarmed</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKBID</name>
              <description>Break Bidirectional
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>Break input BRK in input mode</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>Break input BRK in bidirectional mode</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>DCR</name>
          <displayName>DCR</displayName>
          <description>DMA control register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DBA</name>
              <description>DMA base address
This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.
Example:
...</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>TIMx_CR1,</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>TIMx_CR2,</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>TIMx_SMCR,</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DBL</name>
              <description>DMA burst length
This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
...</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>1 transfer,</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>2 transfers,</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>3 transfers,</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x11</name>
                  <description>18 transfers.</description>
                  <value>0x11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAR</name>
          <displayName>DMAR</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DMAB</name>
              <description>DMA register for burst
              accesses</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AF1</name>
          <displayName>AF1</displayName>
          <description>TIM15 alternate register 1</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>BKINE</name>
              <description>BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>BKIN input disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>BKIN input enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKCMP1E</name>
              <description>BRK COMP1 enable
This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP1 input disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP1 input enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKCMP2E</name>
              <description>BRK COMP2 enable
This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP2 input disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP2 input enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
			<field>
              <name>BKCMP3E</name>
              <description>BRK COMP3 enable
This bit enables the COMP3 for the timer’s BRK input. COMP3 output is 'ORed’ with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP3 input disabled</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP3 input enabled</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKINP</name>
              <description>BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>BKIN input is active low</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>BKIN input is active high</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKCMP1P</name>
              <description>BRK COMP1 input polarity
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP1 input is active low</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP1 input is active high</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BKCMP2P</name>
              <description>BRK COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP2 input is active low</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP2 input is active high</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
			<field>
              <name>BKCMP3P</name>
              <description>BRK COMP3 input polarity
This bit selects the COMP3 input sensitivity. It must be programmed together with the BKP polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>COMP3 input is active low</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>COMP3 input is active high</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TISEL</name>
          <displayName>TISEL</displayName>
          <description>input selection register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TI1SEL</name>
              <description>selects TI1[0] to TI1[15] input
Others: Reserved</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>TIM15_CH1 input</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>TIM2_IC1</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>TIM3_IC1</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TI2SEL</name>
              <description>selects TI2[0] to TI2[15] input
Others: Reserved</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>B_0x0</name>
                  <description>TIM15_CH2 input</description>
                  <value>0x0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x1</name>
                  <description>TIM2_IC2</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B_0x2</name>
                  <description>TIM3_IC2</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>USART1</name>
      <description>Universal synchronous asynchronous receiver
      transmitter</description>
      <groupName>USART</groupName>
      <baseAddress>0x40013800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>USART1</name>
        <description>USART1 global interrupt</description>
        <value>27</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>Control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RXFFIE</name>
              <description>RXFIFO Full interrupt
              enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFEIE</name>
              <description>TXFIFO empty interrupt
              enable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FIFOEN</name>
              <description>FIFO mode enable</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>M1</name>
              <description>Word length</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EOBIE</name>
              <description>End of Block interrupt
              enable</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTOIE</name>
              <description>Receiver timeout interrupt
              enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DEAT</name>
              <description>DEAT</description>
              <bitOffset>21</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>DEDT</name>
              <description>DEDT</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OVER8</name>
              <description>Oversampling mode</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMIE</name>
              <description>Character match interrupt
              enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MME</name>
              <description>Mute mode enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>M0</name>
              <description>Word length</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WAKE</name>
              <description>Receiver wakeup method</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PCE</name>
              <description>Parity control enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PS</name>
              <description>Parity selection</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PEIE</name>
              <description>PE interrupt enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXEIE</name>
              <description>interrupt enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transmission complete interrupt
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNEIE</name>
              <description>RXNE interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLEIE</name>
              <description>IDLE interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TE</name>
              <description>Transmitter enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RE</name>
              <description>Receiver enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UESM</name>
              <description>USART enable in Stop mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UE</name>
              <description>USART enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>Control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>ADD4_7</name>
              <description>Address of the USART node</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ADD0_3</name>
              <description>Address of the USART node</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>RTOEN</name>
              <description>Receiver timeout enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ABRMOD</name>
              <description>Auto baud rate mode</description>
              <bitOffset>21</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ABREN</name>
              <description>Auto baud rate enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MSBFIRST</name>
              <description>Most significant bit first</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAINV</name>
              <description>Binary data inversion</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXINV</name>
              <description>TX pin active level
              inversion</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXINV</name>
              <description>RX pin active level
              inversion</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWAP</name>
              <description>Swap TX/RX pins</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LINEN</name>
              <description>LIN mode enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>STOP</name>
              <description>STOP bits</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CLKEN</name>
              <description>Clock enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CPOL</name>
              <description>Clock polarity</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CPHA</name>
              <description>Clock phase</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBCL</name>
              <description>Last bit clock pulse</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBDIE</name>
              <description>LIN break detection interrupt
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBDL</name>
              <description>LIN break detection length</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADDM7</name>
              <description>7-bit Address Detection/4-bit Address
              Detection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIS_NSS</name>
              <description>When the DSI_NSS bit is set, the NSS pin
              input will be ignored</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Synchronous Slave mode
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR3</name>
          <displayName>CR3</displayName>
          <description>Control register 3</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TXFTCFG</name>
              <description>TXFIFO threshold
              configuration</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>RXFTIE</name>
              <description>RXFIFO threshold interrupt
              enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFTCFG</name>
              <description>Receive FIFO threshold
              configuration</description>
              <bitOffset>25</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>TCBGTIE</name>
              <description>Tr Complete before guard time, interrupt
              enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFTIE</name>
              <description>threshold interrupt enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUFIE</name>
              <description>Wakeup from Stop mode interrupt
              enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUS</name>
              <description>Wakeup from Stop mode interrupt flag
              selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>SCARCNT</name>
              <description>Smartcard auto-retry count</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>DEP</name>
              <description>Driver enable polarity
              selection</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DEM</name>
              <description>Driver enable mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DDRE</name>
              <description>DMA Disable on Reception
              Error</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OVRDIS</name>
              <description>Overrun Disable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ONEBIT</name>
              <description>One sample bit method
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSIE</name>
              <description>CTS interrupt enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSE</name>
              <description>CTS enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTSE</name>
              <description>RTS enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAT</name>
              <description>DMA enable transmitter</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAR</name>
              <description>DMA enable receiver</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SCEN</name>
              <description>Smartcard mode enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NACK</name>
              <description>Smartcard NACK enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HDSEL</name>
              <description>Half-duplex selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IRLP</name>
              <description>Ir low-power</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IREN</name>
              <description>Ir mode enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EIE</name>
              <description>Error interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BRR</name>
          <displayName>BRR</displayName>
          <description>Baud rate register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BRR_4_15</name>
              <description>BRR_4_15</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
            <field>
              <name>BRR_0_3</name>
              <description>BRR_0_3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>GTPR</name>
          <displayName>GTPR</displayName>
          <description>Guard time and prescaler
          register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>GT</name>
              <description>Guard time value</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RTOR</name>
          <displayName>RTOR</displayName>
          <description>Receiver timeout register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BLEN</name>
              <description>Block Length</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>RTO</name>
              <description>Receiver timeout value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RQR</name>
          <displayName>RQR</displayName>
          <description>Request register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TXFRQ</name>
              <description>Transmit data flush
              request</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFRQ</name>
              <description>Receive data flush request</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MMRQ</name>
              <description>Mute mode request</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBKRQ</name>
              <description>Send break request</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ABRRQ</name>
              <description>Auto baud rate request</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ISR</name>
          <displayName>ISR</displayName>
          <description>Interrupt &amp; status
          register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00C0</resetValue>
          <fields>
            <field>
              <name>TXFT</name>
              <description>TXFIFO threshold flag</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFT</name>
              <description>RXFIFO threshold flag</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCBGT</name>
              <description>Transmission complete before guard time
              flag</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFF</name>
              <description>RXFIFO Full</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFE</name>
              <description>TXFIFO Empty</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>REACK</name>
              <description>REACK</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEACK</name>
              <description>TEACK</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF</name>
              <description>WUF</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RWU</name>
              <description>RWU</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBKF</name>
              <description>SBKF</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMF</name>
              <description>CMF</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BUSY</name>
              <description>BUSY</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ABRF</name>
              <description>ABRF</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ABRE</name>
              <description>ABRE</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDR</name>
              <description>SPI slave underrun error
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EOBF</name>
              <description>EOBF</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTOF</name>
              <description>RTOF</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTS</name>
              <description>CTS</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSIF</name>
              <description>CTSIF</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBDF</name>
              <description>LBDF</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXE</name>
              <description>TXE</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TC</name>
              <description>TC</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNE</name>
              <description>RXNE</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLE</name>
              <description>IDLE</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ORE</name>
              <description>ORE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NF</name>
              <description>NF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FE</name>
              <description>FE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PE</name>
              <description>PE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <displayName>ICR</displayName>
          <description>Interrupt flag clear register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>WUCF</name>
              <description>Wakeup from Stop mode clear
              flag</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMCF</name>
              <description>Character match clear flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDRCF</name>
              <description>SPI slave underrun clear
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EOBCF</name>
              <description>End of block clear flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTOCF</name>
              <description>Receiver timeout clear
              flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSCF</name>
              <description>CTS clear flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBDCF</name>
              <description>LIN break detection clear
              flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCBGTCF</name>
              <description>Transmission complete before Guard time
              clear flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCCF</name>
              <description>Transmission complete clear
              flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFECF</name>
              <description>TXFIFO empty clear flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLECF</name>
              <description>Idle line detected clear
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ORECF</name>
              <description>Overrun error clear flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NCF</name>
              <description>Noise detected clear flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FECF</name>
              <description>Framing error clear flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PECF</name>
              <description>Parity error clear flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RDR</name>
          <displayName>RDR</displayName>
          <description>Receive data register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RDR</name>
              <description>Receive data value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TDR</name>
          <displayName>TDR</displayName>
          <description>Transmit data register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TDR</name>
              <description>Transmit data value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PRESC</name>
          <displayName>PRESC</displayName>
          <description>Prescaler register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PRESCALER</name>
              <description>Clock prescaler</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="USART1">
      <name>USART2</name>
      <baseAddress>0x40004400</baseAddress>
      <interrupt>
        <name>USART2</name>
        <description>USART2 global interrupt</description>
        <value>28</value>
      </interrupt>
    </peripheral>
    <peripheral derivedFrom="USART1">
      <name>USART3</name>
      <baseAddress>0x40004800</baseAddress>
      <interrupt>
        <name>USART3_USART4_LPUART1</name>
        <description>USART3 + USART4 + LPUART1</description>
        <value>29</value>
      </interrupt>
    </peripheral>
    <peripheral derivedFrom="USART1">
      <name>USART4</name>
      <baseAddress>0x40004C00</baseAddress>
    </peripheral>
    <peripheral>
      <name>SPI1</name>
      <description>Serial peripheral interface/Inter-IC
      sound</description>
      <groupName>SPI</groupName>
      <baseAddress>0x40013000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>SPI1</name>
        <description>SPI1 global interrupt</description>
        <value>25</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BIDIMODE</name>
              <description>Bidirectional data mode
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BIDIOE</name>
              <description>Output enable in bidirectional
              mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CRCEN</name>
              <description>Hardware CRC calculation
              enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CRCNEXT</name>
              <description>CRC transfer next</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DFF</name>
              <description>Data frame format</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXONLY</name>
              <description>Receive only</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SSM</name>
              <description>Software slave management</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SSI</name>
              <description>Internal slave select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LSBFIRST</name>
              <description>Frame format</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SPE</name>
              <description>SPI enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BR</name>
              <description>Baud rate control</description>
              <bitOffset>3</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MSTR</name>
              <description>Master selection</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CPOL</name>
              <description>Clock polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CPHA</name>
              <description>Clock phase</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RXDMAEN</name>
              <description>Rx buffer DMA enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXDMAEN</name>
              <description>Tx buffer DMA enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SSOE</name>
              <description>SS output enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NSSP</name>
              <description>NSS pulse management</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FRF</name>
              <description>Frame format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ERRIE</name>
              <description>Error interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNEIE</name>
              <description>RX buffer not empty interrupt
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXEIE</name>
              <description>Tx buffer empty interrupt
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DS</name>
              <description>Data size</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>FRXTH</name>
              <description>FIFO reception threshold</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LDMA_RX</name>
              <description>Last DMA transfer for
              reception</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LDMA_TX</name>
              <description>Last DMA transfer for
              transmission</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x0002</resetValue>
          <fields>
            <field>
              <name>RXNE</name>
              <description>Receive buffer not empty</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXE</name>
              <description>Transmit buffer empty</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHSIDE</name>
              <description>Channel side</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>UDR</name>
              <description>Underrun flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CRCERR</name>
              <description>CRC error flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MODF</name>
              <description>Mode fault</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVR</name>
              <description>Overrun flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BSY</name>
              <description>Busy flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIFRFE</name>
              <description>TI frame format error</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRLVL</name>
              <description>FIFO reception level</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FTLVL</name>
              <description>FIFO transmission level</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DR</name>
          <displayName>DR</displayName>
          <description>data register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DR</name>
              <description>Data register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CRCPR</name>
          <displayName>CRCPR</displayName>
          <description>CRC polynomial register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0007</resetValue>
          <fields>
            <field>
              <name>CRCPOLY</name>
              <description>CRC polynomial register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RXCRCR</name>
          <displayName>RXCRCR</displayName>
          <description>RX CRC register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RxCRC</name>
              <description>Rx CRC register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TXCRCR</name>
          <displayName>TXCRCR</displayName>
          <description>TX CRC register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TxCRC</name>
              <description>Tx CRC register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>I2SCFGR</name>
          <displayName>I2SCFGR</displayName>
          <description>configuration register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CHLEN</name>
              <description>Channel length (number of bits per audio
              channel)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DATLEN</name>
              <description>Data length to be
              transferred</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CKPOL</name>
              <description>Inactive state clock
              polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2SSTD</name>
              <description>standard selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PCMSYNC</name>
              <description>PCM frame synchronization</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2SCFG</name>
              <description>I2S configuration mode</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>SE2</name>
              <description>I2S enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2SMOD</name>
              <description>I2S mode selection</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>I2SPR</name>
          <displayName>I2SPR</displayName>
          <description>prescaler register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>I2SDIV</name>
              <description>linear prescaler</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>ODD</name>
              <description>Odd factor for the
              prescaler</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MCKOE</name>
              <description>Master clock output enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR</name>
          <displayName>HWCFGR</displayName>
          <description>hardware configuration
          register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CRCCFG</name>
              <description>CRC capable at SPI mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>I2SCFG</name>
              <description>I2S mode implementation</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>I2SCKCFG</name>
              <description>I2S master clock generator at I2S
              mode</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>DSCFG</name>
              <description>SPI data size
              configuration</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>NSSCFG</name>
              <description>NSS pulse feature enhancement at SPI
              master</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="SPI1">
      <name>SPI2</name>
      <baseAddress>0x40003800</baseAddress>
      <interrupt>
        <name>SPI2</name>
        <description>SPI2 global interrupt</description>
        <value>26</value>
      </interrupt>
    </peripheral>
    <peripheral>
      <name>TIM1</name>
      <description>Advanced-timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40012C00</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM1_BRK_UP_TRG_COMP</name>
        <description>TIM1 break, update, trigger</description>
        <value>13</value>
      </interrupt>
      <interrupt>
        <name>TIM1_CC</name>
        <description>TIM1 Capture Compare interrupt</description>
        <value>14</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CEN</name>
              <description>Counter enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMS</name>
              <description>Center-aligned mode
              selection</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CKD</name>
              <description>Clock division</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>MMS2</name>
              <description>Master mode selection 2</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>OIS6</name>
              <description>Output Idle state 6 (OC6
              output)</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS5</name>
              <description>Output Idle state 5 (OC5
              output)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS4</name>
              <description>Output Idle state 4</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS3N</name>
              <description>Output Idle state 3</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS3</name>
              <description>Output Idle state 3</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS2N</name>
              <description>Output Idle state 2</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS2</name>
              <description>Output Idle state 2</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS1N</name>
              <description>Output Idle state 1</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OIS1</name>
              <description>Output Idle state 1</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TI1S</name>
              <description>TI1 selection</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MMS</name>
              <description>Master mode selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>CCDS</name>
              <description>Capture/compare DMA
              selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCUS</name>
              <description>Capture/compare control update
              selection</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCPC</name>
              <description>Capture/compare preloaded
              control</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SMCR</name>
          <displayName>SMCR</displayName>
          <description>slave mode control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>SMS</name>
              <description>Slave mode selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OCCS</name>
              <description>OCREF clear selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TS_4</name>
              <description>Trigger selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MSM</name>
              <description>Master/Slave mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ETF</name>
              <description>External trigger filter</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ETPS</name>
              <description>External trigger prescaler</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ECE</name>
              <description>External clock enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ETP</name>
              <description>External trigger polarity</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SMS_3</name>
              <description>Slave mode selection - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TS</name>
              <description>Trigger selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IE</name>
              <description>Capture/Compare 1 interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2IE</name>
              <description>Capture/Compare 2 interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3IE</name>
              <description>Capture/Compare 3 interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4IE</name>
              <description>Capture/Compare 4 interrupt
              enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMIE</name>
              <description>COM interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIE</name>
              <description>Trigger interrupt enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BIE</name>
              <description>Break interrupt enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDE</name>
              <description>Update DMA request enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1DE</name>
              <description>Capture/Compare 1 DMA request
              enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2DE</name>
              <description>Capture/Compare 2 DMA request
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3DE</name>
              <description>Capture/Compare 3 DMA request
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4DE</name>
              <description>Capture/Compare 4 DMA request
              enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMDE</name>
              <description>COM DMA request enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TDE</name>
              <description>Trigger DMA request enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IF</name>
              <description>Capture/compare 1 interrupt
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2IF</name>
              <description>Capture/Compare 2 interrupt
              flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3IF</name>
              <description>Capture/Compare 3 interrupt
              flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4IF</name>
              <description>Capture/Compare 4 interrupt
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMIF</name>
              <description>COM interrupt flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIF</name>
              <description>Trigger interrupt flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BIF</name>
              <description>Break interrupt flag</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>B2IF</name>
              <description>Break 2 interrupt flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1OF</name>
              <description>Capture/Compare 1 overcapture
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2OF</name>
              <description>Capture/compare 2 overcapture
              flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3OF</name>
              <description>Capture/Compare 3 overcapture
              flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4OF</name>
              <description>Capture/Compare 4 overcapture
              flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBIF</name>
              <description>System Break interrupt
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC5IF</name>
              <description>Compare 5 interrupt flag</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC6IF</name>
              <description>Compare 6 interrupt flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UG</name>
              <description>Update generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1G</name>
              <description>Capture/compare 1
              generation</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2G</name>
              <description>Capture/compare 2
              generation</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3G</name>
              <description>Capture/compare 3
              generation</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4G</name>
              <description>Capture/compare 4
              generation</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMG</name>
              <description>Capture/Compare control update
              generation</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TG</name>
              <description>Trigger generation</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BG</name>
              <description>Break generation</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>B2G</name>
              <description>Break 2 generation</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Output</name>
          <displayName>CCMR1_Output</displayName>
          <description>capture/compare mode register 1 (output
          mode)</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC1FE</name>
              <description>Output Compare 1 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1PE</name>
              <description>Output Compare 1 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M</name>
              <description>Output Compare 1 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC1CE</name>
              <description>Output Compare 1 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/Compare 2
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC2FE</name>
              <description>Output Compare 2 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2PE</name>
              <description>Output Compare 2 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2M</name>
              <description>Output Compare 2 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC2CE</name>
              <description>Output Compare 2 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M_3</name>
              <description>Output Compare 1 mode - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2M_3</name>
              <description>Output Compare 2 mode - bit
              3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Input</name>
          <displayName>CCMR1_Input</displayName>
          <description>capture/compare mode register 1 (output
          mode)</description>
          <alternateRegister>CCMR1_Output</alternateRegister>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC1FE</name>
              <description>Output Compare 1 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1PE</name>
              <description>Output Compare 1 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M</name>
              <description>Output Compare 1 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC1CE</name>
              <description>Output Compare 1 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/Compare 2
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC2FE</name>
              <description>Output Compare 2 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2PE</name>
              <description>Output Compare 2 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2M</name>
              <description>Output Compare 2 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC2CE</name>
              <description>Output Compare 2 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR2_Output</name>
          <displayName>CCMR2_Output</displayName>
          <description>capture/compare mode register 2 (output
          mode)</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC3S</name>
              <description>Capture/Compare 3
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC3FE</name>
              <description>Output compare 3 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3PE</name>
              <description>Output compare 3 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3M</name>
              <description>Output compare 3 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC3CE</name>
              <description>Output compare 3 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4S</name>
              <description>Capture/Compare 4
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC4FE</name>
              <description>Output compare 4 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4PE</name>
              <description>Output compare 4 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4M</name>
              <description>Output compare 4 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC4CE</name>
              <description>Output compare 4 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3M_3</name>
              <description>Output Compare 3 mode - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4M_3</name>
              <description>Output Compare 4 mode - bit
              3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR2_Input</name>
          <displayName>CCMR2_Input</displayName>
          <description>capture/compare mode register 2 (output
          mode)</description>
          <alternateRegister>CCMR2_Output</alternateRegister>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC3S</name>
              <description>Capture/Compare 3
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC3FE</name>
              <description>Output compare 3 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3PE</name>
              <description>Output compare 3 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3M</name>
              <description>Output compare 3 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC3CE</name>
              <description>Output compare 3 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4S</name>
              <description>Capture/Compare 4
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC4FE</name>
              <description>Output compare 4 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4PE</name>
              <description>Output compare 4 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4M</name>
              <description>Output compare 4 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC4CE</name>
              <description>Output compare 4 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCER</name>
          <displayName>CCER</displayName>
          <description>capture/compare enable
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1E</name>
              <description>Capture/Compare 1 output
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1P</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1NE</name>
              <description>Capture/Compare 1 complementary output
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1NP</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2E</name>
              <description>Capture/Compare 2 output
              enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2P</name>
              <description>Capture/Compare 2 output
              Polarity</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2NE</name>
              <description>Capture/Compare 2 complementary output
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2NP</name>
              <description>Capture/Compare 2 output
              Polarity</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3E</name>
              <description>Capture/Compare 3 output
              enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3P</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3NE</name>
              <description>Capture/Compare 3 complementary output
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3NP</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4E</name>
              <description>Capture/Compare 4 output
              enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4P</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4NP</name>
              <description>Capture/Compare 4 complementary output
              polarity</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC5E</name>
              <description>Capture/Compare 5 output
              enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC5P</name>
              <description>Capture/Compare 5 output
              polarity</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC6E</name>
              <description>Capture/Compare 6 output
              enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC6P</name>
              <description>Capture/Compare 6 output
              polarity</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UIFCPY</name>
              <description>UIF copy</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RCR</name>
          <displayName>RCR</displayName>
          <description>repetition counter register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>REP</name>
              <description>Repetition counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>capture/compare register 1</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR1</name>
              <description>Capture/Compare 1 value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR2</name>
          <displayName>CCR2</displayName>
          <description>capture/compare register 2</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR2</name>
              <description>Capture/Compare 2 value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR3</name>
          <displayName>CCR3</displayName>
          <description>capture/compare register 3</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR3</name>
              <description>Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR4</name>
          <displayName>CCR4</displayName>
          <description>capture/compare register 4</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR4</name>
              <description>Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BDTR</name>
          <displayName>BDTR</displayName>
          <description>break and dead-time register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DTG</name>
              <description>Dead-time generator setup</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>LOCK</name>
              <description>Lock configuration</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OSSI</name>
              <description>Off-state selection for Idle
              mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OSSR</name>
              <description>Off-state selection for Run
              mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKE</name>
              <description>Break enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKP</name>
              <description>Break polarity</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AOE</name>
              <description>Automatic output enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MOE</name>
              <description>Main output enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKF</name>
              <description>Break filter</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>BK2F</name>
              <description>Break 2 filter</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>BK2E</name>
              <description>Break 2 enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2P</name>
              <description>Break 2 polarity</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKDSRM</name>
              <description>Break Disarm</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2DSRM</name>
              <description>Break2 Disarm</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKBID</name>
              <description>Break Bidirectional</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2ID</name>
              <description>Break2 bidirectional</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DCR</name>
          <displayName>DCR</displayName>
          <description>DMA control register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DBL</name>
              <description>DMA burst length</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>DBA</name>
              <description>DMA base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAR</name>
          <displayName>DMAR</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DMAB</name>
              <description>DMA register for burst
              accesses</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OR1</name>
          <displayName>OR1</displayName>
          <description>option register 1</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>OCREF_CLR</name>
              <description>Ocref_clr source selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR3_Output</name>
          <displayName>CCMR3_Output</displayName>
          <description>capture/compare mode register 2 (output
          mode)</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OC6M_bit3</name>
              <description>Output Compare 6 mode bit
              3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC5M_bit3</name>
              <description>Output Compare 5 mode bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC6CE</name>
              <description>Output compare 6 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC6M</name>
              <description>Output compare 6 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC6PE</name>
              <description>Output compare 6 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC6FE</name>
              <description>Output compare 6 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC5CE</name>
              <description>Output compare 5 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC5M</name>
              <description>Output compare 5 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC5PE</name>
              <description>Output compare 5 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC5FE</name>
              <description>Output compare 5 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR5</name>
          <displayName>CCR5</displayName>
          <description>capture/compare register 4</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR5</name>
              <description>Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>GC5C1</name>
              <description>Group Channel 5 and Channel
              1</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GC5C2</name>
              <description>Group Channel 5 and Channel
              2</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GC5C3</name>
              <description>Group Channel 5 and Channel
              3</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR6</name>
          <displayName>CCR6</displayName>
          <description>capture/compare register 4</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR6</name>
              <description>Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AF1</name>
          <displayName>AF1</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>BKINE</name>
              <description>BRK BKIN input enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP1E</name>
              <description>BRK COMP1 enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP2E</name>
              <description>BRK COMP2 enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKINP</name>
              <description>BRK BKIN input polarity</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP1P</name>
              <description>BRK COMP1 input polarity</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKCMP2P</name>
              <description>BRK COMP2 input polarity</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ETRSEL</name>
              <description>ETR source selection</description>
              <bitOffset>14</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AF2</name>
          <displayName>AF2</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>BK2INE</name>
              <description>BRK2 BKIN input enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2CMP1E</name>
              <description>BRK2 COMP1 enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2CMP2E</name>
              <description>BRK2 COMP2 enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2DFBK0E</name>
              <description>BRK2 DFSDM_BREAK0 enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2INP</name>
              <description>BRK2 BKIN input polarity</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2CMP1P</name>
              <description>BRK2 COMP1 input polarity</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BK2CMP2P</name>
              <description>BRK2 COMP2 input polarity</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
        <name>ADC</name>
        <description>Analog to Digital Converter instance
      1</description>
        <groupName>ADC</groupName>
        <baseAddress>0x40012400</baseAddress>
        <addressBlock>
          <offset>0x0</offset>
          <size>0x400</size>
          <usage>registers</usage>
        </addressBlock>
		<interrupt>
          <name>ADC_COMP</name>
          <description>ADC and COMP interrupts</description>
          <value>12</value>
        </interrupt>
        <registers>
          <register>
            <name>ADC_ISR</name>
            <displayName>ADC_ISR</displayName>
            <description>ADC interrupt and status register</description>
            <addressOffset>0x0</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>ADRDY</name>
                <description>ADC ready
	This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.
	It is cleared by software writing 1 to it.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC is ready to start conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOSMP</name>
                <description>End of sampling flag
	This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1’.</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>End of sampling phase reached</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOC</name>
                <description>End of conversion flag
	This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Channel conversion not complete (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Channel conversion complete</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOS</name>
                <description>End of sequence flag
	This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.</description>
                <bitOffset>3</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Conversion sequence complete</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OVR</name>
                <description>ADC overrun
	This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No overrun occurred (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Overrun has occurred</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD1</name>
                <description>Analog watchdog 1 flag
	This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1.</description>
                <bitOffset>7</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog event occurred</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2</name>
                <description>Analog watchdog 2 flag
	This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.</description>
                <bitOffset>8</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog event occurred</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3</name>
                <description>Analog watchdog 3 flag
	This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.</description>
                <bitOffset>9</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog event occurred</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOCAL</name>
                <description>End Of Calibration flag
	This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.</description>
                <bitOffset>11</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Calibration is not complete</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Calibration is complete</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CCRDY</name>
                <description>Channel Configuration Ready flag
	This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it.
	Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.</description>
                <bitOffset>13</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Channel configuration update not applied. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Channel configuration update is applied.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_IER</name>
            <displayName>ADC_IER</displayName>
            <description>ADC interrupt enable register </description>
            <addressOffset>0x4</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>ADRDYIE</name>
                <description>ADC ready interrupt enable
	This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADRDY interrupt disabled.</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOSMPIE</name>
                <description>End of sampling flag interrupt enable
	This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>EOSMP interrupt disabled.</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOCIE</name>
                <description>End of conversion interrupt enable
	This bit is set and cleared by software to enable/disable the end of conversion interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>EOC interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>EOC interrupt enabled. An interrupt is generated when the EOC bit is set.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOSIE</name>
                <description>End of conversion sequence interrupt enable
	This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>3</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>EOS interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>EOS interrupt enabled. An interrupt is generated when the EOS bit is set.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OVRIE</name>
                <description>Overrun interrupt enable
	This bit is set and cleared by software to enable/disable the overrun interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Overrun interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD1IE</name>
                <description>Analog watchdog 1 interrupt enable
	This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
	Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>7</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Analog watchdog interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog interrupt enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2IE</name>
                <description>Analog watchdog 2 interrupt enable
	This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
	Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>8</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Analog watchdog interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog interrupt enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3IE</name>
                <description>Analog watchdog 3 interrupt enable
	This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
	Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>9</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Analog watchdog interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog interrupt enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EOCALIE</name>
                <description>End of calibration interrupt enable
	This bit is set and cleared by software to enable/disable the end of calibration interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>11</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>End of calibration interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>End of calibration interrupt enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CCRDYIE</name>
                <description>Channel Configuration Ready Interrupt enable
	This bit is set and cleared by software to enable/disable the channel configuration ready interrupt.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>13</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Channel configuration ready interrupt disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Channel configuration ready interrupt enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CR</name>
            <displayName>ADC_CR</displayName>
            <description>ADC control register</description>
            <addressOffset>0x8</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>ADEN</name>
                <description>ADC enable command
	This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set.
	It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
	Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC is disabled (OFF state)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Write 1 to enable the ADC.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ADDIS</name>
                <description>ADC disable command
	This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).
	It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).
	Note: Setting ADDIS to '1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No ADDIS command ongoing</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ADSTART</name>
                <description>ADC start conversion command
	This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).
	It is cleared by hardware:
	In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
	In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
	In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware.
	Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).
	After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No ADC conversion is ongoing.</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ADSTP</name>
                <description>ADC stop conversion command
	This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
	It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.
	Note: Setting ADSTP to '1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No ADC stop conversion command ongoing</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ADVREGEN</name>
                <description>ADC Voltage Regulator Enable
	This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP.
	It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0.
	Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).</description>
                <bitOffset>28</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC voltage regulator disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC voltage regulator enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ADCAL</name>
                <description>ADC calibration
	This bit is set by software to start the calibration of the ADC.
	It is cleared by hardware after calibration is complete.
	Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
	The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).</description>
                <bitOffset>31</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Calibration complete</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CFGR1</name>
            <displayName>ADC_CFGR1</displayName>
            <description>ADC configuration register 1</description>
            <addressOffset>0xc</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>DMAEN</name>
                <description>Direct memory access enable
	This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to .
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>DMA disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>DMA enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>DMACFG</name>
                <description>Direct memory access configuration
	This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.
	For more details, refer to page 391
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>DMA one shot mode selected</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>DMA circular mode selected</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SCANDIR</name>
                <description>Scan sequence direction
	This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Upward scan (from CHSEL0 to CHSEL18)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Backward scan (from CHSEL18 to CHSEL0)</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>RES</name>
                <description>Data resolution
	These bits are written by software to select the resolution of the conversion.
	Note: The software is allowed to write these bits only when ADEN = 0.</description>
                <bitOffset>3</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>12 bits</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>10 bits</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>8 bits</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>6 bits</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>ALIGN</name>
                <description>Data alignment
	This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 389
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>5</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Right alignment</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Left alignment</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EXTSEL</name>
                <description>External trigger selection
	These bits select the external event used to trigger the start of conversion (refer to External triggers for details):
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>6</bitOffset>
                <bitWidth>3</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>TRG0</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>TRG1</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>TRG2</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>TRG3</description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>TRG4</description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>TRG5</description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>TRG6</description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>TRG7</description>
                    <value>0x7</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>EXTEN</name>
                <description>External trigger enable and polarity selection
	These bits are set and cleared by software to select the external trigger polarity and enable the trigger.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>10</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Hardware trigger detection disabled (conversions can be started by software)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Hardware trigger detection on the rising edge</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>Hardware trigger detection on the falling edge</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>Hardware trigger detection on both the rising and falling edges</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OVRMOD</name>
                <description>Overrun management mode
	This bit is set and cleared by software and configure the way data overruns are managed.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>12</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC_DR register is preserved with the old data when an overrun is detected. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC_DR register is overwritten with the last conversion result when an overrun is detected.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CONT</name>
                <description>Single / continuous conversion mode
	This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.
	Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
	The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>13</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Single conversion mode</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Continuous conversion mode</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>WAIT</name>
                <description>Wait conversion mode
	This bit is set and cleared by software to enable/disable wait conversion mode..
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>14</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Wait conversion mode off</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Wait conversion mode on</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AUTOFF</name>
                <description>Auto-off mode
	This bit is set and cleared by software to enable/disable auto-off mode..
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>15</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Auto-off mode disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Auto-off mode enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>DISCEN</name>
                <description>Discontinuous mode
	This bit is set and cleared by software to enable/disable discontinuous mode.
	Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
	The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>16</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Discontinuous mode disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Discontinuous mode enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSELRMOD</name>
                <description>Mode selection of the ADC_CHSELR register
	This bit is set and cleared by software to control the ADC_CHSELR feature:
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>21</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Each bit of the ADC_CHSELR register enables an input </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC_CHSELR register is able to sequence up to 8 channels</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD1SGL</name>
                <description>Enable the watchdog on a single channel or on all channels
	This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>22</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Analog watchdog 1 enabled on all channels</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog 1 enabled on a single channel</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD1EN</name>
                <description>Analog watchdog enable
	This bit is set and cleared by software.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>23</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Analog watchdog 1 disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Analog watchdog 1 enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD1CH</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.
	.....
	Others: Reserved
	Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register.
	The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>26</bitOffset>
                <bitWidth>5</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog input Channel 0 monitored by AWD</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog input Channel 1 monitored by AWD</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x11</name>
                    <description>ADC analog input Channel 17 monitored by AWD</description>
                    <value>0x11</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x12</name>
                    <description>ADC analog input Channel 18 monitored by AWD</description>
                    <value>0x12</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CFGR2</name>
            <displayName>ADC_CFGR2</displayName>
            <description>ADC configuration register 2</description>
            <addressOffset>0x10</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>OVSE</name>
                <description>Oversampler Enable
	This bit is set and cleared by software.
	Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Oversampler disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Oversampler enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OVSR</name>
                <description>Oversampling ratio
	This bit filed defines the number of oversampling ratio.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>2</bitOffset>
                <bitWidth>3</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>2x</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>4x</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>8x</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>16x</description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>32x</description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>64x</description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>128x</description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>256x</description>
                    <value>0x7</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OVSS</name>
                <description>Oversampling shift
	This bit is set and cleared by software.
	Others: Reserved
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>5</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>No shift</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Shift 1-bit</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>Shift 2-bits</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>Shift 3-bits</description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>Shift 4-bits</description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>Shift 5-bits</description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>Shift 6-bits</description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>Shift 7-bits</description>
                    <value>0x7</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x8</name>
                    <description>Shift 8-bits</description>
                    <value>0x8</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TOVS</name>
                <description>Triggered Oversampling
	This bit is set and cleared by software.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>9</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>All oversampled conversions for a channel are done consecutively after a trigger</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Each oversampled conversion for a channel needs a trigger</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>LFTRIG</name>
                <description>Low frequency trigger mode enable
	This bit is set and cleared by software.
	Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).</description>
                <bitOffset>29</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Low Frequency Trigger Mode disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Low Frequency Trigger Mode enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CKMODE</name>
                <description>ADC clock mode
	These bits are set and cleared by software to define how the analog ADC is clocked:
	In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.
	Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).</description>
                <bitOffset>30</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>PCLK/2 (Synchronous clock mode)</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>PCLK/4 (Synchronous clock mode)</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_SMPR</name>
            <displayName>ADC_SMPR</displayName>
            <description>ADC sampling time register</description>
            <addressOffset>0x14</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>SMP1</name>
                <description>Sampling time selection 1
	These bits are written by software to select the sampling time that applies to all channels.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                <bitWidth>3</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>1.5 ADC clock cycles </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>3.5 ADC clock cycles </description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>7.5 ADC clock cycles </description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>12.5 ADC clock cycles </description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>19.5 ADC clock cycles </description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>39.5 ADC clock cycles </description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>79.5 ADC clock cycles </description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>160.5 ADC clock cycles </description>
                    <value>0x7</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMP2</name>
                <description>Sampling time selection 2
	These bits are written by software to select the sampling time that applies to all channels.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>4</bitOffset>
                <bitWidth>3</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>1.5 ADC clock cycles </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>3.5 ADC clock cycles </description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>7.5 ADC clock cycles </description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>12.5 ADC clock cycles </description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>19.5 ADC clock cycles </description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>39.5 ADC clock cycles </description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>79.5 ADC clock cycles </description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>160.5 ADC clock cycles </description>
                    <value>0x7</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL0</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>8</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL1</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>9</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL2</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>10</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL3</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>11</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL4</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>12</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL5</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>13</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL6</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>14</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL7</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>15</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL8</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>16</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL9</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>17</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL10</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>18</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL11</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>19</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL12</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>20</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL13</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>21</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL14</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>22</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL15</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>23</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL16</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>24</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL17</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>25</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SMPSEL18</name>
                <description>Channel-x sampling time selection
	These bits are written by software to define which sampling time is used.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>26</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Sampling time of CHANNELx use the setting of SMP1[2:0] register. </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Sampling time of CHANNELx use the setting of SMP2[2:0] register. </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_AWD1TR</name>
            <displayName>ADC_AWD1TR</displayName>
            <description>ADC watchdog threshold register</description>
            <addressOffset>0x20</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x0FFF0000</resetValue>
            <fields>
              <field>
                <name>LT1</name>
                <description>Analog watchdog 1 lower threshold
	These bits are written by software to define the lower threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>HT1</name>
                <description>Analog watchdog 1 higher threshold
	These bits are written by software to define the higher threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>16</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_AWD2TR</name>
            <displayName>ADC_AWD2TR</displayName>
            <description>ADC watchdog threshold register</description>
            <addressOffset>0x24</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x0FFF0000</resetValue>
            <fields>
              <field>
                <name>LT2</name>
                <description>Analog watchdog 2 lower threshold
	These bits are written by software to define the lower threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>HT2</name>
                <description>Analog watchdog 2 higher threshold
	These bits are written by software to define the higher threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>16</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CHSELRMOD0</name>
            <displayName>ADC_CHSELRMOD0</displayName>
            <description>ADC channel selection register</description>
            <addressOffset>0x28</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>CHSEL0</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>0</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL1</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>1</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL2</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>2</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL3</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>3</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL4</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>4</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL5</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>5</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL6</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>6</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL7</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>7</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL8</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>8</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL9</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>9</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL10</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>10</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL11</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>11</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL12</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>12</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL13</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>13</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL14</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>14</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL15</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>15</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL16</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>16</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL17</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>17</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHSEL18</name>
                <description>Channel-x selection
	These bits are written by software and define which channels are part of the sequence of channels to be converted.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
	If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.</description>
                <bitOffset>18</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Input Channel-x is not selected for conversion</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Input Channel-x is selected for conversion</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CHSELRMOD1</name>
            <displayName>ADC_CHSELRMOD1</displayName>
            <description>ADC channel selection register</description>
            <alternateRegister>ADC_CHSELRMOD0</alternateRegister>
            <addressOffset>0x28</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>SQ1</name>
                <description>1st conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ2</name>
                <description>2nd conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>4</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ3</name>
                <description>3rd conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>8</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ4</name>
                <description>4th conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>12</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ5</name>
                <description>5th conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>16</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ6</name>
                <description>6th conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>20</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ7</name>
                <description>7th conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	Refer to SQ8[3:0] for a definition of channel selection.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>24</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SQ8</name>
                <description>8th conversion of the sequence
	These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence.
	When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
	...
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>28</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>CH0 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>CH1</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xC</name>
                    <description>CH12</description>
                    <value>0xC</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xD</name>
                    <description>CH13</description>
                    <value>0xD</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xE</name>
                    <description>CH14</description>
                    <value>0xE</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xF</name>
                    <description>No channel selected (End of sequence)</description>
                    <value>0xF</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_AWD3TR</name>
            <displayName>ADC_AWD3TR</displayName>
            <description>ADC watchdog threshold register</description>
            <addressOffset>0x2c</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x0FFF0000</resetValue>
            <fields>
              <field>
                <name>LT3</name>
                <description>Analog watchdog 3lower threshold
	These bits are written by software to define the lower threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>HT3</name>
                <description>Analog watchdog 3 higher threshold
	These bits are written by software to define the higher threshold for the analog watchdog.
	Refer to ADC_AWDxTR) on page 395.</description>
                <bitOffset>16</bitOffset>
                <bitWidth>12</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_DR</name>
            <displayName>ADC_DR</displayName>
            <description>ADC data register</description>
            <addressOffset>0x40</addressOffset>
            <size>0x20</size>
            <access>read-only</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>DATA</name>
                <description>Converted data
	These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 389.
	Just after a calibration is complete, DATA[6:0] contains the calibration factor.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>16</bitWidth>
                <access>read-only</access>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_AWD2CR</name>
            <displayName>ADC_AWD2CR</displayName>
            <description>ADC Analog Watchdog 2 Configuration register</description>
            <addressOffset>0xa0</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>AWD2CH0</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH1</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>1</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH2</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>2</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH3</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>3</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH4</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>4</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH5</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>5</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH6</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>6</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH7</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>7</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH8</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>8</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH9</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>9</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH10</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>10</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH11</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>11</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH12</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>12</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH13</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>13</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH14</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>14</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH15</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>15</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH16</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>16</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH17</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>17</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD2CH18</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).
	Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>18</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD2 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD2 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_AWD3CR</name>
            <displayName>ADC_AWD3CR</displayName>
            <description>ADC Analog Watchdog 3 Configuration register</description>
            <addressOffset>0xa4</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>AWD3CH0</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>0</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH1</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>1</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH2</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>2</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH3</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>3</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH4</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>4</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH5</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>5</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH6</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>6</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH7</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>7</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH8</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>8</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH9</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>9</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH10</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>10</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH11</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>11</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH12</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>12</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH13</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>13</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH14</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>14</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH15</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>15</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH16</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>16</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH17</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>17</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>AWD3CH18</name>
                <description>Analog watchdog channel selection
	These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).
	Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>18</bitOffset>
                
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>ADC analog channel-x is not monitored by AWD3 </description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>ADC analog channel-x is monitored by AWD3 </description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CALFACT</name>
            <displayName>ADC_CALFACT</displayName>
            <description>ADC Calibration factor</description>
            <addressOffset>0xb4</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>CALFACT</name>
                <description>Calibration factor
	These bits are written by hardware or by software.
	Once a calibration is complete, they are updated by hardware with the calibration factors.
	Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched.
	Just after a calibration is complete, DATA[6:0] contains the calibration factor.
	Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>7</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>ADC_CCR</name>
            <displayName>ADC_CCR</displayName>
            <description>ADC common configuration register</description>
            <addressOffset>0x308</addressOffset>
            <size>0x20</size>
            <access>read-write</access>
            <resetValue>0x00000000</resetValue>
            <fields>
              <field>
                <name>PRESC</name>
                <description>ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC.
Other: Reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).</description>
                <bitOffset>18</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>input ADC clock not divided</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>input ADC clock divided by 2</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x2</name>
                    <description>input ADC clock divided by 4</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x3</name>
                    <description>input ADC clock divided by 6</description>
                    <value>0x3</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x4</name>
                    <description>input ADC clock divided by 8</description>
                    <value>0x4</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x5</name>
                    <description>input ADC clock divided by 10</description>
                    <value>0x5</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x6</name>
                    <description>input ADC clock divided by 12</description>
                    <value>0x6</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x7</name>
                    <description>input ADC clock divided by 16</description>
                    <value>0x7</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x8</name>
                    <description>input ADC clock divided by 32</description>
                    <value>0x8</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x9</name>
                    <description>input ADC clock divided by 64</description>
                    <value>0x9</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xA</name>
                    <description>input ADC clock divided by 128</description>
                    <value>0xA</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0xB</name>
                    <description>input ADC clock divided by 256</description>
                    <value>0xB</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>VREFEN</name>
                <description>VREFINT enable
	This bit is set and cleared by software to enable/disable the VREFINT.
	Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>22</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>VREFINT disabled</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>VREFINT enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TSEN</name>
                <description>Temperature sensor enable
	This bit is set and cleared by software to enable/disable the temperature sensor.
	Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).</description>
                <bitOffset>23</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>Temperature sensor disabled, DAC_OUT1 connected to ADC channel 12</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>Temperature sensor enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>VBATEN</name>
                <description>VBAT enable
	This bit is set and cleared by software to enable/disable the VBAT channel.
	Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)</description>
                <bitOffset>24</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>B_0x0</name>
                    <description>VBAT channel disabled, DAC_OUT2 connected to ADC channel 14</description>
                    <value>0x0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>B_0x1</name>
                    <description>VBAT channel enabled</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
        </registers>
    </peripheral>
    <peripheral>
      <name>COMP</name>
      <description>COMP1</description>
      <groupName>COMP1</groupName>
      <baseAddress>0x40010200</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x200</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>COMP1_CSR</name>
          <displayName>COMP1_CSR</displayName>
          <description>Comparator 1 control and status
          register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>COMP channel 1 enable bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>INMSEL</name>
              <description>Comparator 2 signal selector for
              inverting input INM</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>INPSEL</name>
              <description>Comparator 2 signal selector for
              non-inverting input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>WINMODE</name>
              <description>Comparator 2 non-inverting input
              selector for window mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WINOUT</name>
              <description>Comparator 2 output
              selector</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>POLARITY</name>
              <description>Comparator 2 polarity
              selector</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HYST</name>
              <description>Comparator 2 hysteresis
              selector</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PWRMODE</name>
              <description>Comparator 2 power mode
              selector</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>BLANKSEL</name>
              <description>Comparator 2 blanking source
              selector</description>
              <bitOffset>20</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>VALUE</name>
              <description>Comparator 2 output status</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LOCK</name>
              <description>COMP2_CSR register lock</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>COMP2_CSR</name>
          <displayName>COMP2_CSR</displayName>
          <description>Comparator 2 control and status
          register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN</name>
              <description>COMP channel 1 enable bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>INMSEL</name>
              <description>Comparator 2 signal selector for
              inverting input INM</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>INPSEL</name>
              <description>Comparator 2 signal selector for
              non-inverting input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>WINMODE</name>
              <description>Comparator 2 non-inverting input
              selector for window mode</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WINOUT</name>
              <description>Comparator 2 output
              selector</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>POLARITY</name>
              <description>Comparator 2 polarity
              selector</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HYST</name>
              <description>Comparator 2 hysteresis
              selector</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PWRMODE</name>
              <description>Comparator 2 power mode
              selector</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>BLANKSEL</name>
              <description>Comparator 2 blanking source
              selector</description>
              <bitOffset>20</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>VALUE</name>
              <description>Comparator 2 output status</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LOCK</name>
              <description>COMP2_CSR register lock</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SYSCFG_VREFBUF</name>
      <description>System configuration controller</description>
      <groupName>SYSCFG</groupName>
      <baseAddress>0x40010000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x100</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>VREFBUF_CSR</name>
          <displayName>VREFBUF_CSR</displayName>
          <description>VREFBUF control and status
          register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>ENVR</name>
              <description>Voltage reference buffer mode enable
              This bit is used to enable the voltage reference
              buffer mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HIZ</name>
              <description>High impedance mode This bit controls
              the analog switch to connect or not the VREF+ pin.
              Refer to Table196: VREF buffer modes for the mode
              descriptions depending on ENVR bit
              configuration.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VRR</name>
              <description>Voltage reference buffer
              ready</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>VRS</name>
              <description>Voltage reference scale These bits
              select the value generated by the voltage reference
              buffer. Other: Reserved</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VREFBUF_CCR</name>
          <displayName>VREFBUF_CCR</displayName>
          <description>VREFBUF calibration control
          register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TRIM</name>
              <description>Trimming code These bits are
              automatically initialized after reset with the
              trimming value stored in the Flash memory during the
              production test. Writing into these bits allows to
              tune the internal reference buffer
              voltage.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFGR1</name>
          <displayName>CFGR1</displayName>
          <description>SYSCFG configuration register
          1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>I2C_PAx_FMP</name>
              <description>Fast Mode Plus (FM+) driving capability
              activation bits</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>I2C2_FMP</name>
              <description>FM+ driving capability activation for
              I2C2</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C1_FMP</name>
              <description>FM+ driving capability activation for
              I2C1</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>I2C_PBx_FMP</name>
              <description>Fast Mode Plus (FM+) driving capability
              activation bits</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>UCPD2_STROBE</name>
              <description>Strobe signal bit for
              UCPD2</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD1_STROBE</name>
              <description>Strobe signal bit for
              UCPD1</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BOOSTEN</name>
              <description>I/O analog switch voltage booster
              enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IR_MOD</name>
              <description>IR Modulation Envelope signal
              selection.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>IR_POL</name>
              <description>IR output polarity
              selection</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PA11_PA12_RMP</name>
              <description>PA11 and PA12 remapping
              bit.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MEM_MODE</name>
              <description>Memory mapping selection
              bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFGR2</name>
          <displayName>CFGR2</displayName>
          <description>SYSCFG configuration register
          1</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>LOCKUP_LOCK</name>
              <description>Cortex-M0+ LOCKUP bit enable
              bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SRAM_PARITY_LOCK</name>
              <description>SRAM parity lock bit</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PVD_LOCK</name>
              <description>PVD lock enable bit</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ECC_LOCK</name>
              <description>ECC error lock bit</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SRAM_PEF</name>
              <description>SRAM parity error flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE0</name>
          <displayName>ITLINE0</displayName>
          <description>interrupt line 0 status
          register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WWDG</name>
              <description>Window watchdog interrupt pending
              flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE1</name>
          <displayName>ITLINE1</displayName>
          <description>interrupt line 1 status
          register</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PVDOUT</name>
              <description>PVD supply monitoring interrupt request
              pending (EXTI line 16).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE2</name>
          <displayName>ITLINE2</displayName>
          <description>interrupt line 2 status
          register</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMP</name>
              <description>TAMP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTC</name>
              <description>RTC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE3</name>
          <displayName>ITLINE3</displayName>
          <description>interrupt line 3 status
          register</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>FLASH_ITF</name>
              <description>FLASH_ITF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FLASH_ECC</name>
              <description>FLASH_ECC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE4</name>
          <displayName>ITLINE4</displayName>
          <description>interrupt line 4 status
          register</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RCC</name>
              <description>RCC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE5</name>
          <displayName>ITLINE5</displayName>
          <description>interrupt line 5 status
          register</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI0</name>
              <description>EXTI0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI1</name>
              <description>EXTI1</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE6</name>
          <displayName>ITLINE6</displayName>
          <description>interrupt line 6 status
          register</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI2</name>
              <description>EXTI2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI3</name>
              <description>EXTI3</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE7</name>
          <displayName>ITLINE7</displayName>
          <description>interrupt line 7 status
          register</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EXTI4</name>
              <description>EXTI4</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI5</name>
              <description>EXTI5</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI6</name>
              <description>EXTI6</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI7</name>
              <description>EXTI7</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI8</name>
              <description>EXTI8</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI9</name>
              <description>EXTI9</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI10</name>
              <description>EXTI10</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI11</name>
              <description>EXTI11</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI12</name>
              <description>EXTI12</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI13</name>
              <description>EXTI13</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI14</name>
              <description>EXTI14</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTI15</name>
              <description>EXTI15</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE8</name>
          <displayName>ITLINE8</displayName>
          <description>interrupt line 8 status
          register</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>UCPD1</name>
              <description>UCPD1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPD2</name>
              <description>UCPD2</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE9</name>
          <displayName>ITLINE9</displayName>
          <description>interrupt line 9 status
          register</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMA1_CH1</name>
              <description>DMA1_CH1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE10</name>
          <displayName>ITLINE10</displayName>
          <description>interrupt line 10 status
          register</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMA1_CH2</name>
              <description>DMA1_CH1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMA1_CH3</name>
              <description>DMA1_CH3</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE11</name>
          <displayName>ITLINE11</displayName>
          <description>interrupt line 11 status
          register</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAMUX</name>
              <description>DMAMUX</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMA1_CH4</name>
              <description>DMA1_CH4</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMA1_CH5</name>
              <description>DMA1_CH5</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMA1_CH6</name>
              <description>DMA1_CH6</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMA1_CH7</name>
              <description>DMA1_CH7</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE12</name>
          <displayName>ITLINE12</displayName>
          <description>interrupt line 12 status
          register</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ADC</name>
              <description>ADC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMP1</name>
              <description>COMP1</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COMP2</name>
              <description>COMP2</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE13</name>
          <displayName>ITLINE13</displayName>
          <description>interrupt line 13 status
          register</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM1_CCU</name>
              <description>TIM1_CCU</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1_TRG</name>
              <description>TIM1_TRG</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1_UPD</name>
              <description>TIM1_UPD</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIM1_BRK</name>
              <description>TIM1_BRK</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE14</name>
          <displayName>ITLINE14</displayName>
          <description>interrupt line 14 status
          register</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM1_CC</name>
              <description>TIM1_CC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE15</name>
          <displayName>ITLINE15</displayName>
          <description>interrupt line 15 status
          register</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM2</name>
              <description>TIM2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE16</name>
          <displayName>ITLINE16</displayName>
          <description>interrupt line 16 status
          register</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM3</name>
              <description>TIM3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE17</name>
          <displayName>ITLINE17</displayName>
          <description>interrupt line 17 status
          register</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM6</name>
              <description>TIM6</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DAC</name>
              <description>DAC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM1</name>
              <description>LPTIM1</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE18</name>
          <displayName>ITLINE18</displayName>
          <description>interrupt line 18 status
          register</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM7</name>
              <description>TIM7</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LPTIM2</name>
              <description>LPTIM2</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE19</name>
          <displayName>ITLINE19</displayName>
          <description>interrupt line 19 status
          register</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM14</name>
              <description>TIM14</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE20</name>
          <displayName>ITLINE20</displayName>
          <description>interrupt line 20 status
          register</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM15</name>
              <description>TIM15</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE21</name>
          <displayName>ITLINE21</displayName>
          <description>interrupt line 21 status
          register</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM16</name>
              <description>TIM16</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE22</name>
          <displayName>ITLINE22</displayName>
          <description>interrupt line 22 status
          register</description>
          <addressOffset>0xD8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIM17</name>
              <description>TIM17</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE23</name>
          <displayName>ITLINE23</displayName>
          <description>interrupt line 23 status
          register</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>I2C1</name>
              <description>I2C1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE24</name>
          <displayName>ITLINE24</displayName>
          <description>interrupt line 24 status
          register</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>I2C2</name>
              <description>I2C2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE25</name>
          <displayName>ITLINE25</displayName>
          <description>interrupt line 25 status
          register</description>
          <addressOffset>0xE4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SPI1</name>
              <description>SPI1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE26</name>
          <displayName>ITLINE26</displayName>
          <description>interrupt line 26 status
          register</description>
          <addressOffset>0xE8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SPI2</name>
              <description>SPI2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE27</name>
          <displayName>ITLINE27</displayName>
          <description>interrupt line 27 status
          register</description>
          <addressOffset>0xEC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>USART1</name>
              <description>USART1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE28</name>
          <displayName>ITLINE28</displayName>
          <description>interrupt line 28 status
          register</description>
          <addressOffset>0xF0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>USART2</name>
              <description>USART2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE29</name>
          <displayName>ITLINE29</displayName>
          <description>interrupt line 29 status
          register</description>
          <addressOffset>0xF4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>USART3</name>
              <description>USART3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART4</name>
              <description>USART4</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>USART5</name>
              <description>USART5</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE30</name>
          <displayName>ITLINE30</displayName>
          <description>interrupt line 30 status
          register</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>USART2</name>
              <description>CEC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ITLINE31</name>
          <displayName>ITLINE31</displayName>
          <description>interrupt line 31 status
          register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RNG</name>
              <description>RNG</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AES</name>
              <description>AES</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>TAMP</name>
      <description>Tamper and backup registers</description>
      <groupName>TAMP</groupName>
      <baseAddress>0x4000B000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0xFFFF0000</resetValue>
          <fields>
            <field>
              <name>TAMP1E</name>
              <description>TAMP1E</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2E</name>
              <description>TAMP2E</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP1E</name>
              <description>ITAMP1E</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP3E</name>
              <description>ITAMP3E</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP4E</name>
              <description>ITAMP4E</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP5E</name>
              <description>ITAMP5E</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP6E</name>
              <description>ITAMP6E</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMP1NOER</name>
              <description>TAMP1NOER</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2NOER</name>
              <description>TAMP2NOER</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP1MSK</name>
              <description>TAMP1MSK</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2MSK</name>
              <description>TAMP2MSK</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP1TRG</name>
              <description>TAMP1TRG</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2TRG</name>
              <description>TAMP2TRG</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>FLTCR</name>
          <displayName>FLTCR</displayName>
          <description>TAMP filter control register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMPFREQ</name>
              <description>TAMPFREQ</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>TAMPFLT</name>
              <description>TAMPFLT</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TAMPPRCH</name>
              <description>TAMPPRCH</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TAMPPUDIS</name>
              <description>TAMPPUDIS</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IER</name>
          <displayName>IER</displayName>
          <description>TAMP interrupt enable register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMP1IE</name>
              <description>TAMP1IE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2IE</name>
              <description>TAMP2IE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP1IE</name>
              <description>ITAMP1IE</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP3IE</name>
              <description>ITAMP3IE</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP4IE</name>
              <description>ITAMP4IE</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP5IE</name>
              <description>ITAMP5IE</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP6IE</name>
              <description>ITAMP6IE</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>TAMP status register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMP1F</name>
              <description>TAMP1F</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2F</name>
              <description>TAMP2F</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP1F</name>
              <description>ITAMP1F</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP3F</name>
              <description>ITAMP3F</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP4F</name>
              <description>ITAMP4F</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP5F</name>
              <description>ITAMP5F</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP6F</name>
              <description>ITAMP6F</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP7F</name>
              <description>ITAMP7F</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>MISR</name>
          <displayName>MISR</displayName>
          <description>TAMP masked interrupt status
          register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TAMP1MF</name>
              <description>TAMP1MF:</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMP2MF</name>
              <description>TAMP2MF</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP1MF</name>
              <description>ITAMP1MF</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP3MF</name>
              <description>ITAMP3MF</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP4MF</name>
              <description>ITAMP4MF</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP5MF</name>
              <description>ITAMP5MF</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITAMP6MF</name>
              <description>ITAMP6MF</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SCR</name>
          <displayName>SCR</displayName>
          <description>TAMP status clear register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CTAMP1F</name>
              <description>CTAMP1F</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTAMP2F</name>
              <description>CTAMP2F</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP1F</name>
              <description>CITAMP1F</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP3F</name>
              <description>CITAMP3F</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP4F</name>
              <description>CITAMP4F</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP5F</name>
              <description>CITAMP5F</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP6F</name>
              <description>CITAMP6F</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITAMP7F</name>
              <description>CITAMP7F</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BKP0R</name>
          <displayName>BKP0R</displayName>
          <description>TAMP backup register</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BKP1R</name>
          <displayName>BKP1R</displayName>
          <description>TAMP backup register</description>
          <addressOffset>0x104</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BKP2R</name>
          <displayName>BKP2R</displayName>
          <description>TAMP backup register</description>
          <addressOffset>0x108</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BKP3R</name>
          <displayName>BKP3R</displayName>
          <description>TAMP backup register</description>
          <addressOffset>0x10C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BKP4R</name>
          <displayName>BKP4R</displayName>
          <description>TAMP backup register</description>
          <addressOffset>0x110</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR2</name>
          <displayName>HWCFGR2</displayName>
          <description>TAMP hardware configuration register
          2</description>
          <addressOffset>0x3EC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PTIONREG_OUT</name>
              <description>PTIONREG_OUT</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>TRUST_ZONE</name>
              <description>TRUST_ZONE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR1</name>
          <displayName>HWCFGR1</displayName>
          <description>TAMP hardware configuration register
          1</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>BACKUP_REGS</name>
              <description>BACKUP_REGS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>TAMPER</name>
              <description>TAMPER</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ACTIVE_TAMPER</name>
              <description>ACTIVE_TAMPER</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>INT_TAMPER</name>
              <description>INT_TAMPER</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>UCPD1</name>
      <description>USB Power Delivery interface</description>
      <groupName>UCPD</groupName>
      <baseAddress>0x4000A000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>UCPD1_UCPD2</name>
        <description>UCPD global interrupt</description>
        <value>8</value>
      </interrupt>
      <registers>
        <register>
          <name>CFG1</name>
          <displayName>CFG1</displayName>
          <description>UCPD configuration register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>HBITCLKDIV</name>
              <description>HBITCLKDIV</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
            </field>
            <field>
              <name>IFRGAP</name>
              <description>IFRGAP</description>
              <bitOffset>6</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>TRANSWIN</name>
              <description>TRANSWIN</description>
              <bitOffset>11</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>PSC_USBPDCLK</name>
              <description>PSC_USBPDCLK</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>RXORDSETEN</name>
              <description>RXORDSETEN</description>
              <bitOffset>20</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
            <field>
              <name>TXDMAEN</name>
              <description>TXDMAEN</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXDMAEN</name>
              <description>RXDMAEN:</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UCPDEN</name>
              <description>UCPDEN</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFG2</name>
          <displayName>CFG2</displayName>
          <description>UCPD configuration register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXFILTDIS</name>
              <description>RXFILTDIS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFILT2N3</name>
              <description>RXFILT2N3</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FORCECLK</name>
              <description>FORCECLK</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUPEN</name>
              <description>WUPEN</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFG3</name>
          <displayName>CFG3</displayName>
          <description>UCPD configuration register 3</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TRIM1_NG_CCRPD</name>
              <description>TRIM1_NG_CCRPD</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TRIM1_NG_CC1A5</name>
              <description>TRIM1_NG_CC1A5</description>
              <bitOffset>4</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>TRIM1_NG_CC3A0</name>
              <description>TRIM1_NG_CC3A0</description>
              <bitOffset>9</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TRIM2_NG_CCRPD</name>
              <description>TRIM2_NG_CCRPD</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TRIM2_NG_CC1A5</name>
              <description>TRIM2_NG_CC1A5</description>
              <bitOffset>20</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>TRIM2_NG_CC3A0</name>
              <description>TRIM2_NG_CC3A0</description>
              <bitOffset>25</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>UCPD control register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXMODE</name>
              <description>TXMODE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TXSEND</name>
              <description>TXSEND</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXHRST</name>
              <description>TXHRST</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXMODE</name>
              <description>RXMODE</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PHYRXEN</name>
              <description>PHYRXEN</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PHYCCSEL</name>
              <description>PHYCCSEL</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ANASUBMODE</name>
              <description>ANASUBMODE</description>
              <bitOffset>7</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ANAMODE</name>
              <description>ANAMODE</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CCENABLE</name>
              <description>CCENABLE</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DBATTEN</name>
              <description>DBATTEN</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FRSRXEN</name>
              <description>FRSRXEN</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FRSTX</name>
              <description>FRSTX</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RDCH</name>
              <description>RDCH</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1TCDIS</name>
              <description>CC1TCDIS</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2TCDIS</name>
              <description>CC2TCDIS</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IMR</name>
          <displayName>IMR</displayName>
          <description>UCPD Interrupt Mask Register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXISIE</name>
              <description>TXISIE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGDISCIE</name>
              <description>TXMSGDISCIE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGSENTIE</name>
              <description>TXMSGSENTIE</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGABTIE</name>
              <description>TXMSGABTIE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTDISCIE</name>
              <description>HRSTDISCIE</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTSENTIE</name>
              <description>HRSTSENTIE</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXUNDIE</name>
              <description>TXUNDIE</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNEIE</name>
              <description>RXNEIE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXORDDETIE</name>
              <description>RXORDDETIE</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXHRSTDETIE</name>
              <description>RXHRSTDETIE</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXOVRIE</name>
              <description>RXOVRIE</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXMSGENDIE</name>
              <description>RXMSGENDIE</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT1IE</name>
              <description>TYPECEVT1IE</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT2IE</name>
              <description>TYPECEVT2IE</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FRSEVTIE</name>
              <description>FRSEVTIE</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>UCPD Status Register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXIS</name>
              <description>TXIS</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGDISC</name>
              <description>TXMSGDISC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGSENT</name>
              <description>TXMSGSENT</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGABT</name>
              <description>TXMSGABT</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTDISC</name>
              <description>HRSTDISC</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTSENT</name>
              <description>HRSTSENT</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXUND</name>
              <description>TXUND</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNE</name>
              <description>RXNE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXORDDET</name>
              <description>RXORDDET</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXHRSTDET</name>
              <description>RXHRSTDET</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXOVR</name>
              <description>RXOVR</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXMSGEND</name>
              <description>RXMSGEND</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXERR</name>
              <description>RXERR</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT1</name>
              <description>TYPECEVT1</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT2</name>
              <description>TYPECEVT2</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPEC_VSTATE_CC1</name>
              <description>TYPEC_VSTATE_CC1</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TYPEC_VSTATE_CC2</name>
              <description>TYPEC_VSTATE_CC2</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>FRSEVT</name>
              <description>FRSEVT</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <displayName>ICR</displayName>
          <description>UCPD Interrupt Clear Register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXMSGDISCCF</name>
              <description>TXMSGDISCCF</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGSENTCF</name>
              <description>TXMSGSENTCF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXMSGABTCF</name>
              <description>TXMSGABTCF</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTDISCCF</name>
              <description>HRSTDISCCF</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HRSTSENTCF</name>
              <description>HRSTSENTCF</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXUNDCF</name>
              <description>TXUNDCF</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXORDDETCF</name>
              <description>RXORDDETCF</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXHRSTDETCF</name>
              <description>RXHRSTDETCF</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXOVRCF</name>
              <description>RXOVRCF</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXMSGENDCF</name>
              <description>RXMSGENDCF</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT1CF</name>
              <description>TYPECEVT1CF</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TYPECEVT2CF</name>
              <description>TYPECEVT2CF</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FRSEVTCF</name>
              <description>FRSEVTCF</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TX_ORDSET</name>
          <displayName>TX_ORDSET</displayName>
          <description>UCPD Tx Ordered Set Type
          Register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXORDSET</name>
              <description>TXORDSET</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TX_PAYSZ</name>
          <displayName>TX_PAYSZ</displayName>
          <description>UCPD Tx Paysize Register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXPAYSZ</name>
              <description>TXPAYSZ</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TXDR</name>
          <displayName>TXDR</displayName>
          <description>UCPD Tx Data Register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXDATA</name>
              <description>TXDATA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_ORDSET</name>
          <displayName>RX_ORDSET</displayName>
          <description>UCPD Rx Ordered Set Register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXORDSET</name>
              <description>RXORDSET</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>RXSOP3OF4</name>
              <description>RXSOP3OF4</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXSOPKINVALID</name>
              <description>RXSOPKINVALID</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_PAYSZ</name>
          <displayName>RX_PAYSZ</displayName>
          <description>UCPD Rx Paysize Register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXPAYSZ</name>
              <description>RXPAYSZ</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RXDR</name>
          <displayName>RXDR</displayName>
          <description>UCPD Receive Data Register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>RXDATA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_ORDEXT1</name>
          <displayName>RX_ORDEXT1</displayName>
          <description>UCPD Rx Ordered Set Extension
          Register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXSOPX1</name>
              <description>RXSOPX1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_ORDEXT2</name>
          <displayName>RX_ORDEXT2</displayName>
          <description>UCPD Rx Ordered Set Extension
          Register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXSOPX2</name>
              <description>RXSOPX2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPVER</name>
          <displayName>IPVER</displayName>
          <description>UCPD IP ID register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>IPVER</name>
              <description>IPVER</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPID</name>
          <displayName>IPID</displayName>
          <description>UCPD IP ID register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00150021</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IPID</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>MID</name>
          <displayName>MID</displayName>
          <description>UCPD IP ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IPID</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="UCPD1">
      <name>UCPD2</name>
      <baseAddress>0x4000A400</baseAddress>
    </peripheral>
    <peripheral>
      <name>LPTIM1</name>
      <description>Low power timer</description>
      <groupName>LPTIM</groupName>
      <baseAddress>0x40007C00</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>ISR</name>
          <displayName>ISR</displayName>
          <description>Interrupt and Status Register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DOWN</name>
              <description>Counter direction change up to
              down</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UP</name>
              <description>Counter direction change down to
              up</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARROK</name>
              <description>Autoreload register update
              OK</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPOK</name>
              <description>Compare register update OK</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTTRIG</name>
              <description>External trigger edge
              event</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARRM</name>
              <description>Autoreload match</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPM</name>
              <description>Compare match</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <displayName>ICR</displayName>
          <description>Interrupt Clear Register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DOWNCF</name>
              <description>Direction change to down Clear
              Flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UPCF</name>
              <description>Direction change to UP Clear
              Flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARROKCF</name>
              <description>Autoreload register update OK Clear
              Flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPOKCF</name>
              <description>Compare register update OK Clear
              Flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTTRIGCF</name>
              <description>External trigger valid edge Clear
              Flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARRMCF</name>
              <description>Autoreload match Clear
              Flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPMCF</name>
              <description>compare match Clear Flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IER</name>
          <displayName>IER</displayName>
          <description>Interrupt Enable Register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DOWNIE</name>
              <description>Direction change to down Interrupt
              Enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UPIE</name>
              <description>Direction change to UP Interrupt
              Enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARROKIE</name>
              <description>Autoreload register update OK Interrupt
              Enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPOKIE</name>
              <description>Compare register update OK Interrupt
              Enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EXTTRIGIE</name>
              <description>External trigger valid edge Interrupt
              Enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARRMIE</name>
              <description>Autoreload match Interrupt
              Enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMPMIE</name>
              <description>Compare match Interrupt
              Enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFGR</name>
          <displayName>CFGR</displayName>
          <description>Configuration Register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ENC</name>
              <description>Encoder mode enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COUNTMODE</name>
              <description>counter mode enabled</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PRELOAD</name>
              <description>Registers update mode</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WAVPOL</name>
              <description>Waveform shape polarity</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WAVE</name>
              <description>Waveform shape</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIMOUT</name>
              <description>Timeout enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TRIGEN</name>
              <description>Trigger enable and
              polarity</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>TRIGSEL</name>
              <description>Trigger selector</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>PRESC</name>
              <description>Clock prescaler</description>
              <bitOffset>9</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>TRGFLT</name>
              <description>Configurable digital filter for
              trigger</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CKFLT</name>
              <description>Configurable digital filter for external
              clock</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CKPOL</name>
              <description>Clock Polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CKSEL</name>
              <description>Clock selector</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>Control Register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RSTARE</name>
              <description>Reset after read enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COUNTRST</name>
              <description>Counter reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CNTSTRT</name>
              <description>Timer start in continuous
              mode</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SNGSTRT</name>
              <description>LPTIM start in single mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ENABLE</name>
              <description>LPTIM Enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CMP</name>
          <displayName>CMP</displayName>
          <description>Compare Register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CMP</name>
              <description>Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>Autoreload Register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Auto reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>Counter Register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>Counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CFGR2</name>
          <displayName>CFGR2</displayName>
          <description>LPTIM configuration register 2</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IN2SEL</name>
              <description>LPTIM1 Input 2 selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>IN1SEL</name>
              <description>LPTIMx Input 1 selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="LPTIM1">
      <name>LPTIM2</name>
      <baseAddress>0x40009400</baseAddress>
    </peripheral>
    <peripheral>
      <name>LPUART</name>
      <description>Universal synchronous asynchronous receiver
      transmitter</description>
      <groupName>USART</groupName>
      <baseAddress>0x40008000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>Control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RXFFIE</name>
              <description>RXFIFO Full interrupt
              enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFEIE</name>
              <description>TXFIFO empty interrupt
              enable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FIFOEN</name>
              <description>FIFO mode enable</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>M1</name>
              <description>Word length</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DEAT</name>
              <description>DEAT0</description>
              <bitOffset>21</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>DEDT0</name>
              <description>DEDT0</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>CMIE</name>
              <description>Character match interrupt
              enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MME</name>
              <description>Mute mode enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>M0</name>
              <description>Word length</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WAKE</name>
              <description>Receiver wakeup method</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PCE</name>
              <description>Parity control enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PS</name>
              <description>Parity selection</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PEIE</name>
              <description>PE interrupt enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXEIE</name>
              <description>interrupt enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transmission complete interrupt
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNEIE</name>
              <description>RXNE interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLEIE</name>
              <description>IDLE interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TE</name>
              <description>Transmitter enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RE</name>
              <description>Receiver enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UESM</name>
              <description>USART enable in Stop mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UE</name>
              <description>USART enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>Control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>ADD4_7</name>
              <description>Address of the USART node</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ADD0_3</name>
              <description>Address of the USART node</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSBFIRST</name>
              <description>Most significant bit first</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAINV</name>
              <description>Binary data inversion</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXINV</name>
              <description>TX pin active level
              inversion</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXINV</name>
              <description>RX pin active level
              inversion</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWAP</name>
              <description>Swap TX/RX pins</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>STOP</name>
              <description>STOP bits</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ADDM7</name>
              <description>7-bit Address Detection/4-bit Address
              Detection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR3</name>
          <displayName>CR3</displayName>
          <description>Control register 3</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TXFTCFG</name>
              <description>TXFIFO threshold
              configuration</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>RXFTIE</name>
              <description>RXFIFO threshold interrupt
              enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFTCFG</name>
              <description>Receive FIFO threshold
              configuration</description>
              <bitOffset>25</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>TXFTIE</name>
              <description>threshold interrupt enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUFIE</name>
              <description>Wakeup from Stop mode interrupt
              enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUS</name>
              <description>Wakeup from Stop mode interrupt flag
              selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DEP</name>
              <description>Driver enable polarity
              selection</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DEM</name>
              <description>Driver enable mode</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DDRE</name>
              <description>DMA Disable on Reception
              Error</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OVRDIS</name>
              <description>Overrun Disable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSIE</name>
              <description>CTS interrupt enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSE</name>
              <description>CTS enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTSE</name>
              <description>RTS enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAT</name>
              <description>DMA enable transmitter</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAR</name>
              <description>DMA enable receiver</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HDSEL</name>
              <description>Half-duplex selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EIE</name>
              <description>Error interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>BRR</name>
          <displayName>BRR</displayName>
          <description>Baud rate register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>BRR</name>
              <description>BRR</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RQR</name>
          <displayName>RQR</displayName>
          <description>Request register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TXFRQ</name>
              <description>Transmit data flush
              request</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFRQ</name>
              <description>Receive data flush request</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MMRQ</name>
              <description>Mute mode request</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBKRQ</name>
              <description>Send break request</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ABRRQ</name>
              <description>Auto baud rate request</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ISR</name>
          <displayName>ISR</displayName>
          <description>Interrupt &amp; status
          register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00C0</resetValue>
          <fields>
            <field>
              <name>TXFT</name>
              <description>TXFIFO threshold flag</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFT</name>
              <description>RXFIFO threshold flag</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXFF</name>
              <description>RXFIFO Full</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXFE</name>
              <description>TXFIFO Empty</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>REACK</name>
              <description>REACK</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEACK</name>
              <description>TEACK</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUF</name>
              <description>WUF</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RWU</name>
              <description>RWU</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBKF</name>
              <description>SBKF</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMF</name>
              <description>CMF</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BUSY</name>
              <description>BUSY</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTS</name>
              <description>CTS</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSIF</name>
              <description>CTSIF</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXE</name>
              <description>TXE</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TC</name>
              <description>TC</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXNE</name>
              <description>RXNE</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLE</name>
              <description>IDLE</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ORE</name>
              <description>ORE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NF</name>
              <description>NF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FE</name>
              <description>FE</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PE</name>
              <description>PE</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <displayName>ICR</displayName>
          <description>Interrupt flag clear register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>WUCF</name>
              <description>Wakeup from Stop mode clear
              flag</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMCF</name>
              <description>Character match clear flag</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSCF</name>
              <description>CTS clear flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCCF</name>
              <description>Transmission complete clear
              flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>IDLECF</name>
              <description>Idle line detected clear
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ORECF</name>
              <description>Overrun error clear flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NCF</name>
              <description>Noise detected clear flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FECF</name>
              <description>Framing error clear flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PECF</name>
              <description>Parity error clear flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RDR</name>
          <displayName>RDR</displayName>
          <description>Receive data register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>RDR</name>
              <description>Receive data value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TDR</name>
          <displayName>TDR</displayName>
          <description>Transmit data register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TDR</name>
              <description>Transmit data value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PRESC</name>
          <displayName>PRESC</displayName>
          <description>Prescaler register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PRESCALER</name>
              <description>Clock prescaler</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR2</name>
          <displayName>HWCFGR2</displayName>
          <description>LPUART Hardware Configuration register
          2</description>
          <addressOffset>0x3EC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000013</resetValue>
          <fields>
            <field>
              <name>CFG1</name>
              <description>LUART hardware configuration
              1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG2</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR1</name>
          <displayName>HWCFGR1</displayName>
          <description>LPUART Hardware Configuration register
          1</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x31100000</resetValue>
          <fields>
            <field>
              <name>CFG1</name>
              <description>LUART hardware configuration
              1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG2</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG3</name>
              <description>LUART hardware configuration
              1</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG4</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG5</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG6</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG7</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>CFG8</name>
              <description>LUART hardware configuration
              2</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000023</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00130003</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>HDMI_CEC</name>
      <description>HDMI-CEC</description>
      <groupName>CEC</groupName>
      <baseAddress>0x40007800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CEC_CR</name>
          <displayName>CEC_CR</displayName>
          <description>CEC control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CECEN</name>
              <description>CEC Enable The CECEN bit is set and
              cleared by software. CECEN=1 starts message reception
              and enables the TXSOM control. CECEN=0 disables the
              CEC peripheral, clears all bits of CEC_CR register
              and aborts any on-going reception or
              transmission.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXSOM</name>
              <description>Tx Start Of Message TXSOM is set by
              software to command transmission of the first byte of
              a CEC message. If the CEC message consists of only
              one byte, TXEOM must be set before of TXSOM.
              Start-Bit is effectively started on the CEC line
              after SFT is counted. If TXSOM is set while a message
              reception is ongoing, transmission will start after
              the end of reception. TXSOM is cleared by hardware
              after the last byte of the message is sent with a
              positive acknowledge (TXEND=1), in case of
              transmission underrun (TXUDR=1), negative acknowledge
              (TXACKE=1), and transmission error (TXERR=1). It is
              also cleared by CECEN=0. It is not cleared and
              transmission is automatically retried in case of
              arbitration lost (ARBLST=1). TXSOM can be also used
              as a status bit informing application whether any
              transmission request is pending or under execution.
              The application can abort a transmission request at
              any time by clearing the CECEN bit. Note: TXSOM must
              be set when CECEN=1 TXSOM must be set when
              transmission data is available into TXDR HEADERs
              first four bits containing own peripheral address are
              taken from TXDR[7:4], not from CEC_CFGR.OAR which is
              used only for reception</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXEOM</name>
              <description>Tx End Of Message The TXEOM bit is set
              by software to command transmission of the last byte
              of a CEC message. TXEOM is cleared by hardware at the
              same time and under the same conditions as for TXSOM.
              Note: TXEOM must be set when CECEN=1 TXEOM must be
              set before writing transmission data to TXDR If TXEOM
              is set when TXSOM=0, transmitted message will consist
              of 1 byte (HEADER) only (PING message)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CEC_CFGR</name>
          <displayName>CEC_CFGR</displayName>
          <description>This register is used to configure the
          HDMI-CEC controller. It is mandatory to write CEC_CFGR
          only when CECEN=0.</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SFT</name>
              <description>Signal Free Time SFT bits are set by
              software. In the SFT=0x0 configuration the number of
              nominal data bit periods waited before transmission
              is ruled by hardware according to the transmission
              history. In all the other configurations the SFT
              number is determined by software. * 0x0 ** 2.5
              Data-Bit periods if CEC is the last bus initiator
              with unsuccessful transmission (ARBLST=1, TXERR=1,
              TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is
              the new bus initiator ** 6 Data-Bit periods if CEC is
              the last bus initiator with successful transmission
              (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2:
              1.5 nominal data bit periods * 0x3: 2.5 nominal data
              bit periods * 0x4: 3.5 nominal data bit periods *
              0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal
              data bit periods * 0x7: 6.5 nominal data bit
              periods</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>RXTOL</name>
              <description>Rx-Tolerance The RXTOL bit is set and
              cleared by software. ** Start-Bit, +/- 200 s rise,
              +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350
              s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall
              ** Data-Bit: +/-300 s rise, +/- 500 s
              fall</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BRESTP</name>
              <description>Rx-Stop on Bit Rising Error The BRESTP
              bit is set and cleared by software.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BREGEN</name>
              <description>Generate Error-Bit on Bit Rising Error
              The BREGEN bit is set and cleared by software. Note:
              If BRDNOGEN=0, an Error-bit is generated upon BRE
              detection with BRESTP=1 in broadcast even if
              BREGEN=0</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBPEGEN</name>
              <description>Generate Error-Bit on Long Bit Period
              Error The LBPEGEN bit is set and cleared by software.
              Note: If BRDNOGEN=0, an Error-bit is generated upon
              LBPE detection in broadcast even if
              LBPEGEN=0</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BRDNOGEN</name>
              <description>Avoid Error-Bit Generation in Broadcast
              The BRDNOGEN bit is set and cleared by
              software.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SFTOPT</name>
              <description>SFT Option Bit The SFTOPT bit is set and
              cleared by software.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OAR</name>
              <description>Own addresses configuration The OAR bits
              are set by software to select which destination
              logical addresses has to be considered in receive
              mode. Each bit, when set, enables the CEC logical
              address identified by the given bit position. At the
              end of HEADER reception, the received destination
              address is compared with the enabled addresses. In
              case of matching address, the incoming message is
              acknowledged and received. In case of non-matching
              address, the incoming message is received only in
              listen mode (LSTN=1), but without acknowledge sent.
              Broadcast messages are always received. Example: OAR
              = 0b000 0000 0010 0001 means that CEC acknowledges
              addresses 0x0 and 0x5. Consequently, each message
              directed to one of these addresses is
              received.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>15</bitWidth>
            </field>
            <field>
              <name>LSTN</name>
              <description>Listen mode LSTN bit is set and cleared
              by software.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CEC_TXDR</name>
          <displayName>CEC_TXDR</displayName>
          <description>CEC Tx data register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXD</name>
              <description>Tx Data register. TXD is a write-only
              register containing the data byte to be transmitted.
              Note: TXD must be written when
              TXSTART=1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CEC_RXDR</name>
          <displayName>CEC_RXDR</displayName>
          <description>CEC Rx Data Register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXD</name>
              <description>Rx Data register. RXD is read-only and
              contains the last data byte which has been received
              from the CEC line.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CEC_ISR</name>
          <displayName>CEC_ISR</displayName>
          <description>CEC Interrupt and Status
          Register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXBR</name>
              <description>Rx-Byte Received The RXBR bit is set by
              hardware to inform application that a new byte has
              been received from the CEC line and stored into the
              RXD buffer. RXBR is cleared by software write at
              1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXEND</name>
              <description>End Of Reception RXEND is set by
              hardware to inform application that the last byte of
              a CEC message is received from the CEC line and
              stored into the RXD buffer. RXEND is set at the same
              time of RXBR. RXEND is cleared by software write at
              1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXOVR</name>
              <description>Rx-Overrun RXOVR is set by hardware if
              RXBR is not yet cleared at the time a new byte is
              received on the CEC line and stored into RXD. RXOVR
              assertion stops message reception so that no
              acknowledge is sent. In case of broadcast, a negative
              acknowledge is sent. RXOVR is cleared by software
              write at 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BRE</name>
              <description>Rx-Bit Rising Error BRE is set by
              hardware in case a Data-Bit waveform is detected with
              Bit Rising Error. BRE is set either at the time the
              misplaced rising edge occurs, or at the end of the
              maximum BRE tolerance allowed by RXTOL, in case
              rising edge is still longing. BRE stops message
              reception if BRESTP=1. BRE generates an Error-Bit on
              the CEC line if BREGEN=1. BRE is cleared by software
              write at 1.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBPE</name>
              <description>Rx-Short Bit Period Error SBPE is set by
              hardware in case a Data-Bit waveform is detected with
              Short Bit Period Error. SBPE is set at the time the
              anticipated falling edge occurs. SBPE generates an
              Error-Bit on the CEC line. SBPE is cleared by
              software write at 1.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBPE</name>
              <description>Rx-Long Bit Period Error LBPE is set by
              hardware in case a Data-Bit waveform is detected with
              Long Bit Period Error. LBPE is set at the end of the
              maximum bit-extension tolerance allowed by RXTOL, in
              case falling edge is still longing. LBPE always stops
              reception of the CEC message. LBPE generates an
              Error-Bit on the CEC line if LBPEGEN=1. In case of
              broadcast, Error-Bit is generated even in case of
              LBPEGEN=0. LBPE is cleared by software write at
              1.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXACKE</name>
              <description>Rx-Missing Acknowledge In receive mode,
              RXACKE is set by hardware to inform application that
              no acknowledge was seen on the CEC line. RXACKE
              applies only for broadcast messages and in listen
              mode also for not directly addressed messages
              (destination address not enabled in OAR). RXACKE
              aborts message reception. RXACKE is cleared by
              software write at 1.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARBLST</name>
              <description>Arbitration Lost ARBLST is set by
              hardware to inform application that CEC device is
              switching to reception due to arbitration lost event
              following the TXSOM command. ARBLST can be due either
              to a contending CEC device starting earlier or
              starting at the same time but with higher HEADER
              priority. After ARBLST assertion TXSOM bit keeps
              pending for next transmission attempt. ARBLST is
              cleared by software write at 1.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXBR</name>
              <description>Tx-Byte Request TXBR is set by hardware
              to inform application that the next transmission data
              has to be written to TXDR. TXBR is set when the 4th
              bit of currently transmitted byte is sent.
              Application must write the next byte to TXDR within 6
              nominal data-bit periods before transmission underrun
              error occurs (TXUDR). TXBR is cleared by software
              write at 1.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXEND</name>
              <description>End of Transmission TXEND is set by
              hardware to inform application that the last byte of
              the CEC message has been successfully transmitted.
              TXEND clears the TXSOM and TXEOM control bits. TXEND
              is cleared by software write at 1.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXUDR</name>
              <description>Tx-Buffer Underrun In transmission mode,
              TXUDR is set by hardware if application was not in
              time to load TXDR before of next byte transmission.
              TXUDR aborts message transmission and clears TXSOM
              and TXEOM control bits. TXUDR is cleared by software
              write at 1</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXERR</name>
              <description>Tx-Error In transmission mode, TXERR is
              set by hardware if the CEC initiator detects low
              impedance on the CEC line while it is released. TXERR
              aborts message transmission and clears TXSOM and
              TXEOM controls. TXERR is cleared by software write at
              1.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXACKE</name>
              <description>Tx-Missing Acknowledge Error In
              transmission mode, TXACKE is set by hardware to
              inform application that no acknowledge was received.
              In case of broadcast transmission, TXACKE informs
              application that a negative acknowledge was received.
              TXACKE aborts message transmission and clears TXSOM
              and TXEOM controls. TXACKE is cleared by software
              write at 1.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CEC_IER</name>
          <displayName>CEC_IER</displayName>
          <description>CEC interrupt enable register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXBRIE</name>
              <description>Rx-Byte Received Interrupt Enable The
              RXBRIE bit is set and cleared by
              software.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXENDIE</name>
              <description>End Of Reception Interrupt Enable The
              RXENDIE bit is set and cleared by
              software.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXOVRIE</name>
              <description>Rx-Buffer Overrun Interrupt Enable The
              RXOVRIE bit is set and cleared by
              software.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BREIE</name>
              <description>Bit Rising Error Interrupt Enable The
              BREIE bit is set and cleared by
              software.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBPEIE</name>
              <description>Short Bit Period Error Interrupt Enable
              The SBPEIE bit is set and cleared by
              software.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>LBPEIE</name>
              <description>Long Bit Period Error Interrupt Enable
              The LBPEIE bit is set and cleared by
              software.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXACKIE</name>
              <description>Rx-Missing Acknowledge Error Interrupt
              Enable The RXACKIE bit is set and cleared by
              software.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARBLSTIE</name>
              <description>Arbitration Lost Interrupt Enable The
              ARBLSTIE bit is set and cleared by
              software.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXBRIE</name>
              <description>Tx-Byte Request Interrupt Enable The
              TXBRIE bit is set and cleared by
              software.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXENDIE</name>
              <description>Tx-End Of Message Interrupt Enable The
              TXENDIE bit is set and cleared by
              software.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXUDRIE</name>
              <description>Tx-Underrun Interrupt Enable The TXUDRIE
              bit is set and cleared by software.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXERRIE</name>
              <description>Tx-Error Interrupt Enable The TXERRIE
              bit is set and cleared by software.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXACKIE</name>
              <description>Tx-Missing Acknowledge Error Interrupt
              Enable The TXACKEIE bit is set and cleared by
              software.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DAC</name>
      <description>DAC</description>
      <groupName>DAC</groupName>
      <baseAddress>0x40007400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DAC_CR</name>
          <displayName>DAC_CR</displayName>
          <description>DAC control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN1</name>
              <description>DAC channel1 enable This bit is set and
              cleared by software to enable/disable DAC
              channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEN1</name>
              <description>DAC channel1 trigger
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL1</name>
              <description>DAC channel1 trigger selection These
              bits select the external event used to trigger DAC
              channel1. Note: Only used if bit TEN1 = 1 (DAC
              channel1 trigger enabled).</description>
              <bitOffset>2</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>WAVE1</name>
              <description>DAC channel1 noise/triangle wave
              generation enable These bits are set and cleared by
              software. Note: Only used if bit TEN1 = 1 (DAC
              channel1 trigger enabled).</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MAMP1</name>
              <description>DAC channel1 mask/amplitude selector
              These bits are written by software to select mask in
              wave generation mode or amplitude in triangle
              generation mode. = 1011: Unmask bits[11:0] of LFSR/
              triangle amplitude equal to 4095</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>DMAEN1</name>
              <description>DAC channel1 DMA enable This bit is set
              and cleared by software.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAUDRIE1</name>
              <description>DAC channel1 DMA Underrun Interrupt
              enable This bit is set and cleared by
              software.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CEN1</name>
              <description>DAC Channel 1 calibration enable This
              bit is set and cleared by software to enable/disable
              DAC channel 1 calibration, it can be written only if
              bit EN1=0 into DAC_CR (the calibration mode can be
              entered/exit only when the DAC channel is disabled)
              Otherwise, the write operation is
              ignored.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EN2</name>
              <description>DAC channel2 enable This bit is set and
              cleared by software to enable/disable DAC
              channel2.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEN2</name>
              <description>DAC channel2 trigger
              enable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL2</name>
              <description>DAC channel2 trigger selection These
              bits select the external event used to trigger DAC
              channel2 Note: Only used if bit TEN2 = 1 (DAC
              channel2 trigger enabled).</description>
              <bitOffset>18</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>WAVE2</name>
              <description>DAC channel2 noise/triangle wave
              generation enable These bits are set/reset by
              software. 1x: Triangle wave generation enabled Note:
              Only used if bit TEN2 = 1 (DAC channel2 trigger
              enabled)</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MAMP2</name>
              <description>DAC channel2 mask/amplitude selector
              These bits are written by software to select mask in
              wave generation mode or amplitude in triangle
              generation mode. = 1011: Unmask bits[11:0] of LFSR/
              triangle amplitude equal to 4095</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>DMAEN2</name>
              <description>DAC channel2 DMA enable This bit is set
              and cleared by software.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAUDRIE2</name>
              <description>DAC channel2 DMA underrun interrupt
              enable This bit is set and cleared by
              software.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CEN2</name>
              <description>DAC Channel 2 calibration enable This
              bit is set and cleared by software to enable/disable
              DAC channel 2 calibration, it can be written only if
              bit EN2=0 into DAC_CR (the calibration mode can be
              entered/exit only when the DAC channel is disabled)
              Otherwise, the write operation is
              ignored.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SWTRGR</name>
          <displayName>DAC_SWTRGR</displayName>
          <description>DAC software trigger register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SWTRIG1</name>
              <description>DAC channel1 software trigger This bit
              is set by software to trigger the DAC in software
              trigger mode. Note: This bit is cleared by hardware
              (one APB1 clock cycle later) once the DAC_DHR1
              register value has been loaded into the DAC_DOR1
              register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWTRIG2</name>
              <description>DAC channel2 software trigger This bit
              is set by software to trigger the DAC in software
              trigger mode. Note: This bit is cleared by hardware
              (one APB1 clock cycle later) once the DAC_DHR2
              register value has been loaded into the DAC_DOR2
              register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12R1</name>
          <displayName>DAC_DHR12R1</displayName>
          <description>DAC channel1 12-bit right-aligned data
          holding register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit right-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12L1</name>
          <displayName>DAC_DHR12L1</displayName>
          <description>DAC channel1 12-bit left aligned data
          holding register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit left-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel1.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR8R1</name>
          <displayName>DAC_DHR8R1</displayName>
          <description>DAC channel1 8-bit right aligned data
          holding register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 8-bit right-aligned data
              These bits are written by software which specifies
              8-bit data for DAC channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12R2</name>
          <displayName>DAC_DHR12R2</displayName>
          <description>DAC channel2 12-bit right aligned data
          holding register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 12-bit right-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel2.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12L2</name>
          <displayName>DAC_DHR12L2</displayName>
          <description>DAC channel2 12-bit left aligned data
          holding register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 12-bit left-aligned data
              These bits are written by software which specify
              12-bit data for DAC channel2.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR8R2</name>
          <displayName>DAC_DHR8R2</displayName>
          <description>DAC channel2 8-bit right-aligned data
          holding register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 8-bit right-aligned data
              These bits are written by software which specifies
              8-bit data for DAC channel2.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12RD</name>
          <displayName>DAC_DHR12RD</displayName>
          <description>Dual DAC 12-bit right-aligned data holding
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit right-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 12-bit right-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel2.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR12LD</name>
          <displayName>DAC_DHR12LD</displayName>
          <description>DUAL DAC 12-bit left aligned data holding
          register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit left-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel1.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 12-bit left-aligned data
              These bits are written by software which specifies
              12-bit data for DAC channel2.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DHR8RD</name>
          <displayName>DAC_DHR8RD</displayName>
          <description>DUAL DAC 8-bit right aligned data holding
          register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 8-bit right-aligned data
              These bits are written by software which specifies
              8-bit data for DAC channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>DACC2DHR</name>
              <description>DAC channel2 8-bit right-aligned data
              These bits are written by software which specifies
              8-bit data for DAC channel2.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DOR1</name>
          <displayName>DAC_DOR1</displayName>
          <description>DAC channel1 data output
          register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DOR</name>
              <description>DAC channel1 data output These bits are
              read-only, they contain data output for DAC
              channel1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_DOR2</name>
          <displayName>DAC_DOR2</displayName>
          <description>DAC channel2 data output
          register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC2DOR</name>
              <description>DAC channel2 data output These bits are
              read-only, they contain data output for DAC
              channel2.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SR</name>
          <displayName>DAC_SR</displayName>
          <description>DAC status register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAUDR1</name>
              <description>DAC channel1 DMA underrun flag This bit
              is set by hardware and cleared by software (by
              writing it to 1).</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAL_FLAG1</name>
              <description>DAC Channel 1 calibration offset status
              This bit is set and cleared by hardware</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BWST1</name>
              <description>DAC Channel 1 busy writing sample time
              flag This bit is systematically set just after Sample
              &amp; Hold mode enable and is set each time the
              software writes the register DAC_SHSR1, It is cleared
              by hardware when the write operation of DAC_SHSR1 is
              complete. (It takes about 3LSI periods of
              synchronization).</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMAUDR2</name>
              <description>DAC channel2 DMA underrun flag This bit
              is set by hardware and cleared by software (by
              writing it to 1).</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAL_FLAG2</name>
              <description>DAC Channel 2 calibration offset status
              This bit is set and cleared by hardware</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BWST2</name>
              <description>DAC Channel 2 busy writing sample time
              flag This bit is systematically set just after Sample
              &amp; Hold mode enable and is set each time the
              software writes the register DAC_SHSR2, It is cleared
              by hardware when the write operation of DAC_SHSR2 is
              complete. (It takes about 3 LSI periods of
              synchronization).</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_CCR</name>
          <displayName>DAC_CCR</displayName>
          <description>DAC calibration control
          register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OTRIM1</name>
              <description>DAC Channel 1 offset trimming
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>OTRIM2</name>
              <description>DAC Channel 2 offset trimming
              value</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_MCR</name>
          <displayName>DAC_MCR</displayName>
          <description>DAC mode control register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MODE1</name>
              <description>DAC Channel 1 mode These bits can be
              written only when the DAC is disabled and not in the
              calibration mode (when bit EN1=0 and bit CEN1 =0 in
              the DAC_CR register). If EN1=1 or CEN1 =1 the write
              operation is ignored. They can be set and cleared by
              software to select the DAC Channel 1 mode: DAC
              Channel 1 in normal Mode DAC Channel 1 in sample
              &amp;amp; hold mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MODE2</name>
              <description>DAC Channel 2 mode These bits can be
              written only when the DAC is disabled and not in the
              calibration mode (when bit EN2=0 and bit CEN2 =0 in
              the DAC_CR register). If EN2=1 or CEN2 =1 the write
              operation is ignored. They can be set and cleared by
              software to select the DAC Channel 2 mode: DAC
              Channel 2 in normal Mode DAC Channel 2 in sample
              &amp;amp; hold mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SHSR1</name>
          <displayName>DAC_SHSR1</displayName>
          <description>DAC Sample and Hold sample time register
          1</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TSAMPLE1</name>
              <description>DAC Channel 1 sample Time (only valid in
              sample &amp;amp; hold mode) These bits can be written
              when the DAC channel1 is disabled or also during
              normal operation. in the latter case, the write can
              be done only when BWSTx of DAC_SR register is low, If
              BWSTx=1, the write operation is
              ignored.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SHSR2</name>
          <displayName>DAC_SHSR2</displayName>
          <description>DAC Sample and Hold sample time register
          2</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TSAMPLE2</name>
              <description>DAC Channel 2 sample Time (only valid in
              sample &amp;amp; hold mode) These bits can be written
              when the DAC channel2 is disabled or also during
              normal operation. in the latter case, the write can
              be done only when BWSTx of DAC_SR register is low, if
              BWSTx=1, the write operation is
              ignored.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SHHR</name>
          <displayName>DAC_SHHR</displayName>
          <description>DAC Sample and Hold hold time
          register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00010001</resetValue>
          <fields>
            <field>
              <name>THOLD1</name>
              <description>DAC Channel 1 hold Time (only valid in
              sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x
              T LSI</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
            <field>
              <name>THOLD2</name>
              <description>DAC Channel 2 hold time (only valid in
              sample &amp;amp; hold mode). Hold time= (THOLD[9:0])
              x T LSI</description>
              <bitOffset>16</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_SHRR</name>
          <displayName>DAC_SHRR</displayName>
          <description>DAC Sample and Hold refresh time
          register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00010001</resetValue>
          <fields>
            <field>
              <name>TREFRESH1</name>
              <description>DAC Channel 1 refresh Time (only valid
              in sample &amp;amp; hold mode) Refresh time=
              (TREFRESH[7:0]) x T LSI</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>TREFRESH2</name>
              <description>DAC Channel 2 refresh Time (only valid
              in sample &amp;amp; hold mode) Refresh time=
              (TREFRESH[7:0]) x T LSI</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IP_HWCFGR0</name>
          <displayName>IP_HWCFGR0</displayName>
          <description>DAC IP Hardware Configuration
          Register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00001111</resetValue>
          <fields>
            <field>
              <name>DUAL</name>
              <description>Dual DAC capability</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>LFSR</name>
              <description>Pseudonoise wave generation
              capability</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TRIANGLE</name>
              <description>Triangle wave generation
              capability</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>SAMPLE</name>
              <description>Sample and hold mode
              capability</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>OR_CFG</name>
              <description>option register bit width</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000031</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00110011</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C1</name>
      <description>Inter-integrated circuit</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40005400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C1</name>
        <description>I2C1 global interrupt</description>
        <value>23</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>Control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PE</name>
              <description>Peripheral enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXIE</name>
              <description>TX Interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXIE</name>
              <description>RX Interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADDRIE</name>
              <description>Address match interrupt enable (slave
              only)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NACKIE</name>
              <description>Not acknowledge received interrupt
              enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>STOPIE</name>
              <description>STOP detection Interrupt
              enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TCIE</name>
              <description>Transfer Complete interrupt
              enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ERRIE</name>
              <description>Error interrupts enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DNF</name>
              <description>Digital noise filter</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ANFOFF</name>
              <description>Analog noise filter OFF</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TXDMAEN</name>
              <description>DMA transmission requests
              enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RXDMAEN</name>
              <description>DMA reception requests
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SBC</name>
              <description>Slave byte control</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NOSTRETCH</name>
              <description>Clock stretching disable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUPEN</name>
              <description>Wakeup from STOP enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>GCEN</name>
              <description>General call enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SMBHEN</name>
              <description>SMBus Host address enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SMBDEN</name>
              <description>SMBus Device Default address
              enable</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALERTEN</name>
              <description>SMBUS alert enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PECEN</name>
              <description>PEC enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>Control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PECBYTE</name>
              <description>Packet error checking byte</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>AUTOEND</name>
              <description>Automatic end mode (master
              mode)</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RELOAD</name>
              <description>NBYTES reload mode</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NBYTES</name>
              <description>Number of bytes</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>NACK</name>
              <description>NACK generation (slave
              mode)</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>STOP</name>
              <description>Stop generation (master
              mode)</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>START</name>
              <description>Start generation</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HEAD10R</name>
              <description>10-bit address header only read
              direction (master receiver mode)</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADD10</name>
              <description>10-bit addressing mode (master
              mode)</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RD_WRN</name>
              <description>Transfer direction (master
              mode)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SADD</name>
              <description>Slave address bit (master
              mode)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OAR1</name>
          <displayName>OAR1</displayName>
          <description>Own address register 1</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OA1_0</name>
              <description>Interface address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OA1_7_1</name>
              <description>Interface address</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
            <field>
              <name>OA1_8_9</name>
              <description>Interface address</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OA1MODE</name>
              <description>Own Address 1 10-bit mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OA1EN</name>
              <description>Own Address 1 enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OAR2</name>
          <displayName>OAR2</displayName>
          <description>Own address register 2</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OA2</name>
              <description>Interface address</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
            <field>
              <name>OA2MSK</name>
              <description>Own Address 2 masks</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OA2EN</name>
              <description>Own Address 2 enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMINGR</name>
          <displayName>TIMINGR</displayName>
          <description>Timing register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SCLL</name>
              <description>SCL low period (master
              mode)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SCLH</name>
              <description>SCL high period (master
              mode)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>SDADEL</name>
              <description>Data hold time</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>SCLDEL</name>
              <description>Data setup time</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>PRESC</name>
              <description>Timing prescaler</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUTR</name>
          <displayName>TIMEOUTR</displayName>
          <description>Status register 1</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TIMEOUTA</name>
              <description>Bus timeout A</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
            <field>
              <name>TIDLE</name>
              <description>Idle clock timeout
              detection</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIMOUTEN</name>
              <description>Clock timeout enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIMEOUTB</name>
              <description>Bus timeout B</description>
              <bitOffset>16</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
            <field>
              <name>TEXTEN</name>
              <description>Extended clock timeout
              enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ISR</name>
          <displayName>ISR</displayName>
          <description>Interrupt and Status register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>ADDCODE</name>
              <description>Address match code (Slave
              mode)</description>
              <bitOffset>17</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIR</name>
              <description>Transfer direction (Slave
              mode)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUSY</name>
              <description>Bus busy</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ALERT</name>
              <description>SMBus alert</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMEOUT</name>
              <description>Timeout or t_low detection
              flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PECERR</name>
              <description>PEC Error in reception</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVR</name>
              <description>Overrun/Underrun (slave
              mode)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ARLO</name>
              <description>Arbitration lost</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BERR</name>
              <description>Bus error</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TCR</name>
              <description>Transfer Complete Reload</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TC</name>
              <description>Transfer Complete (master
              mode)</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>STOPF</name>
              <description>Stop detection flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>NACKF</name>
              <description>Not acknowledge received
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ADDR</name>
              <description>Address matched (slave
              mode)</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNE</name>
              <description>Receive data register not empty
              (receivers)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXIS</name>
              <description>Transmit interrupt status
              (transmitters)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXE</name>
              <description>Transmit data register empty
              (transmitters)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICR</name>
          <displayName>ICR</displayName>
          <description>Interrupt clear register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ALERTCF</name>
              <description>Alert flag clear</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIMOUTCF</name>
              <description>Timeout detection flag
              clear</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PECCF</name>
              <description>PEC Error flag clear</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OVRCF</name>
              <description>Overrun/Underrun flag
              clear</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARLOCF</name>
              <description>Arbitration lost flag
              clear</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BERRCF</name>
              <description>Bus error flag clear</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>STOPCF</name>
              <description>Stop detection flag clear</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>NACKCF</name>
              <description>Not Acknowledge flag clear</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADDRCF</name>
              <description>Address Matched flag clear</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PECR</name>
          <displayName>PECR</displayName>
          <description>PEC register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PEC</name>
              <description>Packet error checking
              register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>RXDR</name>
          <displayName>RXDR</displayName>
          <description>Receive data register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>8-bit receive data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TXDR</name>
          <displayName>TXDR</displayName>
          <description>Transmit data register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>TXDATA</name>
              <description>8-bit transmit data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="I2C1">
      <name>I2C2</name>
      <baseAddress>0x40005800</baseAddress>
      <interrupt>
        <name>I2C2</name>
        <description>I2C2 global interrupt</description>
        <value>24</value>
      </interrupt>
    </peripheral>
    <peripheral>
      <name>RTC</name>
      <description>Real-time clock</description>
      <groupName>RTC</groupName>
      <baseAddress>0x40002800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>RTC_STAMP</name>
        <description>RTC and TAMP interrupts</description>
        <value>2</value>
      </interrupt>
      <registers>
        <register>
          <name>TR</name>
          <displayName>TR</displayName>
          <description>time register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>PM</name>
              <description>AM/PM notation</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HT</name>
              <description>Hour tens in BCD format</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>HU</name>
              <description>Hour units in BCD format</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MNT</name>
              <description>Minute tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MNU</name>
              <description>Minute units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ST</name>
              <description>Second tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>SU</name>
              <description>Second units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DR</name>
          <displayName>DR</displayName>
          <description>date register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00002101</resetValue>
          <fields>
            <field>
              <name>YT</name>
              <description>Year tens in BCD format</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>YU</name>
              <description>Year units in BCD format</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>WDU</name>
              <description>Week day units</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MT</name>
              <description>Month tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MU</name>
              <description>Month units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>DT</name>
              <description>Date tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DU</name>
              <description>Date units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SSR</name>
          <displayName>SSR</displayName>
          <description>sub second register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SS</name>
              <description>Sub second value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ICSR</name>
          <displayName>ICSR</displayName>
          <description>initialization and status
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000007</resetValue>
          <fields>
            <field>
              <name>ALRAWF</name>
              <description>Alarm A write flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ALRBWF</name>
              <description>Alarm B write flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WUTWF</name>
              <description>Wakeup timer write flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SHPF</name>
              <description>Shift operation pending</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INITS</name>
              <description>Initialization status flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RSF</name>
              <description>Registers synchronization
              flag</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INITF</name>
              <description>Initialization flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INIT</name>
              <description>Initialization mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RECALPF</name>
              <description>Recalibration pending Flag</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PRER</name>
          <displayName>PRER</displayName>
          <description>prescaler register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x007F00FF</resetValue>
          <fields>
            <field>
              <name>PREDIV_A</name>
              <description>Asynchronous prescaler
              factor</description>
              <bitOffset>16</bitOffset>
              <bitWidth>7</bitWidth>
            </field>
            <field>
              <name>PREDIV_S</name>
              <description>Synchronous prescaler
              factor</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>WUTR</name>
          <displayName>WUTR</displayName>
          <description>wakeup timer register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000FFFF</resetValue>
          <fields>
            <field>
              <name>WUT</name>
              <description>Wakeup auto-reload value
              bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>control register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WUCKSEL</name>
              <description>WUCKSEL</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>TSEDGE</name>
              <description>TSEDGE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>REFCKON</name>
              <description>REFCKON</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BYPSHAD</name>
              <description>BYPSHAD</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>FMT</name>
              <description>FMT</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRAE</name>
              <description>ALRAE</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRBE</name>
              <description>ALRBE</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUTE</name>
              <description>WUTE</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSE</name>
              <description>TSE</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRAIE</name>
              <description>ALRAIE</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRBIE</name>
              <description>ALRBIE</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUTIE</name>
              <description>WUTIE</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSIE</name>
              <description>TSIE</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ADD1H</name>
              <description>ADD1H</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SUB1H</name>
              <description>SUB1H</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BKP</name>
              <description>BKP</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>COSEL</name>
              <description>COSEL</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>POL</name>
              <description>POL</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OSEL</name>
              <description>OSEL</description>
              <bitOffset>21</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>COE</name>
              <description>COE</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITSE</name>
              <description>ITSE</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMPTS</name>
              <description>TAMPTS</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMPOE</name>
              <description>TAMPOE</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMPALRM_PU</name>
              <description>TAMPALRM_PU</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TAMPALRM_TYPE</name>
              <description>TAMPALRM_TYPE</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OUT2EN</name>
              <description>OUT2EN</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>WPR</name>
          <displayName>WPR</displayName>
          <description>write protection register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>KEY</name>
              <description>Write protection key</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CALR</name>
          <displayName>CALR</displayName>
          <description>calibration register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CALP</name>
              <description>Increase frequency of RTC by 488.5
              ppm</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CALW8</name>
              <description>Use an 8-second calibration cycle
              period</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CALW16</name>
              <description>Use a 16-second calibration cycle
              period</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CALM</name>
              <description>Calibration minus</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SHIFTR</name>
          <displayName>SHIFTR</displayName>
          <description>shift control register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ADD1S</name>
              <description>Add one second</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SUBFS</name>
              <description>Subtract a fraction of a
              second</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TSTR</name>
          <displayName>TSTR</displayName>
          <description>time stamp time register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SU</name>
              <description>Second units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ST</name>
              <description>Second tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MNU</name>
              <description>Minute units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MNT</name>
              <description>Minute tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>HU</name>
              <description>Hour units in BCD format</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>HT</name>
              <description>Hour tens in BCD format</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>PM</name>
              <description>AM/PM notation</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TSDR</name>
          <displayName>TSDR</displayName>
          <description>time stamp date register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>WDU</name>
              <description>Week day units</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MT</name>
              <description>Month tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MU</name>
              <description>Month units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>DT</name>
              <description>Date tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DU</name>
              <description>Date units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TSSSR</name>
          <displayName>TSSSR</displayName>
          <description>timestamp sub second register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SS</name>
              <description>Sub second value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ALRMAR</name>
          <displayName>ALRMAR</displayName>
          <description>alarm A register</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MSK4</name>
              <description>Alarm A date mask</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WDSEL</name>
              <description>Week day selection</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DT</name>
              <description>Date tens in BCD format</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DU</name>
              <description>Date units or day in BCD
              format</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK3</name>
              <description>Alarm A hours mask</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PM</name>
              <description>AM/PM notation</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HT</name>
              <description>Hour tens in BCD format</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>HU</name>
              <description>Hour units in BCD format</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK2</name>
              <description>Alarm A minutes mask</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MNT</name>
              <description>Minute tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MNU</name>
              <description>Minute units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK1</name>
              <description>Alarm A seconds mask</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ST</name>
              <description>Second tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>SU</name>
              <description>Second units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ALRMASSR</name>
          <displayName>ALRMASSR</displayName>
          <description>alarm A sub second register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MASKSS</name>
              <description>Mask the most-significant bits starting
              at this bit</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>SS</name>
              <description>Sub seconds value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ALRMBR</name>
          <displayName>ALRMBR</displayName>
          <description>alarm B register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MSK4</name>
              <description>Alarm B date mask</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WDSEL</name>
              <description>Week day selection</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DT</name>
              <description>Date tens in BCD format</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DU</name>
              <description>Date units or day in BCD
              format</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK3</name>
              <description>Alarm B hours mask</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>PM</name>
              <description>AM/PM notation</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>HT</name>
              <description>Hour tens in BCD format</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>HU</name>
              <description>Hour units in BCD format</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK2</name>
              <description>Alarm B minutes mask</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MNT</name>
              <description>Minute tens in BCD format</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>MNU</name>
              <description>Minute units in BCD format</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSK1</name>
              <description>Alarm B seconds mask</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ST</name>
              <description>Second tens in BCD format</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>SU</name>
              <description>Second units in BCD format</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ALRMBSSR</name>
          <displayName>ALRMBSSR</displayName>
          <description>alarm B sub second register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>MASKSS</name>
              <description>Mask the most-significant bits starting
              at this bit</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>SS</name>
              <description>Sub seconds value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ALRAF</name>
              <description>ALRAF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRBF</name>
              <description>ALRBF</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUTF</name>
              <description>WUTF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSF</name>
              <description>TSF</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSOVF</name>
              <description>TSOVF</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITSF</name>
              <description>ITSF</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>MISR</name>
          <displayName>MISR</displayName>
          <description>masked interrupt status
          register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ALRAMF</name>
              <description>ALRAMF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ALRBMF</name>
              <description>ALRBMF</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WUTMF</name>
              <description>WUTMF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSMF</name>
              <description>TSMF</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSOVMF</name>
              <description>TSOVMF</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ITSMF</name>
              <description>ITSMF</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SCR</name>
          <displayName>SCR</displayName>
          <description>status clear register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CALRAF</name>
              <description>CALRAF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CALRBF</name>
              <description>CALRBF</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CWUTF</name>
              <description>CWUTF</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSF</name>
              <description>CTSF</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CTSOVF</name>
              <description>CTSOVF</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CITSF</name>
              <description>CITSF</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>HWCFGR</name>
          <displayName>HWCFGR</displayName>
          <description>hardware configuration
          register</description>
          <addressOffset>0x3F0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ALARMB</name>
              <description>ALARMB</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>WAKEUP</name>
              <description>WAKEUP</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>SMOOTH_CALIB</name>
              <description>SMOOTH_CALIB</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TIMESTAMP</name>
              <description>TIMESTAMP</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>OPTIONREG_OUT</name>
              <description>OPTIONREG_OUT</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>TRUST_ZONE</name>
              <description>TRUST_ZONE</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>VERR</name>
          <displayName>VERR</displayName>
          <description>EXTI IP Version register</description>
          <addressOffset>0x3F4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>MINREV</name>
              <description>Minor Revision number</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MAJREV</name>
              <description>Major Revision number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>IPIDR</name>
          <displayName>IPIDR</displayName>
          <description>EXTI Identification register</description>
          <addressOffset>0x3F8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00120033</resetValue>
          <fields>
            <field>
              <name>IPID</name>
              <description>IP Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SIDR</name>
          <displayName>SIDR</displayName>
          <description>EXTI Size ID register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0xA3C5DD01</resetValue>
          <fields>
            <field>
              <name>SID</name>
              <description>Size Identification</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>TIM14</name>
      <description>General purpose timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40002000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM14</name>
        <description>TIM14 global interrupt</description>
        <value>19</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CKD</name>
              <description>Clock division</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CEN</name>
              <description>Counter enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1IE</name>
              <description>Capture/Compare 1 interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1OF</name>
              <description>Capture/Compare 1 overcapture
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IF</name>
              <description>Capture/compare 1 interrupt
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1G</name>
              <description>Capture/compare 1
              generation</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UG</name>
              <description>Update generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Output</name>
          <displayName>CCMR1_Output</displayName>
          <description>capture/compare mode register 1 (output
          mode)</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CC1S</name>
              <description>CC1S</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC1FE</name>
              <description>OC1FE</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1PE</name>
              <description>OC1PE</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M</name>
              <description>OC1M</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC1CE</name>
              <description>OC1CE</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M_3</name>
              <description>Output Compare 1 mode - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Input</name>
          <displayName>CCMR1_Input</displayName>
          <description>capture/compare mode register 1 (input
          mode)</description>
          <alternateRegister>CCMR1_Output</alternateRegister>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IC1F</name>
              <description>Input capture 1 filter</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>ICPCS</name>
              <description>Input capture 1 prescaler</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCER</name>
          <displayName>CCER</displayName>
          <description>capture/compare enable
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC1NP</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1P</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1E</name>
              <description>Capture/Compare 1 output
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>low counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>UIFCPY</name>
              <description>UIF Copy</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Low Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>capture/compare register 1</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR1</name>
              <description>Low Capture/Compare 1
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TISEL</name>
          <displayName>TISEL</displayName>
          <description>TIM timer input selection
          register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TISEL</name>
              <description>TI1[0] to TI1[15] input
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>TIM6</name>
      <description>Basic timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40001000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM6_DAC_LPTIM1</name>
        <description>TIM6 + LPTIM1 and DAC global
        interrupt</description>
        <value>17</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CEN</name>
              <description>Counter enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>MMS</name>
              <description>Master mode selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UDE</name>
              <description>Update DMA request enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UG</name>
              <description>Update generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT</name>
              <description>Low counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>UIFCPY</name>
              <description>UIF Copy</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ARR</name>
              <description>Low Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="TIM6">
      <name>TIM7</name>
      <baseAddress>0x40001400</baseAddress>
      <interrupt>
        <name>TIM7_LPTIM2</name>
        <description>TIM7 + LPTIM2 global interrupt</description>
        <value>18</value>
      </interrupt>
    </peripheral>
    <peripheral>
      <name>TIM2</name>
      <description>General-purpose-timers</description>
      <groupName>TIM</groupName>
      <baseAddress>0x40000000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM2</name>
        <description>TIM2 global interrupt</description>
        <value>15</value>
      </interrupt>
      <interrupt>
        <name>TIM3</name>
        <description>TIM3 global interrupt</description>
        <value>16</value>
      </interrupt>
      <registers>
        <register>
          <name>CR1</name>
          <displayName>CR1</displayName>
          <description>control register 1</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>UIFREMAP</name>
              <description>UIF status bit remapping</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CKD</name>
              <description>Clock division</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ARPE</name>
              <description>Auto-reload preload enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CMS</name>
              <description>Center-aligned mode
              selection</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>DIR</name>
              <description>Direction</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OPM</name>
              <description>One-pulse mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>URS</name>
              <description>Update request source</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDIS</name>
              <description>Update disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CEN</name>
              <description>Counter enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <displayName>CR2</displayName>
          <description>control register 2</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TI1S</name>
              <description>TI1 selection</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MMS</name>
              <description>Master mode selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>CCDS</name>
              <description>Capture/compare DMA
              selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SMCR</name>
          <displayName>SMCR</displayName>
          <description>slave mode control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TS_4_3</name>
              <description>Trigger selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>SMS_3</name>
              <description>Slave mode selection - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ETP</name>
              <description>External trigger polarity</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ECE</name>
              <description>External clock enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>ETPS</name>
              <description>External trigger prescaler</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>ETF</name>
              <description>External trigger filter</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>MSM</name>
              <description>Master/Slave mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TS</name>
              <description>Trigger selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OCCS</name>
              <description>OCREF clear selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SMS</name>
              <description>Slave mode selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DIER</name>
          <displayName>DIER</displayName>
          <description>DMA/Interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TDE</name>
              <description>Trigger DMA request enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4DE</name>
              <description>Capture/Compare 4 DMA request
              enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3DE</name>
              <description>Capture/Compare 3 DMA request
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2DE</name>
              <description>Capture/Compare 2 DMA request
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1DE</name>
              <description>Capture/Compare 1 DMA request
              enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UDE</name>
              <description>Update DMA request enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIE</name>
              <description>Trigger interrupt enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4IE</name>
              <description>Capture/Compare 4 interrupt
              enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3IE</name>
              <description>Capture/Compare 3 interrupt
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2IE</name>
              <description>Capture/Compare 2 interrupt
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IE</name>
              <description>Capture/Compare 1 interrupt
              enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIE</name>
              <description>Update interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC4OF</name>
              <description>Capture/Compare 4 overcapture
              flag</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3OF</name>
              <description>Capture/Compare 3 overcapture
              flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2OF</name>
              <description>Capture/compare 2 overcapture
              flag</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1OF</name>
              <description>Capture/Compare 1 overcapture
              flag</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TIF</name>
              <description>Trigger interrupt flag</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4IF</name>
              <description>Capture/Compare 4 interrupt
              flag</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3IF</name>
              <description>Capture/Compare 3 interrupt
              flag</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2IF</name>
              <description>Capture/Compare 2 interrupt
              flag</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1IF</name>
              <description>Capture/compare 1 interrupt
              flag</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UIF</name>
              <description>Update interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>EGR</name>
          <displayName>EGR</displayName>
          <description>event generation register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TG</name>
              <description>Trigger generation</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4G</name>
              <description>Capture/compare 4
              generation</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3G</name>
              <description>Capture/compare 3
              generation</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2G</name>
              <description>Capture/compare 2
              generation</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1G</name>
              <description>Capture/compare 1
              generation</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>UG</name>
              <description>Update generation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Output</name>
          <displayName>CCMR1_Output</displayName>
          <description>capture/compare mode register 1 (output
          mode)</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OC2M_3</name>
              <description>Output Compare 2 mode - bit
              3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M_3</name>
              <description>Output Compare 1 mode - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2CE</name>
              <description>Output compare 2 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2M</name>
              <description>Output compare 2 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC2PE</name>
              <description>Output compare 2 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC2FE</name>
              <description>Output compare 2 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/Compare 2
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC1CE</name>
              <description>Output compare 1 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1M</name>
              <description>Output compare 1 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC1PE</name>
              <description>Output compare 1 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC1FE</name>
              <description>Output compare 1 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR1_Input</name>
          <displayName>CCMR1_Input</displayName>
          <description>capture/compare mode register 1 (input
          mode)</description>
          <alternateRegister>CCMR1_Output</alternateRegister>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IC2F</name>
              <description>Input capture 2 filter</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>IC2PSC</name>
              <description>Input capture 2 prescaler</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC2S</name>
              <description>Capture/compare 2
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>IC1F</name>
              <description>Input capture 1 filter</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>IC1PSC</name>
              <description>Input capture 1 prescaler</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC1S</name>
              <description>Capture/Compare 1
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR2_Output</name>
          <displayName>CCMR2_Output</displayName>
          <description>capture/compare mode register 2 (output
          mode)</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>OC4M_3</name>
              <description>Output Compare 4 mode - bit
              3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3M_3</name>
              <description>Output Compare 3 mode - bit
              3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4CE</name>
              <description>Output compare 4 clear
              enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4M</name>
              <description>Output compare 4 mode</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC4PE</name>
              <description>Output compare 4 preload
              enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC4FE</name>
              <description>Output compare 4 fast
              enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4S</name>
              <description>Capture/Compare 4
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>OC3CE</name>
              <description>Output compare 3 clear
              enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3M</name>
              <description>Output compare 3 mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>OC3PE</name>
              <description>Output compare 3 preload
              enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>OC3FE</name>
              <description>Output compare 3 fast
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3S</name>
              <description>Capture/Compare 3
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCMR2_Input</name>
          <displayName>CCMR2_Input</displayName>
          <description>capture/compare mode register 2 (input
          mode)</description>
          <alternateRegister>CCMR2_Output</alternateRegister>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>IC4F</name>
              <description>Input capture 4 filter</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>IC4PSC</name>
              <description>Input capture 4 prescaler</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC4S</name>
              <description>Capture/Compare 4
              selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>IC3F</name>
              <description>Input capture 3 filter</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>IC3PSC</name>
              <description>Input capture 3 prescaler</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>CC3S</name>
              <description>Capture/Compare 3
              selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCER</name>
          <displayName>CCER</displayName>
          <description>capture/compare enable
          register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>CC4NP</name>
              <description>Capture/Compare 4 output
              Polarity</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4P</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC4E</name>
              <description>Capture/Compare 4 output
              enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3NP</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3P</name>
              <description>Capture/Compare 3 output
              Polarity</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC3E</name>
              <description>Capture/Compare 3 output
              enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2NP</name>
              <description>Capture/Compare 2 output
              Polarity</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2P</name>
              <description>Capture/Compare 2 output
              Polarity</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC2E</name>
              <description>Capture/Compare 2 output
              enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1NP</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1P</name>
              <description>Capture/Compare 1 output
              Polarity</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CC1E</name>
              <description>Capture/Compare 1 output
              enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT</name>
          <displayName>CNT</displayName>
          <description>counter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CNT_H</name>
              <description>High counter value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>CNT_L</name>
              <description>Low counter value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>PSC</name>
          <displayName>PSC</displayName>
          <description>prescaler</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>PSC</name>
              <description>Prescaler value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ARR</name>
          <displayName>ARR</displayName>
          <description>auto-reload register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>ARR_H</name>
              <description>High Auto-reload value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>ARR_L</name>
              <description>Low Auto-reload value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR1</name>
          <displayName>CCR1</displayName>
          <description>capture/compare register 1</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR1_H</name>
              <description>High Capture/Compare 1 value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>CCR1_L</name>
              <description>Low Capture/Compare 1
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR2</name>
          <displayName>CCR2</displayName>
          <description>capture/compare register 2</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR2_H</name>
              <description>High Capture/Compare 2 value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>CCR2_L</name>
              <description>Low Capture/Compare 2
              value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR3</name>
          <displayName>CCR3</displayName>
          <description>capture/compare register 3</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR3_H</name>
              <description>High Capture/Compare value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>CCR3_L</name>
              <description>Low Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR4</name>
          <displayName>CCR4</displayName>
          <description>capture/compare register 4</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>CCR4_H</name>
              <description>High Capture/Compare value (TIM2
              only)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
            <field>
              <name>CCR4_L</name>
              <description>Low Capture/Compare value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DCR</name>
          <displayName>DCR</displayName>
          <description>DMA control register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DBL</name>
              <description>DMA burst length</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
            <field>
              <name>DBA</name>
              <description>DMA base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DMAR</name>
          <displayName>DMAR</displayName>
          <description>DMA address for full transfer</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>DMAB</name>
              <description>DMA register for burst
              accesses</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>OR1</name>
          <displayName>OR1</displayName>
          <description>TIM option register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>IOCREF_CLR</name>
              <description>IOCREF_CLR</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>AF1</name>
          <displayName>AF1</displayName>
          <description>TIM alternate function option register
          1</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>ETRSEL</name>
              <description>External trigger source
              selection</description>
              <bitOffset>14</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>TISEL</name>
          <displayName>TISEL</displayName>
          <description>TIM alternate function option register
          1</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x0000</resetValue>
          <fields>
            <field>
              <name>TI1SEL</name>
              <description>TI1SEL</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
            <field>
              <name>TI2SEL</name>
              <description>TI2SEL</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="TIM2">
      <name>TIM3</name>
      <baseAddress>0x40000400</baseAddress>
    </peripheral>
  </peripherals>
</device>