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RMUL2025/lib/cmsis_svd/data/NXP/LPC5410x_v0.4.svd

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>LPC5410x</name>
<version>0.4</version>
<!--Content based on v1.0 of the LPC5410x user manual-->
<description>LPC5410x Cortex-M4 MCU; Cortex-M0+ coprocessor</description>
<cpu>
<name>CM4</name>
<!-- revision and core config (mpu, fpu, systick are present) nvic prio = 3 -->
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>1</mpuPresent>
<fpuPresent>1</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>0</vendorSystickConfig>
</cpu>
<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<!--
Software that is described herein is for illustrative purposes only
which provides customers with programming information regarding the
products. This software is supplied "AS IS" without any warranties.
NXP Semiconductors assumes no responsibility or liability for the
use of the software, conveys no license or title under any patent,
copyright, or mask work right to the product. NXP Semiconductors
reserves the right to make changes in the software without
notification. NXP Semiconductors also make no representation or
warranty that such application will be suitable for the specified
use without further testing or modification.
-->
<peripherals>
<peripheral>
<name>GPIO</name>
<description>General Purpose I/O </description>
<groupName>GPIO</groupName>
<baseAddress>0x1C000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x2304</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>50</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0-49</dimIndex>
<name>B%s</name>
<description>Byte pin registers port 0/1; pins PIO0_0 to PIO1_8</description>
<addressOffset>0x000</addressOffset>
<size>1</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction,
masking, or alternate function, except that pins configured as
analog I/O always read as 0. One register for each port pin.
Supported pins depends on the specific device and package. Write:
loads the pins output bit. One register for each port pin. Supported
pins depends on the specific device and package.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>50</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-49</dimIndex>
<name>W%s</name>
<description>Word pin registers port 0/1; pins PIO0_0 to PIO1_8</description>
<addressOffset>0x1000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read
0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to
0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read.
Writing any value other than 0 will set the output bit. One register
for each port pin. Supported pins depends on the specific device and
package.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>DIR%s</name>
<description>Direction registers port 0/1</description>
<addressOffset>0x2000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIRP</name>
<description>Selects pin direction for pin PIOm_n. Supported pins
depends on the specific device and package. 0 = input. 1 =
output.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>MASK%s</name>
<description>Mask register port 0/1</description>
<addressOffset>0x2080</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASKP</name>
<description>Controls which bits corresponding to PIOm_n are active in
the MPORT register. Supported pins depends on the specific device
and package. 0 = Read MPORT: pin state; write MPORT: load output
bit. 1 = Read MPORT: 0; write MPORT: output bit not
affected.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PIN%s</name>
<description>Port pin register port 0/1</description>
<addressOffset>0x2100</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PORT</name>
<description>Reads pin states or loads output bits. Supported pins
depends on the specific device and package. 0 = Read: pin is low;
write: clear output bit. 1 = Read: pin is high; write: set output
bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>MPIN%s</name>
<description>Masked port register port 0/1</description>
<addressOffset>0x2180</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>MPORTP</name>
<description>Masked port register. Supported pins depends on the
specific device and package. 0 = Read: pin is LOW and/or the
corresponding bit in the MASK register is 1; write: clear output bit
if the corresponding bit in the MASK register is 0. 1 = Read: pin is
HIGH and the corresponding bit in the MASK register is 0; write: set
output bit if the corresponding bit in the MASK register is
0.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>SET%s</name>
<description>Write: Set register for port 0/1 Read: output bits for port
0/1</description>
<addressOffset>0x2200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETP</name>
<description>Read or set output bits. Supported pins depends on the
specific device and package. 0 = Read: output bit: write: no
operation. 1 = Read: output bit; write: set output
bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>CLR%s</name>
<description>Clear port 0/1</description>
<addressOffset>0x2280</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLRP</name>
<description>Clear output bits. Supported pins depends on the specific
device and package. 0 = No operation. 1 = Clear output
bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>NOT%s</name>
<description>Toggle port 0/1</description>
<addressOffset>0x2300</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>NOTP</name>
<description>Toggle output bits. Supported pins depends on the specific
device and package. 0 = no operation. 1 = Toggle output
bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x1C004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA</name>
<value>3</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>DMA control.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>DMA controller master enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The DMA controller is disabled. This
clears any triggers that were asserted at the point when
disabled, but does not prevent re-triggering when the DMA
controller is re-enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The DMA controller is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ACTIVEINT</name>
<description>Summarizes whether any enabled interrupts (other than error
interrupts) are pending.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_PENDING</name>
<description>Not pending. No enabled interrupts are
pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. At least one enabled interrupt is
pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEERRINT</name>
<description>Summarizes whether any error interrupts are
pending.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_PENDING</name>
<description>Not pending. No error interrupts are
pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. At least one error interrupt is
pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<name>SRAMBASE</name>
<description>SRAM address of the channel configuration table.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>OFFSET</name>
<description>Address bits 31:9 of the beginning of the DMA descriptor
table. For 18 channels, the table must begin on a 512 byte
boundary.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>ENABLESET0</name>
<description>Channel Enable read and Set for all DMA channels.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable for DMA channels. Bit n enables or disables DMA
channel n. 0 = disabled. 1 = enabled.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>ENABLECLR0</name>
<description>Channel Enable Clear for all DMA channels.</description>
<addressOffset>0x028</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLR</name>
<description>Writing ones to this register clears the corresponding bits
in ENABLESET0. Bit n clears the channel enable bit n.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>ACTIVE0</name>
<description>Channel Active status for all DMA channels.</description>
<addressOffset>0x030</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ACT</name>
<description>Active flag for DMA channel n. Bit n corresponds to DMA
channel n. 0 = not active. 1 = active.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>BUSY0</name>
<description>Channel Busy status for all DMA channels.</description>
<addressOffset>0x038</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BSY</name>
<description>Busy flag for DMA channel n. Bit n corresponds to DMA
channel n. 0 = not busy. 1 = busy.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>ERRINT0</name>
<description>Error Interrupt status for all DMA channels.</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERR</name>
<description>Error Interrupt flag for DMA channel n. Bit n corresponds
to DMA channel n. 0 = error interrupt is not active. 1 = error
interrupt is active.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET0</name>
<description>Interrupt Enable read and Set for all DMA channels.</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTEN</name>
<description>Interrupt Enable read and set for DMA channel n. Bit n
corresponds to DMA channel n. 0 = interrupt for DMA channel is
disabled. 1 = interrupt for DMA channel is enabled.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR0</name>
<description>Interrupt Enable Clear for all DMA channels.</description>
<addressOffset>0x050</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLR</name>
<description>Writing ones to this register clears corresponding bits in
the INTENSET0. Bit n corresponds to DMA channel n.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTA0</name>
<description>Interrupt A status for all DMA channels.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IA</name>
<description>Interrupt A status for DMA channel n. Bit n corresponds to
DMA channel n. 0 = the DMA channel interrupt A is not active. 1 =
the DMA channel interrupt A is active.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTB0</name>
<description>Interrupt B status for all DMA channels.</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IB</name>
<description>Interrupt B status for DMA channel n. Bit n corresponds to
DMA channel n. 0 = the DMA channel interrupt B is not active. 1 =
the DMA channel interrupt B is active.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>SETVALID0</name>
<description>Set ValidPending control bits for all DMA channels.</description>
<addressOffset>0x068</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SV</name>
<description>SETVALID control for DMA channel n. Bit n corresponds to
DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit
for DMA channel n.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>SETTRIG0</name>
<description>Set Trigger control bits for all DMA channels.</description>
<addressOffset>0x070</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>TRIG</name>
<description>Set Trigger control bit for DMA channel 0. Bit n
corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit
for DMA channel n.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>ABORT0</name>
<description>Channel Abort control for all DMA channels.</description>
<addressOffset>0x078</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>ABORTCTRL</name>
<description>Abort control for DMA channel 0. Bit n corresponds to DMA
channel n. 0 = no effect. 1 = aborts DMA operations on channel
n.</description>
<bitRange>[21:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-21</dimIndex>
<name>CFG%s</name>
<description>Configuration register for DMA channel 0.</description>
<addressOffset>0x400</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PERIPHREQEN</name>
<description>Peripheral request Enable. If a DMA channel is used to
perform a memory-to-memory move, any peripheral DMA request
associated with that channel can be disabled to prevent any
interaction between the peripheral and the DMA
controller.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Peripheral DMA requests are
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Peripheral DMA requests are
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWTRIGEN</name>
<description>Hardware Triggering Enable for this channel.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Hardware triggering is not
used.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Use hardware triggering.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Trigger Polarity. Selects the polarity of a hardware
trigger for this channel.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ACTIVE_LOW__FALLING</name>
<description>Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH__RISING</name>
<description>Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGTYPE</name>
<description>Trigger Type. Selects hardware trigger as edge triggered or
level triggered.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EDGE</name>
<description>Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL</name>
<description>Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGBURST</name>
<description>Trigger Burst. Selects whether hardware triggers cause a
single or burst transfer.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SINGLE_TRANSFER</name>
<description>Single transfer. Hardware trigger causes a single
transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BURST_TRANSFER</name>
<description>Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>BURSTPOWER</name>
<description>Burst Power is used in two ways. It always selects the
address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are
selected (see descriptions elsewhere in this register). When the
TRIGBURST field elsewhere in this register = 1, Burst Power selects
how many transfers are performed for each DMA trigger. This can be
used, for example, with peripherals that contain a FIFO that can
initiate a DMA operation when the FIFO reaches a certain level.
0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst
size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds
to the maximum supported transfer count. others: not supported. The
total transfer length as defined in the XFERCOUNT bits in the
XFERCFG register must be an even multiple of the burst
size.</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[13:12]</bitRange>
</field>
<field>
<name>SRCBURSTWRAP</name>
<description>Source Burst Wrap. When enabled, the source data address
for the DMA is wrapped, meaning that the source address range for
each burst will be the same. As an example, this could be used to
read several sequential registers from a peripheral for each DMA
burst, reading the same registers again for each
burst.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Source burst wrapping is not enabled for
this DMA channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Source burst wrapping is enabled for this
DMA channel.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTBURSTWRAP</name>
<description>Destination Burst Wrap. When enabled, the destination data
address for the DMA is wrapped, meaning that the destination address
range for each burst will be the same. As an example, this could be
used to write several sequential registers to a peripheral for each
DMA burst, writing the same registers again for each
burst.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Destination burst wrapping is not enabled
for this DMA channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Destination burst wrapping is enabled for
this DMA channel.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHPRIORITY</name>
<description>Priority of this channel when multiple DMA requests are
pending. Eight priority levels are supported. 0x0 = highest
priority. 0x7 = lowest priority.</description>
<bitRange>[18:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:19]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-21</dimIndex>
<name>CTLSTAT%s</name>
<description>Control and status register for DMA channel 0.</description>
<addressOffset>0x404</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>VALIDPENDING</name>
<description>Valid pending flag for this channel. This bit is set when a
1 is written to the corresponding bit in the related SETVALID
register when CFGVALID = 1 for the same channel.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. No effect on DMA
operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALID_PENDING</name>
<description>Valid pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TRIG</name>
<description>Trigger flag. Indicates that the trigger for this channel
is currently set. This bit is cleared at the end of an entire
transfer or upon reload when CLRTRIG = 1.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_TRIGGERED</name>
<description>Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGERED</name>
<description>Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-21</dimIndex>
<name>XFERCFG%s</name>
<description>Transfer configuration register for DMA channel 0.</description>
<addressOffset>0x408</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CFGVALID</name>
<description>Configuration Valid flag. This bit indicates whether the
current channel descriptor is valid and can potentially be acted
upon, if all other activation criteria are fulfilled.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_VALID</name>
<description>Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALID</name>
<description>Valid. The current channel descriptor is considered
valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RELOAD</name>
<description>Indicates whether the channel's control structure will be
reloaded when the current descriptor is exhausted. Reloading allows
ping-pong and linked transfers.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Reload the channels' control structure
when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWTRIG</name>
<description>Software Trigger.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_SET</name>
<description>Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRTRIG</name>
<description>Clear Trigger.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_CLEARED</name>
<description>Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEARED</name>
<description>Cleared. The trigger is cleared when this
descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETINTA</name>
<description>Set Interrupt flag A for this channel. There is no hardware
distinction between interrupt A and B. They can be used by software
to assist with more complex descriptor usage. By convention,
interrupt A may be used when only one interrupt flag is
needed.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETINTB</name>
<description>Set Interrupt flag B for this channel. There is no hardware
distinction between interrupt A and B. They can be used by software
to assist with more complex descriptor usage. By convention,
interrupt A may be used when only one interrupt flag is
needed.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>WIDTH</name>
<description>Transfer width used for this DMA channel.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>8_BIT</name>
<description>8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>16_BIT</name>
<description>16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>32_BIT</name>
<description>32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved. Reserved setting, do not
use.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[11:10]</bitRange>
</field>
<field>
<name>SRCINC</name>
<description>Determines whether the source address is incremented for
each DMA transfer.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INCREMENT</name>
<description>No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_X_WIDTH</name>
<description>1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_WIDTH</name>
<description>2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_WIDTH</name>
<description>4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTINC</name>
<description>Determines whether the destination address is incremented
for each DMA transfer.</description>
<bitRange>[15:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INCREMENT</name>
<description>No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_X_WIDTH</name>
<description>1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_WIDTH</name>
<description>2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_WIDTH</name>
<description>4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XFERCOUNT</name>
<description>Total number of transfers to be performed, minus 1 encoded.
The number of bytes transferred is: (XFERCOUNT + 1) x data width (as
defined by the WIDTH field). The DMA controller uses this bit field
during transfer to count down. Hence, it cannot be used by software
to read back the size of the transfer, for instance, in an interrupt
handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a
total of 2 transfers will be performed. ... 0x3FF = a total of 1,024
transfers will be performed.</description>
<bitRange>[25:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>CRC engine</description>
<groupName>CRC</groupName>
<baseAddress>0x1C010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODE</name>
<description>CRC mode register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_POLY</name>
<description>CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial
00= CRC-CCITT polynomial</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>BIT_RVS_WR</name>
<description>Data bit order: 1= Bit order reverse for CRC_WR_DATA (per
byte) 0= No bit order reverse for CRC_WR_DATA (per
byte)</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CMPL_WR</name>
<description>Data complement: 1= 1s complement for CRC_WR_DATA 0= No 1s
complement for CRC_WR_DATA</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BIT_RVS_SUM</name>
<description>CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No
bit order reverse for CRC_SUM</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CMPL_SUM</name>
<description>CRC sum complement: 1= 1s complement for CRC_SUM 0=No 1s
complement for CRC_SUM</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>Reserved</name>
<description>Always 0 when read</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEED</name>
<description>CRC seed register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SEED</name>
<description>A write access to this register will load CRC seed value to
CRC_SUM register with selected bit order and 1s complement
pre-processes. A write access to this register will overrule the CRC
calculation in progresses.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>SUM</name>
<description>CRC checksum register</description>
<addressOffset>0x008</addressOffset>
<access>read-only</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SUM</name>
<description>The most recent CRC sum can be read through this register
with selected bit order and 1s complement
post-processes.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>WR_DATA</name>
<description>CRC data register</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CRC_WR_DATA</name>
<description>Data written to this register will be taken to perform CRC
calculation with selected bit order and 1s complement pre-process.
Any write size 8, 16 or 32-bit are allowed and accept back-to-back
transactions.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCT0</name>
<description>State Configurable Timer/PWM 0 </description>
<groupName>SCT0</groupName>
<baseAddress>0x1C018000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SCT0</name>
<value>16</value>
</interrupt>
<registers>
<register>
<name>CONFIG</name>
<description>SCT configuration register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x7E00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UNIFY</name>
<description>SCT operation</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DUAL_COUNTER</name>
<description>Dual counter. The SCT operates as two 16-bit
counters named L and H.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UNIFIED_COUNTER</name>
<description>Unified counter. The SCT operates as a unified
32-bit counter.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKMODE</name>
<description>SCT clock mode</description>
<bitRange>[2:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYSTEM_CLOCK</name>
<description>System clock. The system clock clocks the SCT and
prescalers.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESCALED_SYSTEM_CLO</name>
<description>Prescaled system clock. The SCT clock is the system
clock, but the prescalers are enabled to count only when
sampling of the input selected by the CKSEL field finds the
selected edge. The minimum pulse width on the clock input is
1 bus clock period. This mode is the high-performance
sampled-clock mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SCT_INPUT</name>
<description>SCT input. The input selected by CKSEL clocks the
SCT and prescalers. The input is synchronized to the system
clock and possibly inverted. The minimum pulse width on the
clock input is 1 bus clock period. This mode is the
low-power sampled-clock mode.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESCALED_SCT_INPUT</name>
<description>Prescaled SCT input. The SCT and prescalers are
clocked by the input edge selected by the CKSEL field. In
this mode, most of the SCT is clocked by the (selected
polarity of the) input. The outputs are switched
synchronously to the input clock. The input clock rate must
be at least half the system clock rate and can be the same
or faster than the system clock.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKSEL</name>
<description>SCT clock select</description>
<bitRange>[6:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_RISING_EDGES</name>
<description>Input 0 rising edges.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_0_FALLING_EDGE</name>
<description>Input 0 falling edges.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_RISING_EDGES</name>
<description>Input 1 rising edges.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_FALLING_EDGE</name>
<description>Input 1 falling edges.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_RISING_EDGES</name>
<description>Input 2 rising edges.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_FALLING_EDGE</name>
<description>Input 2 falling edges.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_RISING_EDGES</name>
<description>Input 3 rising edges.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_FALLING_EDGE</name>
<description>Input 3 falling edges.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_RISING_EDGES</name>
<description>Input 4 rising edges.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_FALLING_EDGE</name>
<description>Input 4 falling edges.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_RISING_EDGES</name>
<description>Input 5 rising edges.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_FALLING_EDGE</name>
<description>Input 5 falling edges.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_RISING_EDGES</name>
<description>Input 6 rising edges.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_FALLING_EDGE</name>
<description>Input 6 falling edges.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_RISING_EDGES</name>
<description>Input 7 rising edges.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_FALLING_EDGE</name>
<description>Input 7 falling edges.</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NORELOAD_L</name>
<description>A 1 in this bit prevents the lower match registers from
being reloaded from their respective reload registers. Software can
write to set or clear this bit at any time. This bit applies to both
the higher and lower registers when the UNIFY bit is
set.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>NORELOAD_H</name>
<description>A 1 in this bit prevents the higher match registers from
being reloaded from their respective reload registers. Software can
write to set or clear this bit at any time. This bit is not used
when the UNIFY bit is set.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>INSYNC</name>
<description>Synchronization for input n (bit 9 = input 0, bit 10 =
input 1,..., bit 14 = input 5). A 1 in one of these bits subjects
the corresponding input to synchronization to the SCT clock, before
it is used to create an event. If an input is synchronous to the SCT
clock, keep its bit 0 for faster response. When the CLKMODE field is
1x, the bit in this field, corresponding to the input selected by
the CKSEL field, is not used.</description>
<bitRange>[14:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[16:15]</bitRange>
</field>
<field>
<name>AUTOLIMIT_L</name>
<description>A one in this bit causes a match on match register 0 to be
treated as a de-facto LIMIT condition without the need to define an
associated event. As with any LIMIT event, this automatic limit
causes the counter to be cleared to zero in uni-directional mode or
to change the direction of count in bi-directional mode. Software
can write to set or clear this bit at any time. This bit applies to
both the higher and lower registers when the UNIFY bit is
set.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>AUTOLIMIT_H</name>
<description>A one in this bit will cause a match on match register 0 to
be treated as a de-facto LIMIT condition without the need to define
an associated event. As with any LIMIT event, this automatic limit
causes the counter to be cleared to zero in uni-directional mode or
to change the direction of count in bi-directional mode. Software
can write to set or clear this bit at any time. This bit is not used
when the UNIFY bit is set.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:19]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>SCT control register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0x40004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOWN_L</name>
<description>This bit is 1 when the L or unified counter is counting
down. Hardware sets this bit when the counter limit is reached and
BIDIR is 1. Hardware clears this bit when the counter reaches 0 or
when the counter is counting down and a limit condition
occurs.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>STOP_L</name>
<description>When this bit is 1 and HALT is 0, the L or unified counter
does not run but I/O events related to the counter can occur. If
such an event matches the mask in the Start register, this bit is
cleared and counting resumes.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>HALT_L</name>
<description>When this bit is 1, the L or unified counter does not run
and no events can occur. A reset sets this bit. When the HALT_L bit
is one, the STOP_L bit is cleared. In order to remove the halt
condition and keep the SCT in the stop condition (not running), the
halt and stop condition can be changed with one single write to this
register. Once set, only software can clear this bit to restore
counter operation.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CLRCTR_L</name>
<description>Writing a 1 to this bit clears the L or unified counter.
This bit always reads as 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BIDIR_L</name>
<description>L or unified counter direction select</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>UNIDIRECTIONAL</name>
<description>Unidirectional. The counter counts up to its limit
condition, then is cleared to zero.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIDIRECTIONAL</name>
<description>Bidirectional. The counter counts up to its limit,
then counts down to a limit condition or to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRE_L</name>
<description>Specifies the factor by which the SCT clock is prescaled to
produce the L or unified counter clock. The counter clock is clocked
at the rate of the SCT clock divided by PRE_L+1. Clear the counter
(by writing a 1 to the CLRCTR bit) whenever changing the PRE
value.</description>
<bitRange>[12:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:13]</bitRange>
</field>
<field>
<name>DOWN_H</name>
<description>This bit is 1 when the H counter is counting down. Hardware
sets this bit when the counter limit is reached and BIDIR is 1.
Hardware clears this bit when the counter reaches 0 or when the
counter is counting down and a limit condition occurs.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>STOP_H</name>
<description>When this bit is 1 and HALT is 0, the H counter does not
run but I/O events related to the counter can occur. If such an
event matches the mask in the Start register, this bit is cleared
and counting resumes.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>HALT_H</name>
<description>When this bit is 1, the H counter does not run and no
events can occur. A reset sets this bit. When the HALT_H bit is one,
the STOP_H bit is cleared. In order to remove the halt condition and
keep the SCT in the stop condition (not running), the halt and stop
condition can be changed with one single write to this register.
Once set, this bit can only be cleared by software to restore
counter operation.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>CLRCTR_H</name>
<description>Writing a 1 to this bit clears the H counter. This bit
always reads as 0.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>BIDIR_H</name>
<description>Direction select</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>UNIDIRECTIONAL</name>
<description>Unidirectional. The H counter counts up to its
limit condition, then is cleared to zero.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIDIRECTIONAL</name>
<description>Bidirectional. The H counter counts up to its
limit, then counts down to a limit condition or to
0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRE_H</name>
<description>Specifies the factor by which the SCT clock is prescaled to
produce the H counter clock. The counter clock is clocked at the
rate of the SCT clock divided by PRELH+1. Clear the counter (by
writing a 1 to the CLRCTR bit) whenever changing the PRE
value.</description>
<bitRange>[28:21]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:29]</bitRange>
</field>
</fields>
</register>
<register>
<name>LIMIT</name>
<description>SCT limit register</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LIMMSK_L</name>
<description>If bit n is one, event n is used as a counter limit event
for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.
The number of bits = number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>LIMMSK_H</name>
<description>If bit n is one, event n is used as a counter limit event
for the H counter (event 0 = bit 16, event 1 = bit 17, etc. The
number of bits = number of events in this SCT.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>HALT</name>
<description>SCT halt condition register</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HALTMSK_L</name>
<description>If bit n is one, event n sets the HALT_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits
= number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>HALTMSK_H</name>
<description>If bit n is one, event n sets the HALT_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, etc. The number of
bits = number of events in this SCT.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>STOP</name>
<description>SCT stop condition register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STOPMSK_L</name>
<description>If bit n is one, event n sets the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits
= number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>STOPMSK_H</name>
<description>If bit n is one, event n sets the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, etc. The number of
bits = number of events in this SCT.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>START</name>
<description>SCT start condition register</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STARTMSK_L</name>
<description>If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits
= number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>STARTMSK_H</name>
<description>If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, etc. The number of
bits = number of events in this SCT.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>SCT counter register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTR_L</name>
<description>When UNIFY = 0, read or write the 16-bit L counter value.
When UNIFY = 1, read or write the lower 16 bits of the 32-bit
unified counter.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>CTR_H</name>
<description>When UNIFY = 0, read or write the 16-bit H counter value.
When UNIFY = 1, read or write the upper 16 bits of the 32-bit
unified counter.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>SCT state register</description>
<addressOffset>0x044</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATE_L</name>
<description>State variable.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:5]</bitRange>
</field>
<field>
<name>STATE_H</name>
<description>State variable.</description>
<bitRange>[20:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<name>INPUT</name>
<description>SCT input register</description>
<addressOffset>0x048</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AIN0</name>
<description>Input 0 state.Direct read.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>AIN1</name>
<description>Input 1 state. Direct read.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>AIN2</name>
<description>Input 2 state. Direct read.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>AIN3</name>
<description>Input 3 state. Direct read.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>AIN4</name>
<description>Input 4 state. Direct read.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>AIN5</name>
<description>Input 5 state. Direct read.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>SIN0</name>
<description>Input 0 state.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>SIN1</name>
<description>Input 1 state.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SIN2</name>
<description>Input 2 state.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>SIN3</name>
<description>Input 3 state.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>SIN4</name>
<description>Input 4 state.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>SIN5</name>
<description>Input 5 state.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>REGMODE</name>
<description>SCT match/capture registers mode register</description>
<addressOffset>0x04C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REGMOD_L</name>
<description>Each bit controls one pair of match/capture registers
(register 0 = bit 0, register 1 = bit 1,..., etc. 0 = registers
operate as match registers. 1 = registers operate as capture
registers.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>REGMOD_H</name>
<description>Each bit controls one pair of match/capture registers
(register 0 = bit 16, register 1 = bit 17, etc. 0 = registers
operate as match registers. 1 = registers operate as capture
registers.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>OUTPUT</name>
<description>SCT output register</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUT</name>
<description>Writing a 1 to bit n makes the corresponding output HIGH. 0
makes the corresponding output LOW (output 0 = bit 0, output 1 = bit
1, etc.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>OUTPUTDIRCTRL</name>
<description>SCT output counter direction control register</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETCLR0</name>
<description>Set/clear operation on output 0. Value 0x3 is reserved. Do
not program this value.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INDEPENDENT</name>
<description>Independent. Set and clear do not depend on any
counter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>L_REVERSED</name>
<description>L-Reversed. Set and clear are reversed when counter
L or the unified counter is counting down.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>H_REVERSED</name>
<description>H-Reversed. Set and clear are reversed when counter
H is counting down. Do not use if UNIFY = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETCLR1</name>
<description>Set/clear operation on output 1. See description of bit
0.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>SETCLR2</name>
<description>Set/clear operation on output 2. See description of bit
0.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>SETCLR3</name>
<description>Set/clear operation on output 3. See description of bit
0.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>SETCLR4</name>
<description>Set/clear operation on output 4. See description of bit
0.</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>SETCLR5</name>
<description>Set/clear operation on output 5. See description of bit
0.</description>
<bitRange>[11:10]</bitRange>
</field>
<field>
<name>SETCLR6</name>
<description>Set/clear operation on output 6. See description of bit
0.</description>
<bitRange>[13:12]</bitRange>
</field>
<field>
<name>SETCLR7</name>
<description>Set/clear operation on output 7. See description of bit
0.</description>
<bitRange>[15:14]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>RES</name>
<description>SCT conflict resolution register</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>O0RES</name>
<description>Effect of simultaneous set and clear on output
0.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR0
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR0
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O1RES</name>
<description>Effect of simultaneous set and clear on output
1.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR1
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR1
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O2RES</name>
<description>Effect of simultaneous set and clear on output
2.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR2
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR2
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O3RES</name>
<description>Effect of simultaneous set and clear on output
3.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR3
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR3
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O4RES</name>
<description>Effect of simultaneous set and clear on output
4.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR4
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR4
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O5RES</name>
<description>Effect of simultaneous set and clear on output
5.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR5
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR5
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O6RES</name>
<description>Effect of simultaneous set and clear on output
6.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR6
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR6
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O7RES</name>
<description>Effect of simultaneous set and clear on output
7.</description>
<bitRange>[15:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set output (or clear based on the SETCLR7
field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear output (or set based on the SETCLR7
field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>DMAREQ0</name>
<description>SCT DMA request 0 register</description>
<addressOffset>0x05C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEV_0</name>
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit
0, event 1 = bit 1, etc. The number of bits = number of events in
this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[29:16]</bitRange>
</field>
<field>
<name>DRL0</name>
<description>A 1 in this bit makes the SCT set DMA request 0 when it
loads the Match_L/Unified registers from the Reload_L/Unified
registers.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DRQ0</name>
<description>This read-only bit indicates the state of DMA Request
0</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>DMAREQ1</name>
<description>SCT DMA request 1 register</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEV_1</name>
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit
0, event 1 = bit 1, etc. The number of bits = number of events in
this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[29:16]</bitRange>
</field>
<field>
<name>DRL1</name>
<description>A 1 in this bit makes the SCT set DMA request 1 when it
loads the Match L/Unified registers from the Reload L/Unified
registers.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DRQ1</name>
<description>This read-only bit indicates the state of DMA Request
1.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>EVEN</name>
<description>SCT event enable register</description>
<addressOffset>0x0F0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IEN</name>
<description>The SCT requests interrupt when bit n of this register and
the event flag register are both one (event 0 = bit 0, event 1 = bit
1, etc.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>EVFLAG</name>
<description>SCT event flag register</description>
<addressOffset>0x0F4</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLAG</name>
<description>Bit n is one if event n has occurred since reset or a 1 was
last written to this bit (event 0 = bit 0, event 1 = bit 1,etc. The
number of bits = number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONEN</name>
<description>SCT conflict enable register</description>
<addressOffset>0x0F8</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NCEN</name>
<description>The SCT requests an interrupt when bit n of this register
and the SCT conflict flag register are both one (output 0 = bit 0,
output 1 = bit 1, etc.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONFLAG</name>
<description>SCT conflict flag register</description>
<addressOffset>0x0FC</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NCFLAG</name>
<description>Bit n is one if a no-change conflict event occurred on
output n since reset or a 1 was last written to this bit (output 0 =
bit 0, output 1 = bit 1, etc.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[29:10]</bitRange>
</field>
<field>
<name>BUSERRL</name>
<description>The most recent bus error from this SCT involved writing
CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>BUSERRH</name>
<description>The most recent bus error from this SCT involved writing
CTR H, STATE H, MATCH H, or the Output register when the H counter
was not halted.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>MATCH%s</name>
<description>SCT match value register of match channels 0 to 12; REGMOD0 to
REGMODE12 = 0</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCHn_L</name>
<description>When UNIFY = 0, read or write the 16-bit value to be
compared to the L counter. When UNIFY = 1, read or write the lower
16 bits of the 32-bit value to be compared to the unified
counter.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>MATCHn_H</name>
<description>When UNIFY = 0, read or write the 16-bit value to be
compared to the H counter. When UNIFY = 1, read or write the upper
16 bits of the 32-bit value to be compared to the unified
counter.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>CAP%s</name>
<description>SCT capture register of capture channel 0 to 12; REGMOD0 to
REGMODE12 = 1</description>
<alternateRegister>MATCH%s</alternateRegister>
<addressOffset>0x100</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPn_L</name>
<description>When UNIFY = 0, read the 16-bit counter value at which this
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last
captured.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>CAPn_H</name>
<description>When UNIFY = 0, read the 16-bit counter value at which this
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last
captured.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>MATCHREL%s</name>
<description>SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 =
0</description>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELOADn_L</name>
<description>When UNIFY = 0, read or write the 16-bit value to be loaded
into the MATCHn_L register. When UNIFY = 1, read or write the lower
16 bits of the 32-bit value to be loaded into the MATCHn
register.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RELOADn_H</name>
<description>When UNIFY = 0, read or write the 16-bit to be loaded into
the MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn
register.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>CAPCTRL%s</name>
<description>SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 =
1</description>
<alternateRegister>MATCHREL%s</alternateRegister>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPCONn_L</name>
<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or
the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1, etc. The number of bits = number of events in this
SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>CAPCONn_H</name>
<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0)
register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The
number of bits = number of events in this SCT.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>EV%s_STATE</name>
<description>SCT event state register 0</description>
<addressOffset>0x300</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATEMSKn</name>
<description>If bit m is one, event n happens in state m of the counter
selected by the HEVENT bit (m = state number; state 0 = bit 0, state
1= bit 1, etc. The number of bits = number of events in this
SCT.</description>
<bitRange>[12:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>13</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-12</dimIndex>
<name>EV%s_CTRL</name>
<description>SCT event control register 0</description>
<addressOffset>0x304</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCHSEL</name>
<description>Selects the Match register associated with this event (if
any). A match can occur only when the counter selected by the HEVENT
bit is running.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>HEVENT</name>
<description>Select L/H counter. Do not set this bit if UNIFY =
1.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>L_COUNTER</name>
<description>L counter. Selects the L state and the L match
register selected by MATCHSEL.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>H_COUNTER</name>
<description>H counter. Selects the H state and the H match
register selected by MATCHSEL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTSEL</name>
<description>Input/output select</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT</name>
<description>Input. Selects the input selected by
IOSEL.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTPUT</name>
<description>Output. Selects the output selected by
IOSEL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOSEL</name>
<description>Selects the input or output signal associated with this
event (if any). Do not select an input in this register, if CLKMODE
is 1x. In this case the clock input is an implicit ingredient of
every event.</description>
<bitRange>[9:6]</bitRange>
</field>
<field>
<name>IOCOND</name>
<description>Selects the I/O condition for event n. (The detection of
edges on outputs lags the conditions that switch the outputs by one
SCT clock). In order to guarantee proper edge/state detection, an
input must have a minimum pulse width of at least one SCT clock
period .</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>LOW</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE</name>
<description>Rise</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL</name>
<description>Fall</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>HIGH</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBMODE</name>
<description>Selects how the specified match and I/O condition are used
and combined.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OR</name>
<description>OR. The event occurs when either the specified
match or I/O condition occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MATCH</name>
<description>MATCH. Uses the specified match only.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IO</name>
<description>IO. Uses the specified I/O condition
only.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>AND</name>
<description>AND. The event occurs when the specified match and
I/O condition occur simultaneously.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATELD</name>
<description>This bit controls how the STATEV value modifies the state
selected by HEVENT when this event is the highest-numbered event
occurring for that state.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ADD</name>
<description>Add. STATEV value is added into STATE (the
carry-out is ignored).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOAD</name>
<description>Load. STATEV value is loaded into
STATE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATEV</name>
<description>This value is loaded into or added to the state selected by
HEVENT, depending on STATELD, when this event is the
highest-numbered event occurring for that state. If STATELD and
STATEV are both zero, there is no change to the STATE
value.</description>
<bitRange>[19:15]</bitRange>
</field>
<field>
<name>MATCHMEM</name>
<description>If this bit is one and the COMBMODE field specifies a match
component to the triggering of this event, then a match is
considered to be active whenever the counter value is GREATER THAN
OR EQUAL TO the value specified in the match register when counting
up, LESS THEN OR EQUAL TO the match value when counting down. If
this bit is zero, a match is only be active during the cycle when
the counter is equal to the match value.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>DIRECTION</name>
<description>Direction qualifier for event generation. This field only
applies when the counters are operating in BIDIR mode. If BIDIR = 0,
the SCT ignores this field. Value 0x3 is reserved.</description>
<bitRange>[22:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DIRECTION_INDEPENDEN</name>
<description>Direction independent. This event is triggered
regardless of the count direction.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTING_UP</name>
<description>Counting up. This event is triggered only during
up-counting when BIDIR = 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTING_DOWN</name>
<description>Counting down. This event is triggered only during
down-counting when BIDIR = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:23]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>OUT%s_SET</name>
<description>SCT output 0 set register</description>
<addressOffset>0x500</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SET</name>
<description>A 1 in bit m selects event m to set output n (or clear it
if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The
number of bits = number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>OUT%s_CLR</name>
<description>SCT output 0 clear register</description>
<addressOffset>0x504</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLR</name>
<description>A 1 in bit m selects event m to clear output n (or set it
if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The
number of bits = number of events in this SCT.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MAILBOX</name>
<description>Mailbox</description>
<groupName>MAILBOX</groupName>
<baseAddress>0x1C02C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MAILBOX</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>IRQ0</name>
<description>Interrupt request register for the Cortex-M0+ CPU.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTREQ</name>
<description>If any bit is set, an interrupt request is sent to the
Cortex-M0+ interrupt controller.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ0SET</name>
<description>Set bits in IRQ0</description>
<addressOffset>0x004</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INTREQSET</name>
<description>Writing 1 sets the corresponding bit in the IRQ0
register.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ0CLR</name>
<description>Clear bits in IRQ0</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INTREQCLR</name>
<description>Writing 1 clears the corresponding bit in the IRQ0
register.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ1</name>
<description>Interrupt request register for the Cortex M4 CPU.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTREQ</name>
<description>If any bit is set, an interrupt request is sent to the
Cortex-M0+ interrupt controller.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ1SET</name>
<description>Set bits in IRQ1</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INTREQSET</name>
<description>Writing 1 sets the corresponding bit in the IRQ1
register.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ1CLR</name>
<description>Clear bits in IRQ1</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INTREQCLR</name>
<description>Writing 1 clears the corresponding bit in the IRQ1
register.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MUTEX</name>
<description>Mutual exclusion register</description>
<addressOffset>0x0F8</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EX</name>
<description>Cleared when read, set when written. See usage description
above.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC0</name>
<description>12-bit ADC controller 0</description>
<groupName>ADC0</groupName>
<baseAddress>0x1C034000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC_SEQA</name>
<value>26</value>
</interrupt>
<interrupt>
<name>ADC_SEQB</name>
<value>27</value>
</interrupt>
<interrupt>
<name>ADC_THCMP</name>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>ADC Control Register. Contains the clock divide value, enable bits
for each sequence and the ADC power-down bit.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x600</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>In synchronous mode only, the system clock is divided by
this value plus one to produce the clock for the ADC converter,
which should be less than or equal to 80 MHz. Typically, software
should program the smallest value in this field that yields this
maximum clock rate or slightly less, but in certain cases (such as a
high-impedance analog source) a slower clock may be desirable. This
field is ignored in the asynchronous operating mode.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>ASYNMODE</name>
<description>Select clock mode.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYNCHRONOUS_MODE</name>
<description>Synchronous mode. The ADC clock is derived from the
system clock based on the divide value selected in the
CLKDIV field. The ADC clock will be started in a controlled
fashion in response to a trigger to eliminate any
uncertainty in the launching of an ADC conversion in
response to any synchronous (on-chip) trigger. In
Synchronous mode with the SYNCBYPASS bit (in a sequence
control register) set, sampling of the ADC input and start
of conversion will initiate 2 system clocks after the
leading edge of a (synchronous) trigger pulse.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ASYNCHRONOUS_MODE</name>
<description>Asynchronous mode. The ADC clock is based on the
output of the ADC clock divider ADCCLKSEL in the SYSCON
block.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESOL</name>
<description>The number of bits of ADC resolution. Accuracy can be
reduced to achieve higher conversion rates. A single conversion
requires the selected number of bits of resolution plus 3 ADC
clocks. This field must only be altered when the ADC is fully idle.
Changing it during any kind of ADC operation may have unpredictable
results. ADC clock frequencies for various resolutions must not
exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the
system clock rate for 10-bit resolution - 3.6x the system clock for
8-bit resolution - 3x the bus clock rate for 6-bit
resolution</description>
<bitRange>[10:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>6_BIT_RESOLUTION</name>
<description>6-bit resolution. An ADC conversion requires 9 ADC
clocks, plus any clocks specified by the TSAMP
field.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_RESOLUTION</name>
<description>8-bit resolution. An ADC conversion requires 11 ADC
clocks, plus any clocks specified by the TSAMP
field.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>10_BIT_RESOLUTION</name>
<description>10-bit resolution. An ADC conversion requires 13
ADC clocks, plus any clocks specified by the TSAMP
field.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>12_BIT_RESOLUTION</name>
<description>12-bit resolution. An ADC conversion requires 15
ADC clocks, plus any clocks specified by the TSAMP
field.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYPASSCAL</name>
<description>Bypass Calibration. This bit may be set to avoid the need
to calibrate if offset error is not a concern in the
application.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CALIBRATE</name>
<description>Calibrate. The stored calibration value will be
applied to the ADC during conversions to compensated for
offset error. A calibration cycle must be performed each
time the chip is powered-up. Re-calibration may be warranted
periodically - especially if operating conditions have
changed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_CALIBRATION</name>
<description>Bypass calibration. Calibration is not utilized.
Less time is required when enabling the ADC - particularly
following chip power-up. Attempts to launch a calibration
cycle are blocked when this bit is set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSAMP</name>
<description>Sample Time. The default sampling period (TSAMP = 000) at
the start of each conversion is 2.5 ADC clock periods. Depending on
a variety of factors, including operating conditions and the output
impedance of the analog source, longer sampling times may be
required. The TSAMP field specifies the number of additional ADC
clock cycles, from zero to seven, by which the sample period will be
extended. The total conversion time will increase by the same number
of clocks. 000 - The sample period will be the default 2.5 ADC
clocks. A complete conversion with 12-bits of accuracy will require
15 clocks. 001- The sample period will be extended by one ADC clock
to a total of 3.5 clock periods. A complete 12-bit conversion will
require 16 clocks. 010 - The sample period will be extended by two
clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will
require 17 ADC clocks. : 111 - The sample period will be extended by
two clocks to 9.5 ADC clock cycles. A complete 12-bit conversion
will require 22 ADC clocks.</description>
<bitRange>[14:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEQA_CTRL</name>
<description>ADC Conversion Sequence-A control Register: Controls triggering and
channel selection for conversion sequence-A. Also specifies interrupt mode
for sequence-A.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHANNELS</name>
<description>Selects which one or more of the ADC channels will be
sampled and converted when this sequence is launched. A 1 in any bit
of this field will cause the corresponding channel to be included in
the conversion sequence, where bit 0 corresponds to channel 0, bit 1
to channel 1 and so forth. When this conversion sequence is
triggered, either by a hardware trigger or via software command, ADC
conversions will be performed on each enabled channel, in sequence,
beginning with the lowest-ordered channel. This field can ONLY be
changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to
change this field and set bit 31 in the same write.</description>
<bitRange>[11:0]</bitRange>
</field>
<field>
<name>TRIGGER</name>
<description>Selects which of the available hardware trigger sources
will cause this conversion sequence to be initiated. Program the
trigger input number in this field. See Table 351. In order to avoid
generating a spurious trigger, it is recommended writing to this
field only when the SEQA_ENA bit (bit 31) is low. It is safe to
change this field and set bit 31 in the same write.</description>
<bitRange>[17:12]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Select the polarity of the selected input trigger for this
conversion sequence. In order to avoid generating a spurious
trigger, it is recommended writing to this field only when the
SEQA_ENA bit (bit 31) is low. It is safe to change this field and
set bit 31 in the same write.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NEGATIVE_EDGE</name>
<description>Negative edge. A negative edge launches the
conversion sequence on the selected trigger
input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE_EDGE</name>
<description>Positive edge. A positive edge launches the
conversion sequence on the selected trigger
input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCBYPASS</name>
<description>Setting this bit allows the hardware trigger input to
bypass synchronization flip-flop stages and therefore shorten the
time between the trigger input signal and the start of a conversion.
There are slightly different criteria for whether or not this bit
can be set depending on the clock operating mode: Synchronous mode
(the ASYNMODE in the CTRL register = 0): Synchronization may be
bypassed (this bit may be set) if the selected trigger source is
already synchronous with the main system clock (eg. coming from an
on-chip, system-clock-based timer). Whether this bit is set or not,
a trigger pulse must be maintained for at least one system clock
period. Asynchronous mode (the ASYNMODE in the CTRL register = 1):
Synchronization may be bypassed (this bit may be set) if it is
certain that the duration of a trigger input pulse will be at least
one cycle of the ADC clock (regardless of whether the trigger comes
from and on-chip or off-chip source). If this bit is NOT set, the
trigger pulse must at least be maintained for one system clock
period.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLE_TRIGGER_SYNCH</name>
<description>Enable trigger synchronization. The hardware
trigger bypass is not enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_TRIGGER_SYNCH</name>
<description>Bypass trigger synchronization. The hardware
trigger bypass is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>START</name>
<description>Writing a 1 to this field will launch one pass through this
conversion sequence. The behavior will be identical to a sequence
triggered by a hardware trigger. Do not write 1 to this bit if the
BURST bit is set. This bit is only set to a 1 momentarily when
written to launch a conversion sequence. It will consequently always
read back as a zero.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>BURST</name>
<description>Writing a 1 to this bit will cause this conversion sequence
to be continuously cycled through. Other sequence A triggers will be
ignored while this bit is set. Repeated conversions can be halted by
clearing this bit. The sequence currently in progress will be
completed before conversions are terminated. Note that a new
sequence could begin just before BURST is cleared.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SINGLESTEP</name>
<description>When this bit is set, a hardware trigger or a write to the
START bit will launch a single conversion on the next channel in the
sequence instead of the default response of launching an entire
sequence of conversions. Once all of the channels comprising a
sequence have been converted, a subsequent trigger will repeat the
sequence beginning with the first enabled channel. Interrupt
generation will still occur either after each individual conversion
or at the end of the entire sequence, depending on the state of the
MODE bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>LOWPRIO</name>
<description>Set priority for sequence A.</description>
<bitRange>[29:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW_PRIORITY</name>
<description>Low priority. Any B trigger which occurs while an A
conversion sequence is active will be ignored and
lost.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_PRIORITY</name>
<description>High priority. Setting this bit to a 1 will permit
any enabled B sequence trigger (including a B sequence
software start) to immediately interrupt sequence A and
launch a B sequence in its place. The conversion currently
in progress will be terminated. The A sequence that was
interrupted will automatically resume after the B sequence
completes. The channel whose conversion was terminated will
be re-sampled and the conversion sequence will resume from
that point.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Indicates whether the primary method for retrieving
conversion results for this sequence will be accomplished via
reading the global data register (SEQA_GDAT) at the end of each
conversion, or the individual channel result registers at the end of
the entire sequence. Impacts when conversion-complete interrupt/DMA
trigger for sequence-A will be generated and which overrun
conditions contribute to an overrun interrupt as described
below.</description>
<bitRange>[30:30]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>END_OF_CONVERSION</name>
<description>End of conversion. The sequence A interrupt/DMA
trigger will be set at the end of each individual ADC
conversion performed under sequence A. This flag will mirror
the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit
in the SEQA_GDAT register will contribute to generation of
an overrun interrupt/DMA trigger if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>END_OF_SEQUENCE</name>
<description>End of sequence. The sequence A interrupt/DMA
trigger will be set when the entire set of sequence-A
conversions completes. This flag will need to be explicitly
cleared by software or by the DMA-clear signal in this mode.
The OVERRUN bit in the SEQA_GDAT register will NOT
contribute to generation of an overrun interrupt/DMA trigger
since it is assumed this register may not be utilized in
this mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQA_ENA</name>
<description>Sequence Enable. In order to avoid spuriously triggering
the sequence, care should be taken to only set the SEQA_ENA bit when
the selected trigger input is in its INACTIVE state (as defined by
the TRIGPOL bit). If this condition is not met, the sequence will be
triggered immediately upon being enabled. In order to avoid
spuriously triggering the sequence, care should be taken to only set
the SEQA_ENA bit when the selected trigger input is in its INACTIVE
state (as defined by the TRIGPOL bit). If this condition is not met,
the sequence will be triggered immediately upon being
enabled.</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Sequence A is disabled. Sequence A
triggers are ignored. If this bit is cleared while sequence
A is in progress, the sequence will be halted at the end of
the current conversion. After the sequence is re-enabled, a
new trigger will be required to restart the sequence
beginning with the next enabled channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Sequence A is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQB_CTRL</name>
<description>ADC Conversion Sequence-B Control Register: Controls triggering and
channel selection for conversion sequence-B. Also specifies interrupt mode
for sequence-B.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHANNELS</name>
<description>Selects which one or more of the ADC channels will be
sampled and converted when this sequence is launched. A 1 in any bit
of this field will cause the corresponding channel to be included in
the conversion sequence, where bit 0 corresponds to channel 0, bit 1
to channel 1 and so forth. When this conversion sequence is
triggered, either by a hardware trigger or via software command, ADC
conversions will be performed on each enabled channel, in sequence,
beginning with the lowest-ordered channel. This field can ONLY be
changed while the SEQB_ENA bit (bit 31) is LOW. It is allowed to
change this field and set bit 31 in the same write.</description>
<bitRange>[11:0]</bitRange>
</field>
<field>
<name>TRIGGER</name>
<description>Selects which of the available hardware trigger sources
will cause this conversion sequence to be initiated. Program the
trigger input number in this field. See Table 351. In order to avoid
generating a spurious trigger, it is recommended writing to this
field only when the SEQB_ENA bit (bit 31) is low. It is safe to
change this field and set bit 31 in the same write.</description>
<bitRange>[17:12]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Select the polarity of the selected input trigger for this
conversion sequence. In order to avoid generating a spurious
trigger, it is recommended writing to this field only when the
SEQB_ENA bit (bit 31) is low. It is safe to change this field and
set bit 31 in the same write.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NEGATIVE_EDGE</name>
<description>Negative edge. A negative edge launches the
conversion sequence on the selected trigger
input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE_EDGE</name>
<description>Positive edge. A positive edge launches the
conversion sequence on the selected trigger
input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCBYPASS</name>
<description>Setting this bit allows the hardware trigger input to
bypass synchronization flip-flop stages and therefore shorten the
time between the trigger input signal and the start of a conversion.
There are slightly different criteria for whether or not this bit
can be set depending on the clock operating mode: Synchronous mode
(the ASYNMODE in the CTRL register = 0): Synchronization may be
bypassed (this bit may be set) if the selected trigger source is
already synchronous with the main system clock (eg. coming from an
on-chip, system-clock-based timer). Whether this bit is set or not,
a trigger pulse must be maintained for at least one system clock
period. Asynchronous mode (the ASYNMODE in the CTRL register = 1):
Synchronization may be bypassed (this bit may be set) if it is
certain that the duration of a trigger input pulse will be at least
one cycle of the ADC clock (regardless of whether the trigger comes
from and on-chip or off-chip source). If this bit is NOT set, the
trigger pulse must at least be maintained for one system clock
period.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLE_SYNCHRONIZATI</name>
<description>Enable synchronization. The hardware trigger bypass
is not enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_SYNCHRONIZATI</name>
<description>Bypass synchronization. The hardware trigger bypass
is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>START</name>
<description>Writing a 1 to this field will launch one pass through this
conversion sequence. The behavior will be identical to a sequence
triggered by a hardware trigger. Do not write 1 to this bit if the
BURST bit is set. This bit is only set to a 1 momentarily when
written to launch a conversion sequence. It will consequently always
read back as a zero.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>BURST</name>
<description>Writing a 1 to this bit will cause this conversion sequence
to be continuously cycled through. Other sequence B triggers will be
ignored while this bit is set. Repeated conversions can be halted by
clearing this bit. The sequence currently in progress will be
completed before conversions are terminated.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SINGLESTEP</name>
<description>When this bit is set, a hardware trigger or a write to the
START bit will launch a single conversion on the next channel in the
sequence instead of the default response of launching an entire
sequence of conversions. Once all of the channels comprising a
sequence have been converted, a subsequent trigger will repeat the
sequence beginning with the first enabled channel. Interrupt
generation will still occur either after each individual conversion
or at the end of the entire sequence, depending on the state of the
MODE bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Indicates whether the primary method for retrieving
conversion results for this sequence will be accomplished via
reading the global data register (SEQB_GDAT) at the end of each
conversion, or the individual channel result registers at the end of
the entire sequence. Impacts when conversion-complete interrupt/DMA
trigger for sequence-B will be generated and which overrun
conditions contribute to an overrun interrupt as described
below.</description>
<bitRange>[30:30]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>END_OF_CONVERSION</name>
<description>End of conversion. The sequence B interrupt/DMA
trigger will be set at the end of each individual ADC
conversion performed under sequence B. This flag will mirror
the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit
in the SEQB_GDAT register will contribute to generation of
an overrun interrupt/DMA trigger if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>END_OF_SEQUENCE</name>
<description>End of sequence. The sequence B interrupt/DMA
trigger will be set when the entire set of sequence-B
conversions completes. This flag will need to be explicitly
cleared by software or by the DMA-clear signal in this mode.
The OVERRUN bit in the SEQB_GDAT register will NOT
contribute to generation of an overrun interrupt/DMA trigger
since it is assumed this register may not be utilized in
this mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQB_ENA</name>
<description>Sequence Enable. In order to avoid spuriously triggering
the sequence, care should be taken to only set the SEQB_ENA bit when
the selected trigger input is in its INACTIVE state (as defined by
the TRIGPOL bit). If this condition is not met, the sequence will be
triggered immediately upon being enabled. In order to avoid
spuriously triggering the sequence, care should be taken to only set
the SEQB_ENA bit when the selected trigger input is in its INACTIVE
state (as defined by the TRIGPOL bit). If this condition is not met,
the sequence will be triggered immediately upon being
enabled.</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Sequence B is disabled. Sequence B
triggers are ignored. If this bit is cleared while sequence
B is in progress, the sequence will be halted at the end of
the current conversion. After the sequence is re-enabled, a
new trigger will be required to restart the sequence
beginning with the next enabled channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Sequence B is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQA_GDAT</name>
<description>ADC Sequence-A Global Data Register. This register contains the
result of the most recent ADC conversion performed under
sequence-A</description>
<addressOffset>0x010</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit ADC conversion result from
the most recent conversion performed under conversion sequence
associated with this register. The result is a binary fraction
representing the voltage on the currently-selected input channel as
it falls within the range of VREFP to VREFN. Zero in the field
indicates that the voltage on the input pin was less than, equal to,
or close to that on VREFN, while 0xFFF indicates that the voltage on
the input was close to, equal to, or greater than that on VREFP.
DATAVALID = 1 indicates that this result has not yet been
read.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Indicates whether the result of the last conversion
performed was above, below or within the range established by the
designated threshold comparison registers (THRn_LOW and
THRn_HIGH).</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Indicates whether the result of the last conversion
performed represented a crossing of the threshold level established
by the designated LOW threshold comparison register (THRn_LOW) and,
if so, in what direction the crossing occurred.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the RESULT bits
were converted (e.g. 0000 identifies channel 0, 0001 channel 1,
etc.).</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is set if a new conversion result is loaded into
the RESULT field before a previous result has been read - i.e. while
the DATAVALID bit is set. This bit is cleared, along with the
DATAVALID bit, whenever this register is read. This bit will
contribute to an overrun interrupt/DMA trigger if the MODE bit (in
SEQAA_CTRL) for the corresponding sequence is set to 0 (and if the
overrun interrupt is enabled).</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 at the end of each conversion when a
new result is loaded into the RESULT field. It is cleared whenever
this register is read. This bit will cause a conversion-complete
interrupt for the corresponding sequence if the MODE bit (in
SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is
enabled).</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEQB_GDAT</name>
<description>ADC Sequence-B Global Data Register. This register contains the
result of the most recent ADC conversion performed under
sequence-B</description>
<addressOffset>0x014</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit ADC conversion result from
the most recent conversion performed under conversion sequence
associated with this register. The result is a binary fraction
representing the voltage on the currently-selected input channel as
it falls within the range of VREFP to VREFN. Zero in the field
indicates that the voltage on the input pin was less than, equal to,
or close to that on VREFN, while 0xFFF indicates that the voltage on
the input was close to, equal to, or greater than that on VREFP.
DATAVALID = 1 indicates that this result has not yet been
read.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Indicates whether the result of the last conversion
performed was above, below or within the range established by the
designated threshold comparison registers (THRn_LOW and
THRn_HIGH).</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Indicates whether the result of the last conversion
performed represented a crossing of the threshold level established
by the designated LOW threshold comparison register (THRn_LOW) and,
if so, in what direction the crossing occurred.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the RESULT bits
were converted (e.g. 0000 identifies channel 0, 0001 channel 1,
etc.).</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is set if a new conversion result is loaded into
the RESULT field before a previous result has been read - i.e. while
the DATAVALID bit is set. This bit is cleared, along with the
DATAVALID bit, whenever this register is read. This bit will
contribute to an overrun interrupt/DMA trigger if the MODE bit (in
SEQB_CTRL) for the corresponding sequence is set to 0 (and if the
overrun interrupt is enabled).</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 at the end of each conversion when a
new result is loaded into the RESULT field. It is cleared whenever
this register is read. This bit will cause a conversion-complete
interrupt for the corresponding sequence if the MODE bit (in
SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is
enabled).</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-11</dimIndex>
<name>DAT%s</name>
<description>ADC Channel 0 Data Register. This register contains the result of
the most recent conversion completed on channel 0.</description>
<addressOffset>0x020</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit ADC conversion result from
the last conversion performed on this channel. This will be a binary
fraction representing the voltage on the AD0[n] pin, as it falls
within the range of VREFP to VREFN. Zero in the field indicates that
the voltage on the input pin was less than, equal to, or close to
that on VREFN, while 0xFFF indicates that the voltage on the input
was close to, equal to, or greater than that on VREFP.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Threshold Range Comparison result. 0x0 = In Range: The last
completed conversion was greater than or equal to the value
programmed into the designated LOW threshold register (THRn_LOW) but
less than or equal to the value programmed into the designated HIGH
threshold register (THRn_HIGH). 0x1 = Below Range: The last
completed conversion on was less than the value programmed into the
designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The
last completed conversion was greater than the value programmed into
the designated HIGH threshold register (THRn_HIGH). 0x3 =
Reserved.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Threshold Crossing Comparison result. 0x0 = No threshold
Crossing detected: The most recent completed conversion on this
channel had the same relationship (above or below) to the threshold
value established by the designated LOW threshold register
(THRn_LOW) as did the previous conversion on this channel. 0x1 =
Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that
a threshold crossing in the downward direction has occurred - i.e.
the previous sample on this channel was above the threshold value
established by the designated LOW threshold register (THRn_LOW) and
the current sample is below that threshold. 0x3 = Upward Threshold
Crossing Detected. Indicates that a threshold crossing in the upward
direction has occurred - i.e. the previous sample on this channel
was below the threshold value established by the designated LOW
threshold register (THRn_LOW) and the current sample is above that
threshold.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHANNEL</name>
<description>This field is hard-coded to contain the channel number that
this particular register relates to (i.e. this field will contain
0b0000 for the DAT0 register, 0b0001 for the DAT1 register,
etc)</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit will be set to a 1 if a new conversion on this
channel completes and overwrites the previous contents of the RESULT
field before it has been read - i.e. while the DONE bit is set. This
bit is cleared, along with the DONE bit, whenever this register is
read or when the data related to this channel is read from either of
the global SEQn_GDAT registers. This bit (in any of the 12
registers) will cause an overrun interrupt/DMA trigger to be
asserted if the overrun interrupt is enabled. While it is allowed to
include the same channels in both conversion sequences, doing so may
cause erratic behavior of the DONE and OVERRUN bits in the data
registers associated with any of the channels that are shared
between the two sequences. Any erratic OVERRUN behavior will also
affect overrun interrupt generation, if enabled.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 when an ADC conversion on this channel
completes. This bit is cleared whenever this register is read or
when the data related to this channel is read from either of the
global SEQn_GDAT registers. While it is allowed to include the same
channels in both conversion sequences, doing so may cause erratic
behavior of the DONE and OVERRUN bits in the data registers
associated with any of the channels that are shared between the two
sequences. Any erratic OVERRUN behavior will also affect overrun
interrupt generation, if enabled.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR0_LOW</name>
<description>ADC Low Compare Threshold Register 0: Contains the lower threshold
level for automatic threshold comparison for any channels linked to
threshold pair 0.</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>THRLOW</name>
<description>Low threshold value against which ADC results will be
compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR1_LOW</name>
<description>ADC Low Compare Threshold Register 1: Contains the lower threshold
level for automatic threshold comparison for any channels linked to
threshold pair 1.</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>THRLOW</name>
<description>Low threshold value against which ADC results will be
compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR0_HIGH</name>
<description>ADC High Compare Threshold Register 0: Contains the upper threshold
level for automatic threshold comparison for any channels linked to
threshold pair 0.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>THRHIGH</name>
<description>High threshold value against which ADC results will be
compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR1_HIGH</name>
<description>ADC High Compare Threshold Register 1: Contains the upper threshold
level for automatic threshold comparison for any channels linked to
threshold pair 1.</description>
<addressOffset>0x05C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>THRHIGH</name>
<description>High threshold value against which ADC results will be
compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CHAN_THRSEL</name>
<description>ADC Channel-Threshold Select Register. Specifies which set of
threshold compare registers are to be used for each channel</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0_THRSEL</name>
<description>Threshold select for channel 0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD0</name>
<description>Threshold 0. Results for this channel will be
compared against the threshold levels indicated in the
THR0_LOW and THR0_HIGH registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD1</name>
<description>Threshold 1. Results for this channel will be
compared against the threshold levels indicated in the
THR1_LOW and THR1_HIGH registers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1_THRSEL</name>
<description>Threshold select for channel 1. See description for channel
0.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CH2_THRSEL</name>
<description>Threshold select for channel 2. See description for channel
0.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CH3_THRSEL</name>
<description>Threshold select for channel 3. See description for channel
0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CH4_THRSEL</name>
<description>Threshold select for channel 4. See description for channel
0.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CH5_THRSEL</name>
<description>Threshold select for channel 5. See description for channel
0.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CH6_THRSEL</name>
<description>Threshold select for channel 6. See description for channel
0.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CH7_THRSEL</name>
<description>Threshold select for channel 7. See description for channel
0.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CH8_THRSEL</name>
<description>Threshold select for channel 8. See description for channel
0.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>CH9_THRSEL</name>
<description>Threshold select for channel 9. See description for channel
0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>CH10_THRSEL</name>
<description>Threshold select for channel 10. See description for
channel 0.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>CH11_THRSEL</name>
<description>Threshold select for channel 11. See description for
channel 0.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTEN</name>
<description>ADC Interrupt Enable Register. This register contains enable bits
that enable the sequence-A, sequence-B, threshold compare and data overrun
interrupts to be generated.</description>
<addressOffset>0x064</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEQA_INTEN</name>
<description>Sequence A interrupt enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence A interrupt/DMA trigger is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence A interrupt/DMA trigger is
enabled and will be asserted either upon completion of each
individual conversion performed as part of sequence A, or
upon completion of the entire A sequence of conversions,
depending on the MODE bit in the SEQA_CTRL
register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQB_INTEN</name>
<description>Sequence B interrupt enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence B interrupt/DMA trigger is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence B interrupt/DMA trigger is
enabled and will be asserted either upon completion of each
individual conversion performed as part of sequence B, or
upon completion of the entire B sequence of conversions,
depending on the MODE bit in the SEQB_CTRL
register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVR_INTEN</name>
<description>Overrun interrupt enable.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The overrun interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The overrun interrupt is enabled.
Detection of an overrun condition on any of the 12 channel
data registers will cause an overrun interrupt/DMA trigger.
In addition, if the MODE bit for a particular sequence is 0,
then an overrun in the global data register for that
sequence will also cause this interrupt/DMA trigger to be
asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN0</name>
<description>Threshold comparison interrupt enable for channel
0.</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN1</name>
<description>Channel 1 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>ADCMPINTEN2</name>
<description>Channel 2 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>ADCMPINTEN3</name>
<description>Channel 3 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>ADCMPINTEN4</name>
<description>Channel 4 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[12:11]</bitRange>
</field>
<field>
<name>ADCMPINTEN5</name>
<description>Channel 5 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[14:13]</bitRange>
</field>
<field>
<name>ADCMPINTEN6</name>
<description>Channel 6 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[16:15]</bitRange>
</field>
<field>
<name>ADCMPINTEN7</name>
<description>Channel 7 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[18:17]</bitRange>
</field>
<field>
<name>ADCMPINTEN8</name>
<description>Channel 8 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[20:19]</bitRange>
</field>
<field>
<name>ADCMPINTEN9</name>
<description>Channel 9 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[22:21]</bitRange>
</field>
<field>
<name>ADCMPINTEN10</name>
<description>Channel 10 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[24:23]</bitRange>
</field>
<field>
<name>ADCMPINTEN11</name>
<description>Channel 21 threshold comparison interrupt enable. See
description for channel 0.</description>
<bitRange>[26:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:27]</bitRange>
</field>
</fields>
</register>
<register>
<name>FLAGS</name>
<description>ADC Flags Register. Contains the four interrupt/DMA trigger flags
and the individual component overrun and threshold-compare flags. (The
overrun bits replicate information stored in the result
registers).</description>
<addressOffset>0x068</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THCMP0</name>
<description>Threshold comparison event on Channel 0. Set to 1 upon
either an out-of-range result or a threshold-crossing result if
enabled to do so in the INTEN register. This bit is cleared by
writing a 1.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>THCMP1</name>
<description>Threshold comparison event on Channel 1. See description
for channel 0.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>THCMP2</name>
<description>Threshold comparison event on Channel 2. See description
for channel 0.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>THCMP3</name>
<description>Threshold comparison event on Channel 3. See description
for channel 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>THCMP4</name>
<description>Threshold comparison event on Channel 4. See description
for channel 0.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>THCMP5</name>
<description>Threshold comparison event on Channel 5. See description
for channel 0.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>THCMP6</name>
<description>Threshold comparison event on Channel 6. See description
for channel 0.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>THCMP7</name>
<description>Threshold comparison event on Channel 7. See description
for channel 0.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>THCMP8</name>
<description>Threshold comparison event on Channel 8. See description
for channel 0.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>THCMP9</name>
<description>Threshold comparison event on Channel 9. See description
for channel 0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>THCMP10</name>
<description>Threshold comparison event on Channel 10. See description
for channel 0.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>THCMP11</name>
<description>Threshold comparison event on Channel 11. See description
for channel 0.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>OVERRUN0</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 0</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>OVERRUN1</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 1</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>OVERRUN2</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 2</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>OVERRUN3</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 3</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>OVERRUN4</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 4</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>OVERRUN5</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 5</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>OVERRUN6</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 6</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>OVERRUN7</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 7</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>OVERRUN8</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 8</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>OVERRUN9</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 9</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>OVERRUN10</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 10</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>OVERRUN11</name>
<description>Mirrors the OVERRRUN status flag from the result register
for ADC channel 11</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>SEQA_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQA_GDAT
register</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SEQB_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQB_GDAT
register</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[27:26]</bitRange>
</field>
<field>
<name>SEQA_INT</name>
<description>Sequence A interrupt/DMA trigger. If the MODE bit in the
SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in
the sequence A global data register (SEQA_GDAT), which is set at the
end of every ADC conversion performed as part of sequence A. It will
be cleared automatically when the SEQA_GDAT register is read. If the
MODE bit in the SEQA_CTRL register is 1, this flag will be set upon
completion of an entire A sequence. In this case it must be cleared
by writing a 1 to this SEQA_INT bit. This interrupt must be enabled
in the INTEN register.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>SEQB_INT</name>
<description>Sequence A interrupt/DMA trigger. If the MODE bit in the
SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in
the sequence A global data register (SEQB_GDAT), which is set at the
end of every ADC conversion performed as part of sequence B. It will
be cleared automatically when the SEQB_GDAT register is read. If the
MODE bit in the SEQB_CTRL register is 1, this flag will be set upon
completion of an entire B sequence. In this case it must be cleared
by writing a 1 to this SEQB_INT bit. This interrupt must be enabled
in the INTEN register.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>THCMP_INT</name>
<description>Threshold Comparison Interrupt. This bit will be set if any
of the THCMP flags in the lower bits of this register are set to 1
(due to an enabled out-of-range or threshold-crossing event on any
channel). Each type of threshold comparison interrupt on each
channel must be individually enabled in the INTEN register to cause
this interrupt. This bit will be cleared when all of the individual
threshold flags are cleared via writing 1s to those
bits.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>OVR_INT</name>
<description>Overrun Interrupt flag. Any overrun bit in any of the
individual channel data registers will cause this interrupt. In
addition, if the MODE bit in either of the SEQn_CTRL registers is 0
then the OVERRUN bit in the corresponding SEQn_GDAT register will
also cause this interrupt. This interrupt must be enabled in the
INTEN register. This bit will be cleared when all of the individual
overrun bits have been cleared via reading the corresponding data
registers.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTUP</name>
<description>ADC Startup Register (typically only used by the ADC
API).</description>
<addressOffset>0x6C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADC_ENA</name>
<description>ADC Enable bit. This bit can only be set to a 1 by
software. It is cleared automatically whenever the ADC is powered
down. This bit must not be set until at least 10 microseconds after
the ADC is powered up (typically by altering a system-level ADC
power control bit).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ADC_INT</name>
<description>tbd</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<description>ADC Calibration Register.</description>
<addressOffset>0x70</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CALIB</name>
<description>Calibration request. Setting this bit will launch an ADC
calibration cycle. This bit can only be set to a 1 by software. It
is cleared automatically when the calibration cycle
completes.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CALREQD</name>
<description>Calibration required. This read-only bit indicates if
calibration is required when enabling the ADC. CALREQD will be 1 if
no calibration has been run since the chip was powered-up and if the
BYPASSCAL bit in the ADCTRL register is low. The ADC API will test
this bit to determine whether to initiate a calibration cycle or
whether to set the ADC_INIT bit (in the ADSTARTUP register) to
launch the ADC initialization process which includes a dummy
conversion cycle. Note: A dummy conversion cycle requires
approximately 6 ADC clocks as opposed to 81 clocks required for
calibration.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CALVALUE</name>
<description>Calibration Value. This read-only field displays the
calibration value established during last calibration cycle. This
value is not typically of any use to the user.</description>
<bitRange>[8:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VFIFO</name>
<description>System FIFO for Serial Peripherals </description>
<groupName>VFIFO</groupName>
<baseAddress>0x1C038000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x4000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FIFOCTLUSART</name>
<description>USART FIFO global control register. These registers are byte,
halfword, and word addressable.The upper 16 bits of these registers provide
information about the System FIFO configuration, and are specific to each
device type.</description>
<addressOffset>0x0100</addressOffset>
<access>read-write</access>
<resetValue>0x707</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXPAUSE</name>
<description>Pause all USARTs receive FIFO operations. This can be used
to prepare the System FIFO to reconfigure FIFO allocations among the
USART receivers.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RXPAUSED</name>
<description>All USART receive FIFOs are paused.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>All USART receive FIFOs are empty.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>TXPAUSE</name>
<description>Pause all USARTs transmit FIFO operations. This can be used
to prepare the System FIFO to reconfigure FIFO allocations among the
USART transmitters.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXPAUSED</name>
<description>All USART transmit FIFOs are paused.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>All USART transmit FIFOs are empty.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:11]</bitRange>
</field>
<field>
<name>RXFIFOTOTAL</name>
<description>Reports the receive FIFO space available for USARTs on this
FIFO. The reset value is device specific.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXFIFOTOTAL</name>
<description>Reports the transmit FIFO space available for USARTs on
this FIFO. The reset value is device specific.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>FIFOUPDATEUSART</name>
<description>USART FIFO global update register</description>
<addressOffset>0x0104</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>USART0RXUPDATESIZE</name>
<description>Writing 1 updates USART0 Rx FIFO size to match the USART0
RXSIZE. Must be done for all USARTs when any USART RXSIZE is
changed.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>USART1RXUPDATESIZE</name>
<description>Writing 1 updates USART1 Rx FIFO size to match the USART1
RXSIZE. Must be done for all USARTs when any USART RXSIZE is
changed.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>USART2RXUPDATESIZE</name>
<description>Writing 1 updates USART2 Rx FIFO size to match the USART2
RXSIZE. Must be done for all USARTs when any USART RXSIZE is
changed.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>USART3RXUPDATESIZE</name>
<description>Writing 1 updates USART3 Rx FIFO size to match the USART3
RXSIZE. Must be done for all USARTs when any USART RXSIZE is
changed.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>USART0TXUPDATESIZE</name>
<description>Writing 1 updates USART0 Tx FIFO size to match the USART0
TXSIZE. Must be done for all USARTs when any USART TXSIZE is
changed.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>USART1TXUPDATESIZE</name>
<description>Writing 1 updates USART1 Tx FIFO size to match the USART1
TXSIZE. Must be done for all USARTs when any USART TXSIZE is
changed.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>USART2TXUPDATESIZE</name>
<description>Writing 1 updates USART2 Tx FIFO size to match the USART2
TXSIZE. Must be done for all USARTs when any USART TXSIZE is
changed.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>USART3TXUPDATESIZE</name>
<description>Writing 1 updates USART3 Tx FIFO size to match the USART3
TXSIZE. Must be done for all USARTs when any USART TXSIZE is
changed.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:20]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>FIFOCFGUSART%s</name>
<description>FIFO configuration register for USART0</description>
<addressOffset>0x0110</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXSIZE</name>
<description>Configures the USART receive FIFO size. A zero values
provides no System FIFO service for the related USART
receiver.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>TXSIZE</name>
<description>Configures the USART transmit FIFO size. A zero values
provides no System FIFO service for the related USART
transmitter.</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>FIFOCTLSPI</name>
<description>SPI FIFO global control register. These registers are byte,
halfword, and word addressable. The upper 16 bits of these registers provide
information about the System FIFO configuration, and are specific to each
device type.</description>
<addressOffset>0x0200</addressOffset>
<access>read-write</access>
<resetValue>0x707</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXPAUSE</name>
<description>Pause all SPIs receive FIFO operations. This can be used to
prepare the System FIFO to reconfigure FIFO allocations among the
SPI receivers.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RXPAUSED</name>
<description>All SPI receive FIFOs are paused.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>All SPI receive FIFOs are empty.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>TXPAUSE</name>
<description>Pause all SPIs transmit FIFO operations. This can be used
to prepare the System FIFO to reconfigure FIFO allocations among the
SPI transmitters.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXPAUSED</name>
<description>All SPI transmit FIFOs are paused.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>All SPI transmit FIFOs are empty.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:11]</bitRange>
</field>
<field>
<name>RXFIFOTOTAL</name>
<description>Reports the receive FIFO space available for SPIs on the
System FIFO. The reset value is device specific.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXFIFOTOTAL</name>
<description>Reports the transmit FIFO space available for SPIs on the
System FIFO. The reset value is device specific.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>FIFOUPDATESPI</name>
<description>SPI FIFO global update register</description>
<addressOffset>0x0204</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SPI0RXUPDATESIZE</name>
<description>Writing 1 updates SPI0 Rx FIFO size to match the SPI0
RXSIZE. Must be done for all SPIs when any SPI RXSIZE is
changed.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SPI1RXUPDATESIZE</name>
<description>Writing 1 updates SPI1 Rx FIFO size to match the SPI1
RXSIZE. Must be done for all SPIs when any SPI RXSIZE is
changed.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:3]</bitRange>
</field>
<field>
<name>SPI0TXUPDATESIZE</name>
<description>Writing 1 updates SPI0 Tx FIFO size to match the SPI0
TXSIZE. Must be done for all SPIs when any SPI TXSIZE is
changed.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>SPI1TXUPDATESIZE</name>
<description>Writing 1 updates SPI1 Tx FIFO size to match the SPI1
TXSIZE. Must be done for all SPIs when any SPI TXSIZE is
changed.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>FIFOCFGSPI%s</name>
<description>FIFO configuration register for SPI0</description>
<addressOffset>0x0210</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXSIZE</name>
<description>Configures the SPI receive FIFO size. A zero values
provides no System FIFO service for the related SPI
receiver.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>TXSIZE</name>
<description>Configures the SPI transmit FIFO size. A zero values
provides no System FIFO service for the related SPI
transmitter.</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CFGUSART%s</name>
<description>USART0 configuration</description>
<addressOffset>0x1000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>TIMEOUTCONTONWRITE</name>
<description>Timeout Continue On Write. When 0, the timeout for the
related peripheral is reset every time data is transferred from the
peripheral into the receive FIFO. When 1, the timeout for the
related peripheral is not reset every time data is transferred into
the receive FIFO. This allows the timeout to be applied to
accumulated data, perhaps related to the FIFO
threshold.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>TIMEOUTCONTONEMPTY</name>
<description>Timeout Continue On Empty. When 0, the timeout for the
related peripheral is reset when the receive FIFO becomes empty.
When 1, the timeout for the related peripheral is not reset when the
receive FIFO becomes empty. This allows the timeout to be used to
flag idle peripherals, and could potentially be used to indicate the
end of a transmission of indeterminate length.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>TIMEOUTBASE</name>
<description>Specifies the least significant timer bit to compare to
TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through
15.</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>TIMEOUTVALUE</name>
<description>Specifies the maximum time value for timeout at the timer
position identified by TimeoutBase. Minimum time TimeoutValue - 1.
is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1
when timeout is enabled.</description>
<bitRange>[15:12]</bitRange>
</field>
<field>
<name>RXTHRESHOLD</name>
<description>Receive FIFO Threshold. The System FIFO indicates that the
threshold has been reached when the number of entries in the receive
FIFO is greater than this value. For example, when RxThreshold = 0,
the threshold is exceeded when there is at least one entry in the
receive FIFO. An interrupt can be generated when the RxThreshold has
been reached (see Section 24.5.10), but has no effect on DMA
requests, which are generated whenever the receiver FIFO is not
empty.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXTHRESHOLD</name>
<description>Transmit FIFO Threshold. The System FIFO indicates that the
threshold has been reached when the number of free entries in the
transmit FIFO is less than or equal to this value. For example, when
TxThreshold = 0, the threshold is exceeded when there is at least
one free entry in the transmit FIFO. An interrupt can be generated
when the TxThreshold has been reached (see Section 24.5.10), but has
no effect on DMA requests, which are generated whenever the transmit
FIFO has any free entries.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>STATUSART%s</name>
<description>USART0 status</description>
<addressOffset>0x1004</addressOffset>
<access>read-write</access>
<resetValue>0x300</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTH</name>
<description>Receive FIFO Threshold. When 1, the receive FIFO threshold
has been reached. This is a read-only bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTH</name>
<description>Transmit FIFO Threshold. When 1, the transmit FIFO
threshold has been reached. This is a read-only bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUT</name>
<description>Receive FIFO Timeout. When 1, the receive FIFO has timed
out, based on the timeout configuration in the CFGUSART register.
The timeout condition can be cleared by writing a 1 to this bit, by
enabling or disabling the timeout interrupt, or by writing a 1 to
the timeout interrupt enable.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>BUSERR</name>
<description>Bus Error. When 1, a bus error has occurred while
processing data for USARTn. The bus error flag can be cleared by
writing a 1 to this bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>Receive FIFO Empty. When 1, the receive FIFO is currently
empty. This is a read-only bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit FIFO Empty. When 1, the transmit FIFO is currently
empty. This is a read-only bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>RXCOUNT</name>
<description>Receive FIFO Count. Indicates how many entries may be read
from the receive FIFO. 0 = FIFO empty. This is a read-only
field.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXCOUNT</name>
<description>Transmit FIFO Count. Indicates how many entries may be
written to the transmit FIFO. 0 = FIFO full. This is a read-only
field that is valid only when the TxFIFO is fully configured and
enabled.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>INTSTATUSART%s</name>
<description>USART0 interrupt status</description>
<addressOffset>0x1008</addressOffset>
<access>read-only</access>
<resetValue>0x300</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTH</name>
<description>Receive FIFO Threshold. When 1, the receive FIFO threshold
has been reached, and the related interrupt is
enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTH</name>
<description>Transmit FIFO Threshold. When 1, the transmit FIFO
threshold has been reached, and the related interrupt is
enabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUT</name>
<description>Receive Timeout. When 1, the receive FIFO has timed out,
based on the timeout configuration in the CFGUSART register, and the
related interrupt is enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>BUSERR</name>
<description>Bus Error. This is simply a copy of the same bit in the
STATUSART register. The bus error interrupt is always
enabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>Receive FIFO Empty. This is simply a copy of the same bit
in the STATUSART register.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit FIFO Empty. This is simply a copy of the same bit
in the STATUSART register.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>RXCOUNT</name>
<description>Receive FIFO Count. This is simply a copy of the same field
in the STATUSART register, included here so an ISR can read all
needed status information in one read.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXCOUNT</name>
<description>Transmit FIFO Available. This is simply a copy of the same
field in the STATUSART register, included here so an ISR can read
all needed status information in one read.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CTLSETUSART%s</name>
<description>USART0 control read and set register. A complete value may be read
from this register. Writing a 1 to any implemented bit position causes that
bit to be set.</description>
<addressOffset>0x100C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTHINTEN</name>
<description>Receive FIFO Threshold Interrupt Enable.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTHINTEN</name>
<description>Transmit FIFO Threshold Interrupt Enable.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUTINTEN</name>
<description>Receive FIFO Timeout Interrupt Enable. When enabled, this
also enables the timeout for this USART. Writing a 1 to this bit
resets the USART timeout logic.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO flush. Writing a 1 to this bit forces the
receive FIFO to be empty.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO flush. Writing a 1 to this bit forces the
transmit FIFO to be empty.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CTLCLRUSART%s</name>
<description>USART0 control clear register. Writing a 1 to any implemented bit
position causes the corresponding bit in the related CTLSET register to be
cleared.</description>
<addressOffset>0x1010</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXTHINTCLR</name>
<description>Receive FIFO Threshold Interrupt clear.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTHINTCLR</name>
<description>Transmit FIFO Threshold Interrupt clear.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUTINTCLR</name>
<description>Receive FIFO Time-out Interrupt clear.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>RXFLUSHCLR</name>
<description>Receive FIFO flush clear.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXFLUSHCLR</name>
<description>Transmit FIFO flush clear.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>RXDATUSART%s</name>
<description>USART0 received data</description>
<addressOffset>0x1014</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>The UART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the UART
configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>RXDATSTATUSART%s</name>
<description>USART0 received data with status</description>
<addressOffset>0x1018</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>The UART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the UART
configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[12:9]</bitRange>
</field>
<field>
<name>FRAMERR</name>
<description>Framing Error status flag. This bit is valid when there is
a character to be read in the RXDAT register and reflects the status
of that character. This bit will set when the character in RXDAT was
received with a missing stop bit at the expected location. This
could be an indication of a baud rate or configuration mismatch with
the transmitting source.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERR</name>
<description>Parity Error status flag. This bit is valid when there is a
character to be read in the RXDAT register and reflects the status
of that character. This bit will be set when a parity error is
detected in a received character.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISE</name>
<description>Received Noise flag.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>TXDATUSART%s</name>
<description>USART0 transmit data</description>
<addressOffset>0x101C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Writing to the UART Transmit Data Register causes the data
to be transmitted as soon as the transmit shift register is
available and the condition for transmitting data is met: TXDIS bit
= 0.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Only zero should be written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>CFGSPI%s</name>
<description>SPI0 configuration</description>
<addressOffset>0x2000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>TIMEOUTCONTONWRITE</name>
<description>Timeout Continue On Write. When 0, the timeout for the
related peripheral is reset every time data is transferred from the
peripheral into the receive FIFO. When 1, the timeout for the
related peripheral is not reset every time data is transferred into
the receive FIFO. This allows the timeout to be applied to
accumulated data, perhaps related to the FIFO
threshold.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>TIMEOUTCONTONEMPTY</name>
<description>Timeout Continue On Empty. When 0, the timeout for the
related peripheral is reset when the receive FIFO becomes empty.
When 1, the timeout for the related peripheral is not reset when the
receive FIFO becomes empty. This allows the timeout to be used to
flag idle peripherals, and could potentially be used to indicate the
end of a transmission of indeterminate length.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>TIMEOUTBASE</name>
<description>Specifies the least significant timer bit to compare to
TimeoutValue. Value can be 0 through 15.</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>TIMEOUTVALUE</name>
<description>Specifies the maximum time value for timeout at the timer
position identified by TimeoutBase. Minimum time TimeoutValue - 1.
TimeoutValue should not be 0 or 1 when timeout is
enabled.</description>
<bitRange>[15:12]</bitRange>
</field>
<field>
<name>RXTHRESHOLD</name>
<description>Receive FIFO Threshold. The System FIFO indicates that the
threshold has been reached when the number of entries in the receive
FIFO is greater than this value. For example, when RxThreshold = 0,
the threshold is exceeded when there is at least one entry in the
receive FIFO. An interrupt can be generated when the RxThreshold has
been reached, but has no effect on DMA requests, which are generated
whenever the receiver FIFO is not empty.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXTHRESHOLD</name>
<description>Transmit FIFO Threshold. The System FIFO indicates that the
threshold has been reached when the number of free entries in the
transmit FIFO is less than or equal to this value. For example, when
TxThreshold = 0, the threshold is exceeded when there is at least
one free entry in the transmit FIFO. An interrupt can be generated
when the TxThreshold has been reached, but has no effect on DMA
requests, which are generated whenever the transmit FIFO has any
free entries.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>STATSPI%s</name>
<description>SPI0 status</description>
<addressOffset>0x2004</addressOffset>
<access>read-write</access>
<resetValue>0x300</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTH</name>
<description>Receive FIFO Threshold. When 1, the receive FIFO threshold
has been reached. This is a read-only bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTH</name>
<description>Transmit FIFO Threshold. When 1, the transmit FIFO
threshold has been reached. This is a read-only bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUT</name>
<description>Receive FIFO Timeout. When 1, the receive FIFO has timed
out, based on the timeout configuration in the CFGSPI register. The
timeout condition can be cleared by writing a 1 to this bit, by
enabling or disabling the timeout interrupt, or by writing a 1 to
the timeout interrupt enable.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>BUSERR</name>
<description>Bus Error. When 1, a bus error has occurred while
processing data for SPI. The bus error flag can be cleared by
writing a 1 to this bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>Receive FIFO Empty. When 1, the receive FIFO is currently
empty. This is a read-only bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit FIFO Empty. When 1, the transmit FIFO is currently
empty. This is a read-only bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>RXCOUNT</name>
<description>Receive FIFO Count. Indicates how many entries may be read
from the receive FIFO. 0 = FIFO empty. This is a read-only
field.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXCOUNT</name>
<description>Transmit FIFO Count. Indicates how many entries may be
written to the transmit FIFO. 0 = FIFO full. This is a read-only
field that is valid only when the TxFIFO is fully configured and
enabled.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>INTSTATSPI%s</name>
<description>SPI0 interrupt status</description>
<addressOffset>0x2008</addressOffset>
<access>read-only</access>
<resetValue>0x300</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTH</name>
<description>Receive FIFO Threshold. When 1, the receive FIFO threshold
has been reached, and the related interrupt is
enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTH</name>
<description>Transmit FIFO Threshold. When 1, the transmit FIFO
threshold has been reached, and the related interrupt is
enabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUT</name>
<description>Receive Timeout. When 1, the receive FIFO has timed out,
based on the timeout configuration in the CFGSPI register, and the
related interrupt is enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>BUSERR</name>
<description>Bus Error. This is simply a copy of the same bit in the
STATSPI register. The bus error interrupt is always
enabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RXEMPTY</name>
<description>Receive FIFO Empty. This is simply a copy of the same bit
in the STATSPI register.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit FIFO Empty. This is simply a copy of the same bit
in the STATSPI register.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>RXCOUNT</name>
<description>Receive FIFO Count. This is simply a copy of the same field
in the STATSPI register, included here so an ISR can read all needed
status information in one read.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TXCOUNT</name>
<description>Transmit FIFO Available. This is simply a copy of the same
field in the STATSPI register, included here so an ISR can read all
needed status information in one read.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>CTLSETSPI%s</name>
<description>SPI0 control read and set register. A complete value may be read
from this register. Writing a 1 to any implemented bit position causes that
bit to be set.</description>
<addressOffset>0x200C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXTHINTEN</name>
<description>Receive FIFO Threshold Interrupt Enable.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTHINTEN</name>
<description>Transmit FIFO Threshold Interrupt Enable.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUTINTEN</name>
<description>Receive FIFO Timeout Interrupt Enable. When enabled, this
also enables the timeout for this SPI. Writing a 1 to this bit
resets the SPI timeout logic.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO flush. Writing a 1 to this bit forces the
receive FIFO to be empty.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO flush. Writing a 1 to this bit forces the
transmit FIFO to be empty.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>CTLCLRSPI%s</name>
<description>SPI0 control clear register. Writing a 1 to any implemented bit
position causes the corresponding bit in the related CTLSET register to be
cleared.</description>
<addressOffset>0x2010</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the CTLSETSPI register, if they are implemented. Bits
that do not correspond to defined bits in CTLSETSPI are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
<field>
<name>RXTHINTCLR</name>
<description>Receive FIFO Threshold Interrupt clear.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXTHINTCLR</name>
<description>Transmit FIFO Threshold Interrupt clear.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>RXTIMEOUTINTCLR</name>
<description>Receive FIFO Timeout Interrupt clear.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>RXFLUSHCLR</name>
<description>Receive FIFO flush clear. do the clear bits 8 and 9 do
anything?</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>TXFLUSHCLR</name>
<description>Transmit FIFO flush clear.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>RXDATSPI%s</name>
<description>SPI0 received data. These registers are half word
addressable.</description>
<addressOffset>0x2014</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>Receiver Data. This contains the next piece of received
data. The number of bits that are used depends on the LEN setting in
TXCTL / TXDATCTL.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RXSSEL0_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL0 pin to be saved along with received data. The value will
reflect the SSEL0 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RXSSEL1_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL1 pin to be saved along with received data. The value will
reflect the SSEL1 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RXSSEL2_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL2 pin to be saved along with received data. The value will
reflect the SSEL2 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>RXSSEL3_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL3 pin to be saved along with received data. The value will
reflect the SSEL3 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>SOT</name>
<description>Start of Transfer flag. This flag will be 1 if this is the
first data after the SSELs went from deasserted to asserted (i.e.,
any previous transfer has ended). This information can be used to
identify the first piece of data in cases where the transfer length
is greater than 16 bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x100</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>TXDATSPI%s</name>
<description>SPI0 transmit data. These registers are half word
addressable.</description>
<addressOffset>0x2018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Transmit Data. This field provides from 1 to 16 bits of
data to be transmitted.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>TXSSEL0_N</name>
<description>Transmit Slave Select. This field asserts SSEL0 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL0 pin is configured by bits in the CFG
register.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASSERTED</name>
<description>Asserted. SSEL0 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ASSERTED</name>
<description>Not asserted. SSEL0 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL1_N</name>
<description>Transmit Slave Select. This field asserts SSEL1 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL1 pin is configured by bits in the CFG
register.</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASSERTED</name>
<description>Asserted. SSEL1 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ASSERTED</name>
<description>Not asserted. SSEL1 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL2_N</name>
<description>Transmit Slave Select. This field asserts SSEL2 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL2 pin is configured by bits in the CFG
register.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASSERTED</name>
<description>Asserted. SSEL2 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ASSERTED</name>
<description>Not asserted. SSEL2 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL3_N</name>
<description>Transmit Slave Select. This field asserts SSEL3 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL3 pin is configured by bits in the CFG
register.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASSERTED</name>
<description>Asserted. SSEL3 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ASSERTED</name>
<description>Not asserted. SSEL3 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOT</name>
<description>End of Transfer. The asserted SSEL will be deasserted at
the end of a transfer, and remain so for at least the time specified
by the Transfer_delay value in the DLY register.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_DEASSERTED</name>
<description>Not deasserted. SSEL not deasserted. This piece of
data is not treated as the end of a transfer. SSEL will not
be deasserted at the end of this data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEASSERTED</name>
<description>Deasserted. SSEL deasserted. This piece of data is
treated as the end of a transfer. SSEL will be deasserted at
the end of this piece of data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOF</name>
<description>End of Frame. Between frames, a delay may be inserted, as
defined by the FRAME_DELAY value in the DLY register. The end of a
frame may not be particularly meaningful if the FRAME_DELAY value =
0. This control can be used as part of the support for frame lengths
greater than 16 bits.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DATA_NOT_EOF</name>
<description>Data not EOF. This piece of data transmitted is not
treated as the end of a frame.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_EOF</name>
<description>Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXIGNORE</name>
<description>Receive Ignore. This allows data to be transmitted using
the SPI without the need to read unneeded data from the receiver to
simplify the transmit process and can be used with the
DMA.</description>
<bitRange>[22:22]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>READ_RECEIVED_DATA</name>
<description>Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IGNORE_RECEIVED_DATA</name>
<description>Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>LEN</name>
<description>Data Length. Specifies the data length from 1 to 16 bits.
Note that transfer lengths greater than 16 bits are supported by
implementing multiple sequential data transmits. 0x0 = Data transfer
is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 =
Data transfer is 3 bits in length. ... 0xF = Data transfer is 16
bits in length.</description>
<bitRange>[27:24]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCON</name>
<description>System configuration</description>
<groupName>SYSCON</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSMEMREMAP</name>
<description>System memory remap</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAP</name>
<description>System memory remap. Value 0x3 is reserved.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BOOT_LOADER_MODE</name>
<description>Boot Loader Mode. Interrupt vectors are re-mapped
to Boot ROM.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_RAM_MODE</name>
<description>User RAM Mode. Interrupt vectors are re-mapped to
Static RAM.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_FLASH_MODE</name>
<description>User Flash Mode. Interrupt vectors are not
re-mapped and reside in Flash.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBMATPRIO</name>
<description>AHB multilayer matrix priority control</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_ICODE</name>
<description>I-Code bus priority. Should be lower than PRI_DCODE for
proper operation.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>PRI_DCODE</name>
<description>D-Code bus priority.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>PRI_SYS</name>
<description>System bus priority.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>PRI_DMA</name>
<description>DMA controller priority.</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[13:10]</bitRange>
</field>
<field>
<name>PRI_FIFO</name>
<description>System FIFO bus priority</description>
<bitRange>[15:14]</bitRange>
</field>
<field>
<name>PRI_M0</name>
<description>Cortex-M0+ bus priority.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSTCKCAL</name>
<description>System tick counter calibration</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAL</name>
<description>System tick timer calibration value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>SKEW</name>
<description>Initial value for the Systick timer.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>NOREF</name>
<description>Initial value for the Systick timer.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>NMISRC</name>
<description>NMI Source Select</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRQM4</name>
<description>The IRQ number of the interrupt that acts as the
Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by
NMIENM4.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>IRQM0</name>
<description>The IRQ number of the interrupt that acts as the
Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by
NMIENM0.</description>
<bitRange>[13:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[29:14]</bitRange>
</field>
<field>
<name>NMIENM0</name>
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt
(NMI) source selected by IRQM0.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>NMIENM4</name>
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt
(NMI) source selected by IRQM4.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCTRL</name>
<description>Asynchronous APB Control</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the asynchronous APB bridge and
subsystem.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Asynchronous APB bridge is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Asynchronous APB bridge is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSRSTSTAT</name>
<description>System reset status register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POR</name>
<description>POR reset status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_POR_DETECTED</name>
<description>No POR detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POR_DETECTED</name>
<description>POR detected. Writing a one clears this
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTRST</name>
<description>Status of the external RESET pin. External reset
status.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_RESET_EVENT_DETEC</name>
<description>No reset event detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_DETECTED</name>
<description>Reset detected. Writing a one clears this
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT</name>
<description>Status of the Watchdog reset</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_WDT_RESET_DETECTE</name>
<description>No WDT reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WDT_RESET_DETECTED</name>
<description>WDT reset detected. Writing a one clears this
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD</name>
<description>Status of the Brown-out detect reset</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_BOD_RESET_DETECTE</name>
<description>No BOD reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BOD_RESET_DETECTED</name>
<description>BOD reset detected. Writing a one clears this
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSRST</name>
<description>Status of the software system reset</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_SYSTEM_RESET_DETE</name>
<description>No System reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_RESET_DETECTE</name>
<description>System reset detected. Writing a one clears this
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL0</name>
<description>Peripheral reset control 0</description>
<addressOffset>0x044</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:0]</bitRange>
</field>
<field>
<name>FLASH_RST</name>
<description>Flash controller reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>FMC_RST</name>
<description>Flash accelerator reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>MUX_RST</name>
<description>Input mux reset control. 0 = Clear reset to this function.
1 = Assert reset to this function.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>IOCON_RST</name>
<description>IOCON reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>GPIO0_RST</name>
<description>GPIO0 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>GPIO1_RST</name>
<description>GPIO1 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>PINT_RST</name>
<description>Pin interrupt (PINT) reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>GINT_RST</name>
<description>Grouped interrupt (GINT) reset control. 0 = Clear reset to
this function. 1 = Assert reset to this function.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>DMA_RST</name>
<description>DMA reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>CRC_RST</name>
<description>CRC generator reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>WWDT_RST</name>
<description>Watchdog timer reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>RTC_RST</name>
<description>RTC reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:24]</bitRange>
</field>
<field>
<name>MAILBOX_RST</name>
<description>Mailbox reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>ADC0_RST</name>
<description>ADC0 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL1</name>
<description>Peripheral reset control 1</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MRT_RST</name>
<description>Multi-rate timer (MRT) reset control. 0 = Clear reset to
this function. 1 = Assert reset to this function.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RIT_RST</name>
<description>Repetitive interrupt timer (RIT) reset control. 0 = Clear
reset to this function. 1 = Assert reset to this
function.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SCT0_RST</name>
<description>State configurable timer 0 (SCT0) reset control. 0 = Clear
reset to this function. 1 = Assert reset to this
function.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[8:3]</bitRange>
</field>
<field>
<name>FIFO_RST</name>
<description>System FIFO reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>UTICK_RST</name>
<description>Micro-tick Timer reset control. 0 = Clear reset to this
function. 1 = Assert reset to this function.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[21:11]</bitRange>
</field>
<field>
<name>TIMER2_RST</name>
<description>Timer 2 reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:23]</bitRange>
</field>
<field>
<name>TIMER3_RST</name>
<description>Timer 3 reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>TIMER4_RST</name>
<description>Timer 4 reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRLSET0</name>
<description>Set bits in PRESETCTRL0</description>
<addressOffset>0x04C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RST_SET0</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the PRESETCTRL0 register, if they are implemented. Bits that
do not correspond to defined bits in PRESETCTRL0 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRLSET1</name>
<description>Set bits in PRESETCTRL1</description>
<addressOffset>0x050</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RST_SET1</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the PRESETCTRL1 register, if they are implemented. Bits that
do not correspond to defined bits in PRESETCTRL1 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRLCLR0</name>
<description>Clear bits in PRESETCTRL0</description>
<addressOffset>0x054</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RST_CLR0</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the PRESETCTRL0 register, if they are implemented. Bits
that do not correspond to defined bits in PRESETCTRL0 are reserved
and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRLCLR1</name>
<description>Clear bits in PRESETCTRL1</description>
<addressOffset>0x058</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RST_CLR1</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the PRESETCTRL1 register, if they are implemented. Bits
that do not correspond to defined bits in PRESETCTRL1 are reserved
and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP0</name>
<description>POR captured PIO status 0</description>
<addressOffset>0x05C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOPORSTAT</name>
<description>State of PIO0_31 through PIO0_0 at power-on
reset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP1</name>
<description>POR captured PIO status 1</description>
<addressOffset>0x060</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOPORSTAT</name>
<description>State of PIO1_31 through PIO1_0 at power-on
reset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIORESCAP0</name>
<description>Reset captured PIO status 0</description>
<addressOffset>0x068</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIORESSTAT</name>
<description>State of PIO0_31 through PIO0_0 for resets other than
power-on reset.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIORESCAP1</name>
<description>Reset captured PIO status 1</description>
<addressOffset>0x06C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIORESSTAT</name>
<description>State of PIO1_31 through PIO1_0 for resets other than
power-on reset.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKSELA</name>
<description>Main clock source select A</description>
<addressOffset>0x080</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for main clock source selector A</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>CLKIN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKSELB</name>
<description>Main clock source select B</description>
<addressOffset>0x084</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for main clock source selector B. Selects the
clock source for the main clock.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MAINCLKSELA</name>
<description>MAINCLKSELA. Use the clock source selected in
MAINCLKSELA register.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_PLL_INPUT</name>
<description>System PLL input.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_PLL_OUTPUT</name>
<description>System PLL output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC_OSC_OUTPUT</name>
<description>RTC osc output. RTC oscillator 32 kHz
output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADCCLKSEL</name>
<description>ADC clock source select</description>
<addressOffset>0x08C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>ADC clock source.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MAIN_CLOCK</name>
<description>Main clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_PLL_OUTPUT</name>
<description>System PLL output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTSELA</name>
<description>CLKOUT clock source select A</description>
<addressOffset>0x094</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>CLKOUT clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MAIN_CLOCK</name>
<description>Main clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>CLKIN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC oscillator</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTSELB</name>
<description>CLKOUT clock source select B</description>
<addressOffset>0x098</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>CLKOUT clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CLKOUTSELA</name>
<description>CLKOUTSELA. Clock source selected in the CLKOUTSELA
register.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>reserved</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>reserved</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC_32_KHZ_CLOCK</name>
<description>RTC 32 kHz clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCLKSEL</name>
<description>PLL clock source select</description>
<addressOffset>0x0A0</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>System PLL clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>CLKIN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC_32_KHZ_CLOCK</name>
<description>RTC 32 kHz clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRL0</name>
<description>AHB Clock control 0</description>
<addressOffset>0x0C0</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ROM</name>
<description>Enables the clock for the Boot ROM. 0 = Disable; 1 =
Enable.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SRAM1</name>
<description>Enables the clock for SRAM1. 0 = Disable; 1 =
Enable.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SRAM2</name>
<description>Enables the clock for SRAM2. 0 = Disable; 1 =
Enable.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:5]</bitRange>
</field>
<field>
<name>FLASH</name>
<description>Enables the clock for the flash controller. 0 = Disable; 1
= Enable.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>FMC</name>
<description>Enables the clock for the Flash accelerator. 0 = Disable; 1
= Enable.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>INPUTMUX</name>
<description>Enables the clock for the input muxes. 0 = Disable; 1 =
Enable.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>IOCON</name>
<description>Enables the clock for the IOCON block. 0 = Disable; 1 =
Enable.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>GPIO0</name>
<description>Enables the clock for the GPIO0 port registers. 0 =
Disable; 1 = Enable.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>GPIO1</name>
<description>Enables the clock for the GPIO1 port registers. 0 =
Disable; 1 = Enable.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>PINT</name>
<description>Enables the clock for the pin interrupt block.0 = Disable;
1 = Enable.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>GINT</name>
<description>Enables the clock for the grouped pin interrupt block. 0 =
Disable; 1 = Enable.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>DMA</name>
<description>Enables the clock for the DMA controller. 0 = Disable; 1 =
Enable.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>CRC</name>
<description>Enables the clock for the CRC engine. 0 = Disable; 1 =
Enable.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>WWDT</name>
<description>Enables the clock for the Watchdog Timer. 0 = Disable; 1 =
Enable.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>RTC</name>
<description>Enables the clock for the RTC. 0 = Disable; 1 =
Enable.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:24]</bitRange>
</field>
<field>
<name>MAILBOX</name>
<description>Enables the clock for the Mailbox. 0 = Disable; 1 =
Enable.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>ADC0</name>
<description>Enables the clock for the ADC0 register interface. 0 =
Disable; 1 = Enable.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRL1</name>
<description>AHB Clock control 1</description>
<addressOffset>0x0C4</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MRT</name>
<description>Enables the clock for the Multi-Rate Timer. 0 = Disable; 1
= Enable.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RIT</name>
<description>Enables the clock for the repetitive interrupt timer. 0 =
Disable; 1 = Enable.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SCT0</name>
<description>Enables the clock for SCT0. 0 = Disable; 1 =
Enable.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[8:3]</bitRange>
</field>
<field>
<name>FIFO</name>
<description>Enables the clock for system FIFOs. 0 = Disable; 1 =
Enable.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>UTICK</name>
<description>Enables the clock for the Micro-tick Timer. 0 = Disable; 1
= Enable.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[21:11]</bitRange>
</field>
<field>
<name>TIMER2</name>
<description>Enables the clock for Timer 2. 0 = Disable; 1 =
Enable.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[25:23]</bitRange>
</field>
<field>
<name>TIMER3</name>
<description>Enables the clock for Timer 3. 0 = Disable; 1 =
Enable.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>TIMER4</name>
<description>Enables the clock for Timer 4. 0 = Disable; 1 =
Enable.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRLSET0</name>
<description>Set bits in AHBCLKCTRL0</description>
<addressOffset>0x0C8</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLK_SET0</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the AHBCLKCTRL0 register, if they are implemented. Bits that
do not correspond to defined bits in AHBCLKCTRL0 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRLSET1</name>
<description>Set bits in AHBCLKCTRL1</description>
<addressOffset>0x0CC</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLK_SET1</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the AHBCLKCTRL1 register, if they are implemented. Bits that
do not correspond to defined bits in AHBCLKCTRL1 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRLCLR0</name>
<description>Clear bits in AHBCLKCTRL0</description>
<addressOffset>0x0D0</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLK_CLR0</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the AHBCLKCTRL0 register, if they are implemented. Bits
that do not correspond to defined bits in AHBCLKCTRL0 are reserved
and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKCTRLCLR1</name>
<description>Clear bits in AHBCLKCTRL1</description>
<addressOffset>0x0D4</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLK_CLR1</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the AHBCLKCTRL1 register, if they are implemented. Bits
that do not correspond to defined bits in AHBCLKCTRL1 are reserved
and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSTICKCLKDIV</name>
<description>SYSTICK clock divider</description>
<addressOffset>0x0E0</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>SYSTICK clock divider value. 0: Disable SYSTICK timer
clock. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>AHBCLKDIV</name>
<description>System clock divider</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>System AHB clock divider value. 0: System clock disabled.
1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADCCLKDIV</name>
<description>ADC clock divider</description>
<addressOffset>0x108</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>ADC clock divider value. 0: Disable ADC clock. 1: Divide by
1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTDIV</name>
<description>CLKOUT clock divider</description>
<addressOffset>0x10C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>CLKOUT clock divider value. 0: Disable CLKOUT clock
divider. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FREQMECTRL</name>
<description>Frequency measure register</description>
<addressOffset>0x120</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPVAL</name>
<description>Stores the capture result which is used to calculate the
frequency of the target clock. This field is
read-only.</description>
<bitRange>[13:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[30:14]</bitRange>
</field>
<field>
<name>PROG</name>
<description>Set this bit to one to initiate a frequency measurement
cycle. Hardware clears this bit when the measurement cycle has
completed and there is valid capture data in the CAPVAL field (bits
13:0).</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>FLASHCFG</name>
<description>Flash wait states configuration</description>
<addressOffset>0x124</addressOffset>
<access>read-write</access>
<resetValue>0x5000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Do not change the value of these bits. Bits 11:0
must be written back exactly as read.</description>
<bitRange>[11:0]</bitRange>
</field>
<field>
<name>FLASHTIM</name>
<description>Flash memory access time. FLASHTIM +1 is equal to the
number of system clocks used for flash access.</description>
<bitRange>[14:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. 1 system clock flash access time
(for system clock frequencies of up to MHz).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. 2 system clocks flash access time
(for system clock frequencies of up to MHz).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. 3 system clocks flash access time
(for system clock frequencies of up to MHz).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_CLOCK_CYCLES</name>
<description>4 clock cycles. 4 system clocks flash access
time.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>5_CLOCK_CYCLES</name>
<description>5 clock cycles. 5 system clocks flash access
time.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>6_CLOCK_CYCLES</name>
<description>6 clock cycles. 6 system clocks flash access
time.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>7_CLOCK_CYCLES</name>
<description>7 clock cycles. 7 system clocks flash access
time.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>8_CLOCK_CYCLES</name>
<description>8 clock cycles. 8 system clocks flash access
time.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not change the value of these bits. Bits 31:2
must be written back exactly as read.</description>
<bitRange>[31:15]</bitRange>
</field>
</fields>
</register>
<register>
<name>FIFOCTRL</name>
<description>Serial interface FIFO enables</description>
<addressOffset>0x148</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>U0TXFIFOEN</name>
<description>USART0 transmitter FIFO enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>U1TXFIFOEN</name>
<description>USART1 transmitter FIFO enable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>U2TXFIFOEN</name>
<description>USART2 transmitter FIFO enable</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>U3TXFIFOEN</name>
<description>USART3 transmitter FIFO enable</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SPI0TXFIFOEN</name>
<description>SPI0 transmitter FIFO enable</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SPI1TXFIFOEN</name>
<description>SPI1 transmitter FIFO enable</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>U0RXFIFOEN</name>
<description>USART0 receiver FIFO enable</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>U1RXFIFOEN</name>
<description>USART1 receiver FIFO enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>U2RXFIFOEN</name>
<description>USART2 receiver FIFO enable</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>U3RXFIFOEN</name>
<description>USART3 receiver FIFO enable</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>SPI0RXFIFOEN</name>
<description>SPI0 receiver FIFO enable</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>SPI1RXFIFOEN</name>
<description>SPI1 receiver FIFO enable</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:14]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRCCTRL</name>
<description>IRC oscillator control</description>
<addressOffset>0x184</addressOffset>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>Trim value</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RTCOSCCTRL</name>
<description>RTC oscillator 32 kHz output control</description>
<addressOffset>0x190</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>RTC 32 kHz clock enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. RTC clock off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. RTC clock on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCTRL</name>
<description>PLL control</description>
<addressOffset>0x1B0</addressOffset>
<access>read-write</access>
<resetValue>0x8000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SELR</name>
<description>Bandwidth select R value</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>SELI</name>
<description>Bandwidth select I value</description>
<bitRange>[9:4]</bitRange>
</field>
<field>
<name>SELP</name>
<description>Bandwidth select P value</description>
<bitRange>[14:10]</bitRange>
</field>
<field>
<name>BYPASS</name>
<description>PLL bypass control</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. PLL CCO is used to create the PLL
output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. PLL is bypassed, the PLL input clock is
routed directly to the PLL output (default).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYPASSCCODIV2</name>
<description>Bypass feedback clock divide by 2.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DIVIDE_BY_2</name>
<description>Divide by 2. The CCO feedback clock is divided by 2
in addition to the programmed M divide.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS</name>
<description>Bypass. The CCO feedback clock is divided only by
the programmed M divide.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UPLIMOFF</name>
<description>Enable spread spectrum/fractional mode</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL_MODE</name>
<description>Normal mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSGC_MODE</name>
<description>SSGC mode. Spread spectrum/fractional
mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BANDSEL</name>
<description>PLL filter control. Set this bit to one when the SSGC is
disabled or at low frequencies.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSCG_CONTROL</name>
<description>SSCG control. The PLL filter uses the parameters
derived from the SSCG decoder.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MDEC_CONTROL</name>
<description>MDEC control. The PLL filter uses the programmable
fields SELP, SELR, and SELI in this register to control the
filter constants.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRECTI</name>
<description>PLL0 direct input enable</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The PLL input divider (N divider) output
is used to drive the PLL CCO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The PLL input divider (N divider) is
bypassed. the PLL input clock is used directly to drive the
PLL CCO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRECTO</name>
<description>PLL0 direct output enable</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The PLL output divider (P divider) is
used to create the PLL output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The PLL output divider (P divider) is
bypassed, the PLL CCO output is used as the PLL
output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLSTAT</name>
<description>PLL status</description>
<addressOffset>0x1B4</addressOffset>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCK</name>
<description>PLL0 lock indicator</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLNDEC</name>
<description>PLL N decoder</description>
<addressOffset>0x1B8</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NDEC</name>
<description>Decoded N-divider coefficient value</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>NREQ</name>
<description>NDEC reload request. When a 1 is written to this bit, the
NDEC value is loaded into the PLL. Must be cleared by software for
any subsequent load, or the PLL can be powered down and back up via
the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is
changed.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLPDEC</name>
<description>PLL P decoder</description>
<addressOffset>0x1BC</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDEC</name>
<description>Decoded P-divider coefficient value</description>
<bitRange>[6:0]</bitRange>
</field>
<field>
<name>PREQ</name>
<description>PDEC reload request. When a 1 is written to this bit, the
PDEC value is loaded into the PLL. Must be cleared by software for
any subsequent load, or the PLL can be powered down and back up via
the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is
changed.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLSSCTRL0</name>
<description>PLL spread spectrum control 0</description>
<addressOffset>0x1C0</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MDEC</name>
<description>Decoded M-divider coefficient value</description>
<bitRange>[16:0]</bitRange>
</field>
<field>
<name>MREQ</name>
<description>MDEC reload request. When a 1 is written to this bit, the
MDEC value is loaded into the PLL. Must be cleared by software for
any subsequent load, or the PLL can be powered down and back up via
the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is
changed.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SEL_EXT</name>
<description>Select spread spectrum mode.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SPREAD_SPECTRUM_MODE</name>
<description>Spread spectrum mode. Spread spectrum mode
enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MDEC_ENABLED</name>
<description>MDEC enabled. Spread spectrum clock generator not
used.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:19]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLSSCTRL1</name>
<description>PLL spread spectrum control 1</description>
<addressOffset>0x1C4</addressOffset>
<access>read-write</access>
<resetValue>0x10000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MD</name>
<description>M- divider value with fraction. MD[18:11] : integer portion
of the feedback divider value. MD[10:0] : fractional portion of the
feedback divider value.</description>
<bitRange>[18:0]</bitRange>
</field>
<field>
<name>MDREQ</name>
<description>MD reload request. When a 1 is written to this bit, the MD
value is loaded into the PLL. This bit is cleared when the load is
complete.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MF</name>
<description>Programmable modulation frequency fm = Fref/Nss with Fref =
Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm
= 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 =>
Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm = 32.3 - 64.5
kHz) 0b101 => Nss = 32 (fm = 62.5- 125 kHz) 0b110 => Nss = 24 (fm =
83.3- 166.6 kHz) 0b111 => Nss = 16 (fm = 125- 250 kHz)</description>
<bitRange>[22:20]</bitRange>
</field>
<field>
<name>MR</name>
<description>Programmable frequency modulation depth deltafmodpk-pk =
Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread
spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k
= 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8</description>
<bitRange>[25:23]</bitRange>
</field>
<field>
<name>MC</name>
<description>Modulation waveform control 0 = no compensation
Compensation for low pass filtering of the PLL to get a triangular
modulation at the output of the PLL, giving a flat frequency
spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11
=> max. compensation</description>
<bitRange>[27:26]</bitRange>
</field>
<field>
<name>PD</name>
<description>Power down.</description>
<bitRange>[28:28]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Spread spectrum controller is
enabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Spread spectrum controller is
disabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DITHER</name>
<description>Select modulation frequency.</description>
<bitRange>[29:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FIXED</name>
<description>Fixed. Fixed modulation frequency.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DITHER</name>
<description>Dither. Randomly dither between two modulation
frequencies.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:30]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDRUNCFG</name>
<description>Power configuration register</description>
<addressOffset>0x210</addressOffset>
<access>read-write</access>
<resetValue>0x500500</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>PDEN_IRC_OSC</name>
<description>IRC oscillator output. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PDEN_IRC</name>
<description>IRC oscillator. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PDEN_FLASH</name>
<description>Flash memory. 0 = Powered; 1 = Powered down.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PDEN_BOD_RST</name>
<description>Brown-out Detect reset. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>PDEN_BOD_INTR</name>
<description>Brown-out Detect interrupt. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>PDEN_ADC0</name>
<description>ADC0. 0 = Powered; 1 = Powered down.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[12:11]</bitRange>
</field>
<field>
<name>PDEN_SRAM0A</name>
<description>First 8 kB of SRAM0). 0 = Powered; 1 = Powered
down.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PDEN_SRAM0B</name>
<description>Remaining portion of SRAM0). 0 = Powered; 1 = Powered
down.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>PDEN_SRAM1</name>
<description>SRAM1. 0 = Powered; 1 = Powered down.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>PDEN_SRAM2</name>
<description>SRAM2 (undedicated 8 kB RAM). 0 = Powered; 1 = Powered
down.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>PDEN_ROM</name>
<description>ROM. 0 = Powered; 1 = Powered down.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>PDEN_VDDA</name>
<description>Vdda to the ADC, must be enabled for the ADC to work. Also
see bit 23. 0 = Powered; 1 = Powered down.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>PDEN_WDT_OSC</name>
<description>Watchdog oscillator. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>PDEN_SYS_PLL</name>
<description>PLL0. 0 = Powered; 1 = Powered down.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>PDEN_VREFP</name>
<description>Vrefp to the ADC, must be enabled for the ADC to work. Also
see bit 19. 0 = Powered; 1 = Powered down.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>PDEN_32K_OSC</name>
<description>32 kHz RTC oscillator. 0 = Powered; 1 = Powered
down.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:25]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDRUNCFGSET</name>
<description>Set bits in PDRUNCFG</description>
<addressOffset>0x214</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PD_SET</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the PDRUNCFG register, if they are implemented. Bits that do
not correspond to defined bits in PDRUNCFG are reserved and only
zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDRUNCFGCLR</name>
<description>Clear bits in PDRUNCFG</description>
<addressOffset>0x218</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PD_CLR</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the PDRUNCFG register, if they are implemented. Bits that
do not correspond to defined bits in PDRUNCFG are reserved and only
zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERP0</name>
<description>Start logic 0 wake-up enable register</description>
<addressOffset>0x240</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WWDT</name>
<description>WWDT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>BOD</name>
<description>BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>DMA</name>
<description>DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
Typically used in sleep mode only.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>GINT0</name>
<description>Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PINT0</name>
<description>GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PINT1</name>
<description>GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PINT2</name>
<description>GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>PINT3</name>
<description>GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>UTICK</name>
<description>Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MRT</name>
<description>Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Typically used in sleep mode only.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>TIMER0</name>
<description>Timer 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>TIMER1</name>
<description>Timer 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>TIMER2</name>
<description>Timer 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>TIMER3</name>
<description>Timer 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>TIMER4</name>
<description>Timer 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>SCT0</name>
<description>SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.Typically used in sleep mode only.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>USART0</name>
<description>USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>USART1</name>
<description>USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>USART2</name>
<description>USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>USART3</name>
<description>USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>I2C0</name>
<description>I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>I2C1</name>
<description>I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>I2C2</name>
<description>I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>SPI0</name>
<description>SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SPI1</name>
<description>SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled. Peripheral interrupt.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>ADC0_SEQA</name>
<description>ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1
= Wake-up enabled.Typically used in sleep mode only.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>ADC0_SEQB</name>
<description>ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1
= Wake-up enabled.Typically used in sleep mode only.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>ADC0_THCMP</name>
<description>ADC0 threshold and error interrupt wake-up. 0 = Wake-up
disabled. 1 = Wake-up enabled.Typically used in sleep mode
only.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>RTC</name>
<description>RTC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up
enabled.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>MAILBOX</name>
<description>Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled.Typically used in sleep mode only.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERP1</name>
<description>Start logic 1 wake-up enable register</description>
<addressOffset>0x244</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GINT1</name>
<description>Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PINT4</name>
<description>GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PINT5</name>
<description>GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PINT6</name>
<description>GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PINT7</name>
<description>GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 =
Wake-up enabled. Not for pattern match.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>RIT</name>
<description>Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up
disabled. 1 = Wake-up enabled. Typically used in sleep mode
only.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:15]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERPSET0</name>
<description>Set bits in STARTERP0</description>
<addressOffset>0x248</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>START_SET0</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the STARTERP0 register, if they are implemented. Bits that
do not correspond to defined bits in STARTERP0 are reserved and only
zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERPSET1</name>
<description>Set bits in STARTERP1</description>
<addressOffset>0x24C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>START_SET1</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the STARTERP1 register, if they are implemented. Bits that
do not correspond to defined bits in STARTERP1 are reserved and only
zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERPCLR0</name>
<description>Clear bits in STARTERP0</description>
<addressOffset>0x250</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>START_CLR0</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the STARTERP0 register, if they are implemented. Bits
that do not correspond to defined bits in STARTERP0 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERPCLR1</name>
<description>Clear bits in STARTERP1</description>
<addressOffset>0x254</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>START_CLR1</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the STARTERP1 register, if they are implemented. Bits
that do not correspond to defined bits in STARTERP1 are reserved and
only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CPUCTRL</name>
<description>CPU Control for multiple processors</description>
<addressOffset>0x300</addressOffset>
<access>read-write</access>
<resetValue>0x4D</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASTERCPU</name>
<description>Determines which CPU is considered the master. The master
CPU cannot have its clock turned off via the related CMnCLKEN bit or
be reset via the related CMxRSTEN in this register. The slave CPU
wakes up briefly following device reset, then goes back to sleep
until activated by the master CPU.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>M0P</name>
<description>M0+. Cortex-M0+ is the master CPU.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>M4</name>
<description>M4. Cortex-M4 is the master CPU.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CM4CLKEN</name>
<description>Cortex-M4 clock enable.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Cortex-M4 clock is not
enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Cortex-M4 clock is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM0CLKEN</name>
<description>Cortex-M0+ clock enable.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Cortex-M0+ clock is not
enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Cortex-M0+ clock is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM4RSTEN</name>
<description>Cortex-M4 reset.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Cortex-M4 is not being
reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Cortex-M4 is being
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM0RSTEN</name>
<description>Cortex-M0+ reset.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Cortex-M0+ is not being
reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Cortex-M0+ is being
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POWERCPU</name>
<description>Identifies the owner of reduced power mode control: which
CPU can cause the device to enter Sleep, Deep Sleep, Power-down, and
Deep Power-down modes.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>M0P</name>
<description>M0+. Cortex-M0+ is the owner of reduced power mode
control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>M4</name>
<description>M4. Cortex-M4 is the owner of reduced power mode
control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>CPBOOT</name>
<description>Coprocessor Boot Address</description>
<addressOffset>0x304</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BOOTADDR</name>
<description>Slave processor boot address.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CPSTACK</name>
<description>Coprocessor Stack Address</description>
<addressOffset>0x308</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STACKADDR</name>
<description>Slave processor stack address.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>JTAGIDCODE</name>
<description>JTAG ID code register</description>
<addressOffset>0x3F4</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>JTAGID</name>
<description>JTAG ID code.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVICE_ID0</name>
<description>Part ID register</description>
<addressOffset>0x3F8</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PARTID</name>
<description>Part ID</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVICE_ID1</name>
<description>Boot ROM and die revision register</description>
<addressOffset>0x3FC</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>REVID</name>
<description>Revision.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CT32B2</name>
<description>Standard counter/timer 2 </description>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B2</name>
<value>13</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The
IR can be read to identify which of eight possible interrupt sources are
pending.</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CR3INT</name>
<description>Interrupt flag for capture channel 3 event.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through the
TCR.</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Timer Counter and Prescale Counter are
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.</description>
<addressOffset>0x08</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCVAL</name>
<description>Timer counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (PC) is equal to this
value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0x0C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRVAL</name>
<description>Prescale counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 32 bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and controllable
through the bus interface.</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescale counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt
is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0
matches the value in the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it. 0 =
disabled. 1 = enabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR0 matches the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1
matches the value in the TC. 0 = disabled. 1 = enabled. 0 =
disabled. 1 = enabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it. 0 =
disabled. 1 = enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR1 matches the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2
matches the value in the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it. 0 =
disabled. 1 = enabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR2 matches the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3
matches the value in the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it. 0 =
disabled. 1 = enabled.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR3 matches the TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MR%s</name>
<description>Match Register 0. MR0 can be enabled through the MCR to reset the
TC, stop both the TC and PC, and/or generate an interrupt every time MR0
matches the TC.</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place.</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Rising edge of capture channel 0: a sequence of 0 then 1
causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CAP0FE</name>
<description>Falling edge of capture channel 0: a sequence of 1 then 0
causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CAP0I</name>
<description>Generate interrupt on channel 0 capture event: a CR0 load
generates an interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CAP1RE</name>
<description>Rising edge of capture channel 1: a sequence of 0 then 1
causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CAP1FE</name>
<description>Falling edge of capture channel 1: a sequence of 1 then 0
causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CAP1I</name>
<description>Generate interrupt on channel 1 capture event: a CR1 load
generates an interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CAP2RE</name>
<description>Rising edge of capture channel 2: a sequence of 0 then 1
causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CAP2FE</name>
<description>Falling edge of capture channel 2: a sequence of 1 then 0
causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CAP2I</name>
<description>Generate interrupt on channel 2 capture event: a CR2 load
generates an interrupt.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>CAP3RE</name>
<description>Rising edge of capture channel 3: a sequence of 0 then 1
causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>CAP3FE</name>
<description>Falling edge of capture channel 3: a sequence of 1 then 0
causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
enabled.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>CAP3I</name>
<description>Generate interrupt on channel 3 capture event: a CR3 load
generates an interrupt.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CR%s</name>
<description>Capture Register 0. CR0 is loaded with the value of TC when there
is an event on the CAPn.0 input.</description>
<addressOffset>0x2C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and
the external match pins.</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output
MAT0, whether or not this output is connected to a pin. When a match
occurs between the TC and MR0, this bit can either toggle, go LOW,
go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven
to the MAT pins if the match function is selected via IOCON. 0 =
LOW. 1 = HIGH.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output
MAT1, whether or not this output is connected to a pin. When a match
occurs between the TC and MR1, this bit can either toggle, go LOW,
go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven
to the MAT pins if the match function is selected via IOCON. 0 =
LOW. 1 = HIGH.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of output
MAT2, whether or not this output is connected to a pin. When a match
occurs between the TC and MR2, this bit can either toggle, go LOW,
go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven
to the MAT pins if the match function is selected via IOCON. 0 =
LOW. 1 = HIGH.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output
MAT3, whether or not this output is connected to a pin. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW,
go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven
to the MAT pins if the match function is selected via IOCON. 0 =
LOW. 1 = HIGH.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of
External Match 0.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match
bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of
External Match 1.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match
bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of
External Match 2.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match
bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of
External Match 3.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match
bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter
mode, and in Counter mode selects the signal and edge(s) for
counting.</description>
<addressOffset>0x70</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTMODE</name>
<description>Counter/Timer Mode This field selects which rising PCLK
edges can increment Timer's Prescale Counter (PC), or clear PC and
increment Timer Counter (TC). Timer Mode: the TC is incremented when
the Prescale Counter matches the Prescale Register.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_MODE</name>
<description>Timer Mode. Incremented every rising PCLK
edge.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_RISING</name>
<description>Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_FALLING</name>
<description>Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_DUAL_ED</name>
<description>Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CINSEL</name>
<description>Count Input Select When bits 1:0 in this register are not
00, these bits select which CAP pin is sampled for clocking. Note:
If Counter mode is selected for a particular CAPn input in the CTCR,
the 3 bits for that input in the Capture Control Register (CCR) must
be programmed as 000. However, capture and/or interrupt can be
selected for the other 3 CAPn inputs in the same
timer.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CHANNEL_0</name>
<description>Channel 0. CAPn.0 for TIMERn</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1</name>
<description>Channel 1. CAPn.1 for TIMERn</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2</name>
<description>Channel 2. CAPn.2 for TIMERn</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_3</name>
<description>Channel 3. CAPn.3 for TIMERn</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SELCC</name>
<description>Edge select. When bit 4 is 1, these bits select which
capture input edge will cause the timer and prescaler to be cleared.
These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and
0x6 to 0x7 are reserved.</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CHANNEL_0_RISING_EDG</name>
<description>Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_0_FALLING_ED</name>
<description>Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1_RISING_EDG</name>
<description>Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1_FALLING_ED</name>
<description>Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2_RISING_EDG</name>
<description>Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2_FALLING_ED</name>
<description>Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external
match pins.</description>
<addressOffset>0x74</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CT32Bn_MAT0 is controlled by
EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for
CT32Bn_MAT0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CT32Bn_MAT01 is controlled by
EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for
CT32Bn_MAT1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CT32Bn_MAT2 is controlled by
EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for
CT32Bn_MAT2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3. Note: It is recommended to
use match channel 3 to set the PWM cycle.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CT32Bn_MAT3 is controlled by
EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for
CT132Bn_MAT3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CT32B2">
<name>CT32B3</name>
<description>Standard counter/timer 3 </description>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B3</name>
<value>14</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="CT32B2">
<name>CT32B4</name>
<description>Standard counter/timer 4 </description>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B4</name>
<value>15</value>
</interrupt>
</peripheral>
<peripheral>
<name>GINT0</name>
<description>Group GPIO input interrupt 0</description>
<groupName>GINT0</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT0</name>
<value>4</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>GPIO grouped interrupt control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT</name>
<description>Group interrupt status. This bit is cleared by writing a
one to it. Writing zero has no effect.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_REQUEST</name>
<description>No request. No interrupt request is
pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REQUEST_ACTIVE</name>
<description>Request active. Interrupt request is
active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMB</name>
<description>Combine enabled inputs for group interrupt</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OR</name>
<description>Or. OR functionality: A grouped interrupt is
generated when any one of the enabled inputs is active
(based on its programmed polarity).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AND</name>
<description>And. AND functionality: An interrupt is generated
when all enabled bits are active (based on their programmed
polarity).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG</name>
<description>Group interrupt trigger</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EDGE_TRIGGERED</name>
<description>Edge-triggered.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_TRIGGERED</name>
<description>Level-triggered.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>PORT_POL%s</name>
<description>GPIO grouped interrupt port 0 polarity register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL</name>
<description>Configure pin polarity of port m pins for group interrupt.
Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active
LOW. If the level on this pin is LOW, the pin contributes to the
group interrupt. 1 = the pin is active HIGH. If the level on this
pin is HIGH, the pin contributes to the group
interrupt.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>PORT_ENA%s</name>
<description>GPIO grouped interrupt port 0 enable register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to
pin Pm_n of port m. 0 = the port 0 pin is disabled and does not
contribute to the grouped interrupt. 1 = the port 0 pin is enabled
and contributes to the grouped interrupt.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GINT0">
<name>GINT1</name>
<description>Group GPIO input interrupt 1</description>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT1</name>
<value>32</value>
</interrupt>
</peripheral>
<peripheral>
<name>PINT</name>
<description>Pin interrupt and pattern match engine</description>
<groupName>PINT</groupName>
<baseAddress>0x40018000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIN_INT0</name>
<value>5</value>
</interrupt>
<interrupt>
<name>PIN_INT1</name>
<value>6</value>
</interrupt>
<interrupt>
<name>PIN_INT2</name>
<value>7</value>
</interrupt>
<interrupt>
<name>PIN_INT3</name>
<value>8</value>
</interrupt>
<interrupt>
<name>PIN_INT4</name>
<value>33</value>
</interrupt>
<interrupt>
<name>PIN_INT5</name>
<value>34</value>
</interrupt>
<interrupt>
<name>PIN_INT6</name>
<value>35</value>
</interrupt>
<interrupt>
<name>PIN_INT7</name>
<value>36</value>
</interrupt>
<registers>
<register>
<name>ISEL</name>
<description>Pin Interrupt Mode register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMODE</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n
configures the pin interrupt selected in PINTSELn. 0 = Edge
sensitive 1 = Level sensitive</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENR</name>
<description>Pin interrupt level or rising edge interrupt enable
register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENRL</name>
<description>Enables the rising edge or level interrupt for each pin
interrupt. Bit n configures the pin interrupt selected in PINTSELn.
0 = Disable rising edge or level interrupt. 1 = Enable rising edge
or level interrupt.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENR</name>
<description>Pin interrupt level or rising edge interrupt set
register</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENRL</name>
<description>Ones written to this address set bits in the IENR, thus
enabling interrupts. Bit n sets bit n in the IENR register. 0 = No
operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENR</name>
<description>Pin interrupt level (rising edge interrupt) clear
register</description>
<addressOffset>0x00C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENRL</name>
<description>Ones written to this address clear bits in the IENR, thus
disabling the interrupts. Bit n clears bit n in the IENR register. 0
= No operation. 1 = Disable rising edge or level
interrupt.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENF</name>
<description>Pin interrupt active level or falling edge interrupt enable
register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENAF</name>
<description>Enables the falling edge or configures the active level
interrupt for each pin interrupt. Bit n configures the pin interrupt
selected in PINTSELn. 0 = Disable falling edge interrupt or set
active interrupt level LOW. 1 = Enable falling edge interrupt
enabled or set active interrupt level HIGH.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENF</name>
<description>Pin interrupt active level or falling edge interrupt set
register</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENAF</name>
<description>Ones written to this address set bits in the IENF, thus
enabling interrupts. Bit n sets bit n in the IENF register. 0 = No
operation. 1 = Select HIGH-active interrupt or enable falling edge
interrupt.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENF</name>
<description>Pin interrupt active level or falling edge interrupt clear
register</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENAF</name>
<description>Ones written to this address clears bits in the IENF, thus
disabling interrupts. Bit n clears bit n in the IENF register. 0 =
No operation. 1 = LOW-active interrupt selected or falling edge
interrupt disabled.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RISE</name>
<description>Pin interrupt rising edge register</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDET</name>
<description>Rising edge detect. Bit n detects the rising edge of the
pin selected in PINTSELn. Read 0: No rising edge has been detected
on this pin since Reset or the last time a one was written to this
bit. Write 0: no operation. Read 1: a rising edge has been detected
since Reset or the last time a one was written to this bit. Write 1:
clear rising edge detection for this pin.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FALL</name>
<description>Pin interrupt falling edge register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FDET</name>
<description>Falling edge detect. Bit n detects the falling edge of the
pin selected in PINTSELn. Read 0: No falling edge has been detected
on this pin since Reset or the last time a one was written to this
bit. Write 0: no operation. Read 1: a falling edge has been detected
since Reset or the last time a one was written to this bit. Write 1:
clear falling edge detection for this pin.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IST</name>
<description>Pin interrupt status register</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PSTAT</name>
<description>Pin interrupt status. Bit n returns the status, clears the
edge interrupt, or inverts the active level of the pin selected in
PINTSELn. Read 0: interrupt is not being requested for this
interrupt pin. Write 0: no operation. Read 1: interrupt is being
requested for this interrupt pin. Write 1 (edge-sensitive): clear
rising- and falling-edge detection for this pin. Write 1
(level-sensitive): switch the active level for this pin (in the IENF
register).</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Pattern match interrupt control register</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL_PMATCH</name>
<description>Specifies whether the 8 pin interrupts are controlled by
the pin interrupt function or by the pattern match
function.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIN_INTERRUPT</name>
<description>Pin interrupt. Interrupts are driven in response to
the standard pin interrupt function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PATTERN_MATCH</name>
<description>Pattern match. Interrupts are driven in response to
pattern matches.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENA_RXEV</name>
<description>Enables the RXEV output to the CPU and/or to a GPIO output
when the specified boolean expression evaluates to
true.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. RXEV output to the CPU is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. RXEV output to the CPU is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write 1s to unused bits.</description>
<bitRange>[23:2]</bitRange>
</field>
<field>
<name>PMAT</name>
<description>This field displays the current state of pattern matches. A
1 in any bit of this field indicates that the corresponding product
term is matched by the current state of the appropriate
inputs.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>PMSRC</name>
<description>Pattern match interrupt bit-slice source register</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Reserved</name>
<description>Software should not write 1s to unused bits.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>SRC0</name>
<description>Selects the input source for bit slice 0</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 0.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 0.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 0.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 0.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC1</name>
<description>Selects the input source for bit slice 1</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 1.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 1.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 1.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 1.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC2</name>
<description>Selects the input source for bit slice 2</description>
<bitRange>[16:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 2.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 2.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 2.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 2.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 2.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 2.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC3</name>
<description>Selects the input source for bit slice 3</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 3.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 3.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 3.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 3.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 3.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 3.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 3.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC4</name>
<description>Selects the input source for bit slice 4</description>
<bitRange>[22:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 4.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 4.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 4.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 4.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 4.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 4.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC5</name>
<description>Selects the input source for bit slice 5</description>
<bitRange>[25:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 5.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 5.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 5.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 5.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 5.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 5.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 5.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC6</name>
<description>Selects the input source for bit slice 6</description>
<bitRange>[28:26]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 6.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 6.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 6.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 6.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 6.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 6.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 6.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 6.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC7</name>
<description>Selects the input source for bit slice 7</description>
<bitRange>[31:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 7.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 7.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 7.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 7.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 7.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 7.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 7.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 7.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCFG</name>
<description>Pattern match interrupt bit slice configuration
register</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PROD_ENDPTS0</name>
<description>Determines whether slice 0 is an endpoint.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 0 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 0 is the endpoint of a product term
(minterm). Pin interrupt 0 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS1</name>
<description>Determines whether slice 1 is an endpoint.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 1 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 1 is the endpoint of a product term
(minterm). Pin interrupt 1 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS2</name>
<description>Determines whether slice 2 is an endpoint.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 2 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 2 is the endpoint of a product term
(minterm). Pin interrupt 2 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS3</name>
<description>Determines whether slice 3 is an endpoint.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 3 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 3 is the endpoint of a product term
(minterm). Pin interrupt 3 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS4</name>
<description>Determines whether slice 4 is an endpoint.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 4 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 4 is the endpoint of a product term
(minterm). Pin interrupt 4 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS5</name>
<description>Determines whether slice 5 is an endpoint.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 5 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 5 is the endpoint of a product term
(minterm). Pin interrupt 5 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS6</name>
<description>Determines whether slice 6 is an endpoint.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 6 is not an
endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 6 is the endpoint of a product term
(minterm). Pin interrupt 6 in the NVIC is raised if the
minterm evaluates as true.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Bit slice 7 is automatically considered a product
end point.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CFG0</name>
<description>Specifies the match contribution condition for bit slice
0.</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG1</name>
<description>Specifies the match contribution condition for bit slice
1.</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG2</name>
<description>Specifies the match contribution condition for bit slice
2.</description>
<bitRange>[16:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG3</name>
<description>Specifies the match contribution condition for bit slice
3.</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG4</name>
<description>Specifies the match contribution condition for bit slice
4.</description>
<bitRange>[22:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG5</name>
<description>Specifies the match contribution condition for bit slice
5.</description>
<bitRange>[25:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG6</name>
<description>Specifies the match contribution condition for bit slice
6.</description>
<bitRange>[28:26]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG7</name>
<description>Specifies the match contribution condition for bit slice
7.</description>
<bitRange>[31:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to
a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level
on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0</name>
<description>Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IOCON</name>
<description>I/O pin configuration </description>
<groupName>IOCON</groupName>
<baseAddress>0x4001C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>16</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-15</dimIndex>
<name>PIO0_%s</name>
<description>Digital I/O control for port 0 pins PIO0_0 to
PIO0_15.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00000190</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE</name>
<description>Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE</name>
<description>Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>16-17</dimIndex>
<name>PIO0_%s</name>
<description>Digital I/O control for port 0 pins PIO0_16 to
PIO0_17.</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0x00000195</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE</name>
<description>Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE</name>
<description>Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>18-22</dimIndex>
<name>PIO0_%s</name>
<description>Digital I/O control for port 0 pins PIO0_18 to
PIO0_22.</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0x00000190</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE</name>
<description>Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE</name>
<description>Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>6</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>23-28</dimIndex>
<name>PIO0_%s</name>
<description>Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins
support I2C with true open-drain, drive and filtering for modes up to
Fast-mode Plus.</description>
<addressOffset>0x05C</addressOffset>
<access>read-write</access>
<resetValue>0x000001A0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[4:3]</bitRange>
</field>
<field>
<name>I2CSLEW</name>
<description>Controls slew rate of I2C pad.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>I2C_MODE</name>
<description>I2C mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_MODE</name>
<description>GPIO mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2CDRIVE</name>
<description>Controls the current sink capability of the
pin.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2CFILTER</name>
<description>Configures I2C features for standard mode, fast mode, and
Fast Mode Plus operation.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. I2C 50 ns glitch filter
enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. I2C 50 ns glitch filter
disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>29-31</dimIndex>
<name>PIO0_%s</name>
<description>Digital I/O control for port 0 pins PIO0_29 to PIO0_31. These pins
include an ADC input.</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0x00000190</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>9</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-8</dimIndex>
<name>PIO1_%s</name>
<description>Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins
include an ADC input.</description>
<addressOffset>0x080</addressOffset>
<access>read-write</access>
<resetValue>0x00000190</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<dim>9</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>9-17</dimIndex>
<name>PIO1_%s</name>
<description>Digital I/O control for port 1 pins PIO1_9 to
PIO1_17.</description>
<addressOffset>0x0A4</addressOffset>
<access>read-write</access>
<resetValue>0x00000190</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor
control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor
enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor
enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVERT</name>
<description>Input polarity.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Input function is not
inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Input is function inverted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGIMODE</name>
<description>Select Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_MODE</name>
<description>Analog mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_MODE</name>
<description>Digital mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTEROFF</name>
<description>Controls input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_ENABLED</name>
<description>Filter enabled. Noise pulses below approximately 10
ns are filtered out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_DISABLED</name>
<description>Filter disabled. No input filtering is
done</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE</name>
<description>Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE</name>
<description>Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Controls open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal. Normal push-pull output</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN</name>
<description>Open-drain. Simulated open-drain output (high drive
disabled)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UTICK</name>
<description>Micro-tick timer</description>
<groupName>UTICK</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UTICK</name>
<value>9</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Control register.</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DELAYVAL</name>
<description>Tick interval value. The delay will be equal to DELAYVAL +
1 periods of the timer clock. The minimum usable value is 1, for a
delay of 2 timer clocks. A value of 0 stops the timer.</description>
<bitRange>[30:0]</bitRange>
</field>
<field>
<name>REPEAT</name>
<description>Repeat delay. 0 = One-time delay. 1 = Delay repeats
continuously.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>Status register.</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTR</name>
<description>Interrupt flag. 0 = No interrupt is pending. 1 = An
interrupt is pending. A write of any value to this register clears
this flag.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ACTIVE</name>
<description>Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The
Micro-Tick Timer is currently active.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADVSYSCON</name>
<description>Advanced System configuration </description>
<groupName>ADVSYSCON</groupName>
<baseAddress>0x4002C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>BOD</name>
<value>1</value>
</interrupt>
<registers>
<register>
<name>BODCTRL</name>
<description>Brown-Out Detect control</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BODRSTLEV</name>
<description>BOD reset level</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_0_1</name>
<description>Level 0: 1.5 V</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_1_1</name>
<description>Level 1: 1.85 V</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2_2</name>
<description>Level 2: 2.0 V</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3_2</name>
<description>Level 3: 2.3 V</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODINTVAL</name>
<description>BOD interrupt level</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_0_2</name>
<description>Level 0: 2.05 V</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_1_2</name>
<description>Level 1: 2.45 V</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2_2</name>
<description>Level 2: 2.75 V</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3_3</name>
<description>Level 3: 3.05 V</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODRSTENA</name>
<description>BOD reset enable</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_RESET_FUNCTI</name>
<description>Disable reset function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_RESET_FUNCTIO</name>
<description>Enable reset function.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDT</name>
<description>Windowed Watchdog Timer</description>
<groupName>WWDT</groupName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDT</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>MOD</name>
<description>Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDEN</name>
<description>Watchdog enable bit. Once this bit is set to one and a
watchdog feed is performed, the watchdog timer will run
permanently.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STOP</name>
<description>Stop. The watchdog timer is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUN</name>
<description>Run. The watchdog timer is running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRESET</name>
<description>Watchdog reset enable bit. Once this bit has been written
with a 1 it cannot be re-written with a 0.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INTERRUPT</name>
<description>Interrupt. A watchdog time-out will not cause a
chip reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Reset. A watchdog time-out will cause a chip
reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOF</name>
<description>Watchdog time-out flag. Set when the watchdog timer times
out, by a feed error, or by events associated with WDPROTECT.
Cleared by software. Causes a chip reset if WDRESET =
1.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>WDINT</name>
<description>Warning interrupt flag. Set when the timer reaches the
value in WDWARNINT. Cleared by software.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>WDPROTECT</name>
<description>Watchdog update mode. This bit can be set once by software
and is only cleared by a reset.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FLEXIBLE</name>
<description>Flexible. The watchdog time-out value (TC) can be
changed at any time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD</name>
<description>Threshold. The watchdog time-out value (TC) can be
changed only after the counter is below the value of
WDWARNINT and WDWINDOW.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Once this bit is set to one and a watchdog feed is
performed, disabling or powering down the watchdog oscillator is
prevented by hardware. This bit can be set once by software and is
only cleared by any reset.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Watchdog timer constant register. This 24-bit register determines
the time-out value.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Watchdog time-out value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>FEED</name>
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to
this register reloads the Watchdog timer with the value contained in
WDTC.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>FEED</name>
<description>Feed value should be 0xAA followed by 0x55.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>TV</name>
<description>Watchdog timer value register. This 24-bit register reads out the
current value of the Watchdog timer.</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter timer value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>WARNINT</name>
<description>Watchdog Warning Interrupt compare value.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WARNINT</name>
<description>Watchdog warning interrupt compare value.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, only zero should be written.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>WINDOW</name>
<description>Watchdog Window compare value.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WINDOW</name>
<description>Watchdog window value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, only zero should be written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real-Time Clock</description>
<groupName>RTC</groupName>
<baseAddress>0x4003C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC</name>
<value>29</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>RTC control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SWRESET</name>
<description>Software reset control</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_IN_RESET</name>
<description>Not in reset. The RTC is not held in reset. This
bit must be cleared prior to configuring or initiating any
operation of the RTC.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN_RESET</name>
<description>In reset. The RTC is held in reset. All register
bits within the RTC will be forced to their reset value
except the OFD bit. This bit must be cleared before writing
to any register in the RTC - including writes to set any of
the other bits within this register. Do not attempt to write
to any bits of this register at the same time that the reset
bit is being cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFD</name>
<description>Oscillator fail detect status.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RUN</name>
<description>Run. The RTC oscillator is running properly.
Writing a 0 has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAIL</name>
<description>Fail. RTC oscillator fail detected. Clear this flag
after the following power-up. Writing a 1 clears this
bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARM1HZ</name>
<description>RTC 1 Hz timer alarm flag status.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_MATCH</name>
<description>No match. No match has occurred on the 1 Hz RTC
timer. Writing a 0 has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MATCH</name>
<description>Match. A match condition has occurred on the 1 Hz
RTC timer. This flag generates an RTC alarm interrupt
request RTC_ALARM which can also wake up the part from any
low power mode. Writing a 1 clears this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE1KHZ</name>
<description>RTC 1 kHz timer wake-up flag status.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RUN</name>
<description>Run. The RTC 1 kHz timer is running. Writing a 0
has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIME_OUT</name>
<description>Time-out. The 1 kHz high-resolution/wake-up timer
has timed out. This flag generates an RTC wake-up interrupt
request RTC-WAKE which can also wake up the part from any
low power mode. Writing a 1 clears this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARMDPD_EN</name>
<description>RTC 1 Hz timer alarm enable for Deep
power-down.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 Hz RTC timer will not
bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. A match on the 1 Hz RTC timer bring the
part out of Deep power-down mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKEDPD_EN</name>
<description>RTC 1 kHz timer wake-up enable for Deep
power-down.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 kHz RTC timer will not
bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. A match on the 1 kHz RTC timer bring the
part out of Deep power-down mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC1KHZ_EN</name>
<description>RTC 1 kHz clock enable. This bit can be set to 0 to
conserve power if the 1 kHz timer is not used. This bit has no
effect when the RTC is disabled (bit 7 of this register is
0).</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 kHz RTC timer will not
bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. The 1 kHz RTC timer is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC_EN</name>
<description>RTC enable.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. The RTC 1 Hz and 1 kHz clocks are shut
down and the RTC operation is disabled. This bit should be 0
when writing to load a value in the RTC counter
register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. The 1 Hz RTC clock is running and RTC
operation is enabled. This bit must be set to initiate
operation of the RTC. The first clock to the RTC counter
occurs 1 s after this bit is set. To also enable the
high-resolution, 1 kHz clock, set bit 6 in this
register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MATCH</name>
<description>RTC match register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATVAL</name>
<description>Contains the match value against which the 1 Hz RTC timer
will be compared to generate set the alarm flag RTC_ALARM and
generate an alarm interrupt/wake-up if enabled.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>RTC counter register</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>A read reflects the current value of the main, 1 Hz RTC
timer. A write loads a new initial value into the timer. The RTC
counter will count up continuously at a 1 Hz rate once the RTC
Software Reset is removed (by clearing bit 0 of the CTRL register).
Only write to this register when the RTC_EN bit in the RTC CTRL
Register is 0. The counter increments one second after the RTC_EN
bit is set.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>WAKE</name>
<description>RTC high-resolution/wake-up timer control register</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>A read reflects the current value of the
high-resolution/wake-up timer. A write pre-loads a start count value
into the wake-up timer and initializes a count-down sequence. Do not
write to this register while counting is in progress.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written..</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>INPUTMUX</name>
<description>Input multiplexing</description>
<groupName>INPUTMUX</groupName>
<baseAddress>0x40050000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>PINTSEL%s</name>
<description>Pin interrupt select register 0</description>
<addressOffset>0x0C0</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTPIN</name>
<description>Pin number select for pin interrupt or pattern match engine
input. (PIO0_0 to PIO1_31 correspond to numbers 0 to
63).</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-21</dimIndex>
<name>DMA_ITRIG_INMUX%s</name>
<description>Trigger select register for DMA channel 0</description>
<addressOffset>0x0E0</addressOffset>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INP</name>
<description>Trigger input number (decimal value) for DMA channel n (n =
0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B
interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0
Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0
8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 =
Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin
interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 =
DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA
output trigger mux 3</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>DMA_OTRIG_INMUX%s</name>
<description>DMA output trigger selection to become DMA trigger 16</description>
<addressOffset>0x140</addressOffset>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INP</name>
<description>DMA trigger output number (decimal value) for DMA channel n
(n = 0 to 19).</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>FREQMEAS_REF</name>
<description>Clock selection for frequency measurement function reference
clock</description>
<addressOffset>0x160</addressOffset>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKIN</name>
<description>Clock source number (decimal value) for frequency measure
function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC
oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 =
Main clock (see Section 4.5.21) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8
= PIO1_4</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>FREQMEAS_TARGET</name>
<description>Clock selection for frequency measurement function target
clock</description>
<addressOffset>0x164</addressOffset>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKIN</name>
<description>Clock source number (decimal value) for frequency measure
function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC
oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 =
Main clock (see Section 4.5.18) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8
= PIO1_4</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RIT</name>
<description>Repetitive Interrupt Timer</description>
<groupName>RIT</groupName>
<baseAddress>0x40070000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RIT</name>
<value>40</value>
</interrupt>
<registers>
<register>
<name>COMPVAL</name>
<description>Compare value LSB register. Holds the 32 LSBs of the compare
value.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RICOMP</name>
<description>Compare register. Holds the 32 LSBs of the value which is
compared to the counter.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MASK</name>
<description>Mask LSB register. This register holds the 32 LSB s of the mask
value. A 1 written to any bit will force the compare to be true for the
corresponding bit of the counter and compare register.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RIMASK</name>
<description>Mask register. This register holds the 32 LSBs of the mask
value. A one written to any bit overrides the result of the
comparison for the corresponding bit of the counter and compare
register (causes the comparison of the register bits to be always
true).</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Control register.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0xC</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RITINT</name>
<description>Interrupt flag</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>This bit is set to 1 by hardware whenever the
counter value equals the masked compare value specified by
the contents of RICOMPVAL and RIMASK registers. Writing a 1
to this bit will clear it to 0. Writing a 0 has no
effect.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>NOMTCH</name>
<description>The counter value does not equal the masked compare
value.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RITENCLR</name>
<description>Timer enable clear</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CLEAR</name>
<description>The timer will be cleared to 0 whenever the counter
value equals the masked compare value specified by the
contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
This will occur on the same clock that sets the interrupt
flag.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>NOCLEAR</name>
<description>The timer will not be cleared to 0.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RITENBR</name>
<description>Timer enable for debug</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>HALT</name>
<description>The timer is halted when the processor is halted
for debugging.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DEBUG</name>
<description>Debug has no effect on the timer
operation.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RITEN</name>
<description>Timer enable.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_ENABLED</name>
<description>Timer enabled. This can be overruled by a debug
halt if enabled in bit 2.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_DISABLED</name>
<description>Timer disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNTER</name>
<description>Counter LSB register. 32 LSBs of the counter.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RICOUNTER</name>
<description>32 LSBs of the up counter. Counts continuously unless RITEN
bit in CTRL register is cleared or debug mode is entered (if enabled
by the RITNEBR bit in RICTRL). Can be loaded to any value in
software.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>COMPVAL_H</name>
<description>Compare value MSB register. Holds the 16 MSBs of the compare
value.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RICOMP</name>
<description>Compare value MSB register. Holds the 16 MSBs of the value
which is compared to the counter.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>MASK_H</name>
<description>Mask MSB register. This register holds the 16 MSBs of the mask
value. A 1 written to any bit will force a compare on the corresponding bit
of the counter and compare register.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RIMASK</name>
<description>Mask register. This register holds the 16 MSBs of the mask
value. A one written to any bit overrides the result of the
comparison for the corresponding bit of the counter and compare
register (causes the comparison of the register bits to be always
true).</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNTER_H</name>
<description>Counter MSB register. 16 MSBs of the counter.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RICOUNTER</name>
<description>16 LSBs of the up counter. Counts continuously unless RITEN
bit in RICTRL register is cleared or debug mode is entered (if
enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in
software.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MRT</name>
<description>Multi-Rate Timer</description>
<groupName>MRT</groupName>
<baseAddress>0x40074000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MRT</name>
<value>10</value>
</interrupt>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>INTVAL%s</name>
<description>MRTn Time interval value register. This value is loaded into the
TIMER0 register.</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IVALUE</name>
<description>Time interval load value. This value is loaded into the
TIMERn register and the MRT channel n starts counting down from
IVALUE -1. If the timer is idle, writing a non-zero value to this
bit field starts the timer immediately. If the timer is running,
writing a zero to this bit field does the following: If LOAD = 1,
the timer stops immediately. If LOAD = 0, the timer stops at the end
of the time interval.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[30:24]</bitRange>
</field>
<field>
<name>LOAD</name>
<description>Determines how the timer interval value IVALUE -1 is loaded
into the TIMERn register. This bit is write-only. Reading this bit
always returns 0.</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_FORCE_LOAD</name>
<description>No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCE_LOAD</name>
<description>Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>TIMER%s</name>
<description>MRTn Timer register. This register reads the value of the
down-counter.</description>
<addressOffset>0x4</addressOffset>
<access>read-only</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Holds the current timer value of the down-counter. The
initial value of the TIMERn register is loaded as IVALUE - 1 from
the INTVALn register either at the end of the time interval or
immediately in the following cases: INTVALn register is updated in
the idle state. INTVALn register is updated with LOAD = 1. When the
timer is in idle state, reading this bit fields returns -1 (0x00FF
FFFF).</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CTRL%s</name>
<description>MRTn Control register. This register controls the MRTn
modes.</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTEN</name>
<description>Enable the TIMERn interrupt.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>TIMERn interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>TIMERn interrupt is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects timer mode.</description>
<bitRange>[2:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>REPEAT_INTERRUPT_MOD</name>
<description>Repeat interrupt mode.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_INTERRUPT_M</name>
<description>One-shot interrupt mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_STALL_MODE</name>
<description>One-shot stall mode.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>STAT%s</name>
<description>MRTn Status register.</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTFLAG</name>
<description>Monitors the interrupt flag.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is equivalent
to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>Indicates the state of TIMERn. This bit is
read-only.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IDLE_STATE</name>
<description>Idle state. TIMERn is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUNNING</name>
<description>Running. TIMERn is running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INUSE</name>
<description>Channel In Use flag. Operating details depend on the
MULTITASK bit in the MODCFG register, and affects the use of
IDLE_CH. </description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO</name>
<description>This channel is not in use.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>YES</name>
<description>This channel is in use.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>MODCFG</name>
<description>Module Configuration register. This register provides information
about this particular MRT instance, and allows choosing an overall mode for
the idle channel feature.</description>
<addressOffset>0xF0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NOC</name>
<description>Identifies the number of channels in this
MRT.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>NOB</name>
<description>Identifies the number of timer bits in this
MRT.</description>
<bitRange>[8:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[30:9]</bitRange>
</field>
<field>
<name>MULTITASK</name>
<description>Selects the operating mode for the INUSE flags and the
IDLE_CH register. See Idle channel register (IDLE_CH) for
details.</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>HARDWARE_STATUS_MODE</name>
<description>Hardware status mode. In this mode, the INUSE(n)
flags for all channels are reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MULTI_TASK_MODE</name>
<description>Multi-task mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IDLE_CH</name>
<description>Idle channel register. This register returns the number of the
first idle channel.</description>
<addressOffset>0xF4</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>CHAN</name>
<description>Idle channel. Reading the CHAN bits, returns the lowest
idle timer channel. The number is positioned such that it can be
used as an offset from the MRT base address in order to access the
registers for the allocated channel. If all timer channels are
running, CHAN = 0xF. See text above for more details.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQ_FLAG</name>
<description>Global interrupt flag register</description>
<addressOffset>0xF8</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GFLAG0</name>
<description>Monitors the interrupt flag of TIMER0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is equivalent
to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending because
TIMER0 has reached the end of the time interval. If the
INTEN bit in the CONTROL0 register is also set to 1, the
interrupt for timer channel 0 and the global interrupt are
raised. Writing a 1 to this bit clears the interrupt
request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFLAG1</name>
<description>Monitors the interrupt flag of TIMER1. See description of
channel 0.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>GFLAG2</name>
<description>Monitors the interrupt flag of TIMER2. See description of
channel 0.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>GFLAG3</name>
<description>Monitors the interrupt flag of TIMER3. See description of
channel 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ASYNCSYSCON</name>
<description>Asynchronous system configuration</description>
<groupName>ASYNCSYSCON</groupName>
<baseAddress>0x40080000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>AYSNCPRESETCTRL</name>
<description>Async peripheral reset control</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>USART0</name>
<description>USART0 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>USART1</name>
<description>USART1 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>USART2</name>
<description>USART2 reset control.0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>USART3</name>
<description>USART3 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>I2C0</name>
<description>I2C0 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2C1</name>
<description>I2C1 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>I2C2</name>
<description>I2C2 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>SPI0</name>
<description>SPI0 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>SPI1</name>
<description>SPI1 reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[12:11]</bitRange>
</field>
<field>
<name>TIMER0</name>
<description>Timer 0 reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>TIMER1</name>
<description>Timer 1 reset control. 0 = Clear reset to this function. 1
= Assert reset to this function.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>FRG0</name>
<description>FRG reset control. 0 = Clear reset to this function. 1 =
Assert reset to this function.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>AYSNCPRESETCTRLSET</name>
<description>Set bits in AYSNCPRESETCTRL</description>
<addressOffset>0x004</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>ARST_SET</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the AYSNCPRESETCTRL register, if they are implemented. Bits
that do not correspond to defined bits in AYSNCPRESETCTRL are
reserved and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>AYSNCPRESETCTRLCLR</name>
<description>Clear bits in AYSNCPRESETCTRL</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>ARST_CLR</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the AYSNCPRESETCTRL register, if they are implemented.
Bits that do not correspond to defined bits in AYSNCPRESETCTRL are
reserved and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCLKCTRL</name>
<description>Async peripheral clock control</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>USART0</name>
<description>Controls the clock for USART0. 0 = Disable; 1 =
Enable.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>USART1</name>
<description>Controls the clock for USART1. 0 = Disable; 1 =
Enable.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>USART2</name>
<description>Controls the clock for USART2. 0 = Disable; 1 =
Enable.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>USART3</name>
<description>Controls the clock for USART3. 0 = Disable; 1 =
Enable.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>I2C0</name>
<description>Controls the clock for I2C0. 0 = Disable; 1 =
Enable.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2C1</name>
<description>Controls the clock for I2C1. 0 = Disable; 1 =
Enable.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>I2C2</name>
<description>Controls the clock for I2C2. 0 = Disable; 1 =
Enable.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>SPI0</name>
<description>Controls the clock for SPI0. 0 = Disable; 1 =
Enable.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>SPI1</name>
<description>Controls the clock for SPI1. 0 = Disable; 1 =
Enable.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[12:11]</bitRange>
</field>
<field>
<name>TIMER0</name>
<description>Controls the clock for TIMER0. 0 = Disable; 1 =
Enable.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>TIMER1</name>
<description>Controls the clock for TIMER1. 0 = Disable; 1 =
Enable.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>FRG0</name>
<description>Controls the clock for the Fractional Rate Generator used
with the USARTs. 0 = Disable; 1 = Enable.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCLKCTRLSET</name>
<description>Set bits in ASYNCAPBCLKCTRL</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>ACLK_SET</name>
<description>Writing ones to this register sets the corresponding bit or
bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits
that do not correspond to defined bits in AYSNCPRESETCTRL are
reserved and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCLKCTRLCLR</name>
<description>Clear bits in ASYNCAPBCLKCTRL</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>ACLK_CLR</name>
<description>Writing ones to this register clears the corresponding bit
or bits in the ASYNCAPBCLKCTRL register, if they are implemented.
Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are
reserved and only zeroes should be written to them.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCLKSELA</name>
<description>Async APB clock source select A</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for asynchronous clock source selector
A</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCAPBCLKSELB</name>
<description>Async APB clock source select B</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for asynchronous clock source selector
B.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MAIN_CLOCK</name>
<description>Main clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>CLKIN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_PLL_OUTPUT</name>
<description>System PLL output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ASYNCAPBCLKSELA</name>
<description>ASYNCAPBCLKSELA. Clock selected by the
ASYNCAPBCLKSELA register.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>ASYNCCLKDIV</name>
<description>Async APB clock divider</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Asynchronous APB clock divider value. 0: Clock disabled. 1:
Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FRGCTRL</name>
<description>USART fractional rate generator control</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Denominator of the fractional divider. DIV is equal to the
programmed value +1. Always set to 0xFF to use with the fractional
baud rate generator.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>MULT</name>
<description>Numerator of the fractional divider. MULT is equal to the
programmed value.</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>BODCTRL</name>
<description>Brown-Out Detect control</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BODRSTLEV</name>
<description>BOD reset level</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_0_1</name>
<description>Level 0: 1.5 V</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_1_1</name>
<description>Level 1: 1.85 V</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2_2</name>
<description>Level 2: 2.0 V</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3_2</name>
<description>Level 3: 2.3 V</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODINTVAL</name>
<description>BOD interrupt level</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_0_2</name>
<description>Level 0: 2.05 V</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_1_2</name>
<description>Level 1: 2.45 V</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2_2</name>
<description>Level 2: 2.75 V</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3_3</name>
<description>Level 3: 3.05 V</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODRSTENA</name>
<description>BOD reset enable</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_RESET_FUNCTI</name>
<description>Disable reset function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_RESET_FUNCTIO</name>
<description>Enable reset function.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART0</name>
<description>USART0 </description>
<groupName>USART0</groupName>
<baseAddress>0x40084000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>USART Configuration register. Basic USART configuration settings
that typically are not changed during operation.</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>USART Enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART is disabled and the internal
state machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When Enable
is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore
available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART is enabled for
operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>DATALEN</name>
<description>Selects the data size for the USART.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>7_BIT_DATA_LENGTH</name>
<description>7 bit Data length.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_DATA_LENGTH</name>
<description>8 bit Data length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BIT_DATA_LENGTH</name>
<description>9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the CTL
register.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARITYSEL</name>
<description>Selects what type of parity is used by the
USART.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_PARITY</name>
<description>No parity.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_PARITY</name>
<description>Even parity. Adds a bit to each character such that
the number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be
even.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ODD_PARITY</name>
<description>Odd parity. Adds a bit to each character such that
the number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be
odd.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPLEN</name>
<description>Number of stop bits appended to transmitted data. Only a
single stop bit is required for received data.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_STOP_BIT</name>
<description>1 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP_BITS</name>
<description>2 stop bits. This setting should only be used for
asynchronous communication.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE32K</name>
<description>Selects standard or 32 kHz clocking mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART uses standard
clocking.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. USART uses the 32 kHz clock from the RTC
oscillator as the clock source to the BRG, and uses a
special bit clocking scheme.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINMODE</name>
<description>LIN break mode enable.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Break detect and generate is configured
for normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Break detect and generate is configured
for LIN bus operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS Enable. Determines whether CTS is used for flow
control. CTS can be from the input pin, or from the USART's own RTS
if loopback mode is enabled.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_FLOW_CONTROL</name>
<description>No flow control. The transmitter does not receive
any automatic flow control signal.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FLOW_CONTROL_ENABLED</name>
<description>Flow control enabled. The transmitter uses the CTS
input (or RTS output in loopback mode) for flow control
purposes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>SYNCEN</name>
<description>Selects synchronous or asynchronous
operation.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASYNCHRONOUS_MODE</name>
<description>Asynchronous mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCHRONOUS_MODE</name>
<description>Synchronous mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPOL</name>
<description>Selects the clock polarity and sampling edge of received
data in synchronous mode.</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Un_RXD is sampled on the falling edge
of SCLK.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Un_RXD is sampled on the rising edge
of SCLK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>SYNCMST</name>
<description>Synchronous mode Master select.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave. When synchronous mode is enabled, the USART
is a slave.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Master. When synchronous mode is enabled, the USART
is a master.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOP</name>
<description>Selects data loopback mode.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL_OPERATION</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOOPBACK_MODE</name>
<description>Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data from
the transmitter (Un_TXD) is connected internally to serial
input of the receive (Un_RXD). Un_TXD and Un_RTS activity
will also appear on external pins if these functions are
configured to appear on device pins. The receiver RTS signal
is also looped back to CTS and performs flow control if
enabled by CTSEN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOMODE</name>
<description>I/O output mode.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. USART output and input operate in
standard fashion.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IRDA</name>
<description>IrDA. USART output and input operate in IrDA
mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>OETA</name>
<description>Output Enable Turnaround time enable for RS-485
operation.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. If selected by OESEL, the Output Enable
signal deasserted at the end of the last stop bit of a
transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. If selected by OESEL, the Output Enable
signal remains asserted for one character time after the end
of the last stop bit of a transmission. OE will also remain
asserted if another transmit begins before it is
deasserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOADDR</name>
<description>Automatic Address matching enable.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more
than one address).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in the
ADDR register as the address to match.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OESEL</name>
<description>Output Enable Select.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The RTS signal is used as the standard
flow control function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RS_485</name>
<description>RS-485. The RTS signal configured to provide an
output enable signal to control an RS-485
transceiver.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OEPOL</name>
<description>Output Enable Polarity.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. If selected by OESEL, the output enable is
active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. If selected by OESEL, the output enable is
active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXPOL</name>
<description>Receive data polarity.</description>
<bitRange>[22:22]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The RX signal is used as it arrives from
the pin. This means that the RX rest value is 1, start bit
is 0, data is not inverted, and the stop bit is
1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The RX signal is inverted before being
used by the USART. This means that the RX rest value is 0,
start bit is 1, data is inverted, and the stop bit is
0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXPOL</name>
<description>Transmit data polarity.</description>
<bitRange>[23:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The TX signal is sent out without change.
This means that the TX rest value is 1, start bit is 0, data
is not inverted, and the stop bit is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The TX signal is inverted by the USART
before being sent out. This means that the TX rest value is
0, start bit is 1, data is inverted, and the stop bit is
0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTL</name>
<description>USART Control register. USART control settings that are more likely
to change during operation.</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXBRKEN</name>
<description>Break Enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL_OPERATION</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS_BREAK</name>
<description>Continuous break. Continuous break is sent
immediately when this bit is set, and remains until this bit
is cleared. A break may be sent without danger of corrupting
any currently transmitting character if the transmitter is
first disabled (TXDIS in CTL is set) and then waiting for
the transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADDRDET</name>
<description>Enable address detect mode.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART presents all incoming
data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART receiver ignores incoming data
that does not have the most significant bit of the data
(typically the 9th bit) = 1. When the data MSB bit = 1, the
receiver treats the incoming data normally, generating a
received data interrupt. Software can then check the data to
see if this is an address that should be handled. If it is,
the ADDRDET bit is cleared by software and further incoming
data is handled normally.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:3]</bitRange>
</field>
<field>
<name>TXDIS</name>
<description>Transmit Disable.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_DISABLED</name>
<description>Not disabled. USART transmitter is not
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow
control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CC</name>
<description>Continuous Clock generation. By default, SCLK is only
output while data is being transmitted in synchronous
mode.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CLOCK_ON_CHARACTER</name>
<description>Clock on character. In synchronous mode, SCLK
cycles only when characters are being sent on Un_TXD or to
complete a character that is being received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS_CLOCK</name>
<description>Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on
Un_TXD).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCCONRX</name>
<description>Clear Continuous Clock.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. No effect on the CC bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_CLEAR</name>
<description>Auto-clear. The CC bit is automatically cleared
when a complete character has been received. This bit is
cleared at the same time.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>AUTOBAUD</name>
<description>Autobaud enable.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART is in normal operating
mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. USART is in autobaud mode. This bit should
only be set when the USART receiver is idle. The first start
bit of RX is measured and used the update the BRG register
to match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an
AERR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>USART Status register. The complete status value can be read here.
Writing ones clears some bits in the register. Some bits can be cleared by
writing a 1 to them.</description>
<addressOffset>0x08</addressOffset>
<access>read-write</access>
<resetValue>0x0E</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag. When 1, indicates that data is
available to be read from the receiver buffer. Cleared after a read
of the RXDAT or RXDATSTAT registers.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RXIDLE</name>
<description>Receiver Idle. When 0, indicates that the receiver is
currently in the process of receiving data. When 1, indicates that
the receiver is not currently in the process of receiving
data.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag. When 1, this bit indicates that
data may be written to the transmit buffer. Previous data may still
be in the process of being transmitted. Cleared when data is written
to TXDAT. Set when the data is moved from the transmit buffer to the
transmit shift register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter Idle. When 0, indicates that the transmitter is
currently in the process of sending data.When 1, indicate that the
transmitter is not currently in the process of sending
data.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CTS</name>
<description>This bit reflects the current state of the CTS signal,
regardless of the setting of the CTSEN bit in the CFG register. This
will be the value of the CTS input pin unless loopback mode is
enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state is detected for
the CTS flag above. This bit is cleared by software.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISSTAT</name>
<description>Transmitter Disabled Status flag. When 1, this bit
indicates that the USART transmitter is fully idle after being
disabled via the TXDIS bit in the CFG register (TXDIS =
1).</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag. This flag is set when a new
character is received while the receiver buffer is still in use. If
this occurs, the newly received character in the shift register is
lost.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RXBRK</name>
<description>Received Break. This bit reflects the current state of the
receiver break detection logic. It is set when the Un_RXD pin
remains low for 16 bit times. Note that FRAMERRINT will also be set
when this condition occurs because the stop bit(s) for the character
would be missing. RXBRK is cleared when the Un_RXD pin goes
high.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver
break detection occurs. Cleared by software.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver
input. Its purpose is primarily to allow wake-up from Deep-sleep or
Power-down mode immediately when a start is detected. Cleared by
software.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag. This flag is set when a
character is received with a missing stop bit at the expected
location. This could be an indication of a baud rate or
configuration mismatch with the transmitting source.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag. This flag is set when a parity
error is detected in a received character..</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag. Three samples of received
data are taken in order to determine the value of each received data
bit, except in synchronous mode. This acts as a noise filter if one
sample disagrees. This flag is set when a received data bit contains
one disagreeing sample. This could indicate line noise, a baud rate
or character format mismatch, or loss of synchronization during data
reception.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERR</name>
<description>Auto baud Error. An auto baud error can occur if the BRG
counts to its limit before the end of the start bit that is being
measured, essentially an auto baud time-out.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt Enable read and Set register. Contains an individual
interrupt enable bit for each potential USART interrupt. A complete value
may be read from this register. Writing a 1 to any implemented bit position
causes that bit to be set.</description>
<addressOffset>0x0C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>When 1, enables an interrupt when there is a received
character available to be read from the RXDAT
register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDYEN</name>
<description>When 1, enables an interrupt when the TXDAT register is
available to take another character to transmit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLEEN</name>
<description>When 1, enables an interrupt when the transmitter becomes
idle (TXIDLE = 1).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTSEN</name>
<description>When 1, enables an interrupt when there is a change in the
state of the CTS input.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISEN</name>
<description>When 1, enables an interrupt when the transmitter is fully
disabled as indicated by the TXDISINT flag in STAT. See description
of the TXDISINT bit for details.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNEN</name>
<description>When 1, enables an interrupt when an overrun error
occurred.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRKEN</name>
<description>When 1, enables an interrupt when a change of state has
occurred in the detection of a received break condition (break
condition asserted or deasserted).</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>STARTEN</name>
<description>When 1, enables an interrupt when a received start bit has
been detected.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERREN</name>
<description>When 1, enables an interrupt when a framing error has been
detected.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERREN</name>
<description>When 1, enables an interrupt when a parity error has been
detected.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEEN</name>
<description>When 1, enables an interrupt when noise is detected. See
description of the RXNOISEINT bit in Table 311.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERREN</name>
<description>When 1, enables an interrupt when an auto baud error
occurs.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt Enable Clear register. Allows clearing any combination of
bits in the INTENSET register. Writing a 1 to any implemented bit position
causes the corresponding bit to be cleared.</description>
<addressOffset>0x10</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTSCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRKCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>STARTCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET
register.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>RXDAT</name>
<description>Receiver Data register. Contains the last character
received.</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>DATA</name>
<description>The USART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the USART
configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>RXDATSTAT</name>
<description>Receiver Data with Status register. Combines the last character
received with the current USART receive status. Allows DMA or software to
recover incoming data and status together.</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RXDATA</name>
<description>The USART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the USART
configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[12:9]</bitRange>
</field>
<field>
<name>FRAMERR</name>
<description>Framing Error status flag. This bit is valid when there is
a character to be read in the RXDAT register and reflects the status
of that character. This bit will set when the character in RXDAT was
received with a missing stop bit at the expected location. This
could be an indication of a baud rate or configuration mismatch with
the transmitting source.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERR</name>
<description>Parity Error status flag. This bit is valid when there is a
character to be read in the RXDAT register and reflects the status
of that character. This bit will be set when a parity error is
detected in a received character.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISE</name>
<description>Received Noise flag. See description of the RxNoiseInt bit
in Table 311.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>TXDAT</name>
<description>Transmit Data register. Data to be transmitted is written
here.</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Writing to the USART Transmit Data Register causes the data
to be transmitted as soon as the transmit shift register is
available and any conditions for transmitting data are met: CTS low
(if CTSEN bit = 1), TXDIS bit = 0.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Only zero should be written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>BRG</name>
<description>Baud Rate Generator register. 16-bit integer baud rate divisor
value.</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BRGVAL</name>
<description>This value is used to divide the USART input clock to
determine the baud rate, based on the input clock from the FRG. 0 =
The FRG clock is used directly by the USART function. 1 = The FRG
clock is divided by 2 before use by the USART function. 2 = The FRG
clock is divided by 3 before use by the USART function. ... 0xFFFF =
The FRG clock is divided by 65,536 before use by the USART
function.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status register. Reflects interrupts that are currently
enabled.</description>
<addressOffset>0x24</addressOffset>
<access>read-only</access>
<resetValue>0x05</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter Idle status.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state of the CTS input
is detected.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISINT</name>
<description>Transmitter Disabled Interrupt flag.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver
break detection occurs.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver
input.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERRINT</name>
<description>Auto baud Error Interrupt flag.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Oversample selection register for asynchronous
communication.</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OSRVAL</name>
<description>Oversample Selection Value. 0 to 3 = not supported 0x4 = 5
peripheral clocks are used to transmit and receive each data bit.
0x5 = 6 peripheral clocks are used to transmit and receive each data
bit. ... 0xF= 16 peripheral clocks are used to transmit and receive
each data bit.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description>Address register for automatic address matching.</description>
<addressOffset>0x2C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDRESS</name>
<description>8-bit address used with automatic address matching. Used
when address detection is enabled (ADDRDET in CTL = 1) and automatic
address matching is enabled (AUTOADDR in CFG = 1).</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART1</name>
<description>USART1</description>
<baseAddress>0x40088000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART1</name>
<value>18</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART2</name>
<description>USART2</description>
<baseAddress>0x4008C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART2</name>
<value>19</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART3</name>
<description>USART3</description>
<baseAddress>0x40090000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART3</name>
<value>20</value>
</interrupt>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>I2C-bus interface 0</description>
<groupName>I2C0</groupName>
<baseAddress>0x40094000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>Configuration for shared functions.</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTEN</name>
<description>Master Enable. When disabled, configurations settings for
the Master function are not changed, but the Master function is
internally reset.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C Master function is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C Master function is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVEN</name>
<description>Slave Enable. When disabled, configurations settings for
the Slave function are not changed, but the Slave function is
internally reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C slave function is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C slave function is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONEN</name>
<description>Monitor Enable. When disabled, configurations settings for
the Monitor function are not changed, but the Monitor function is
internally reset.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C monitor function is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C monitor function is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMEOUTEN</name>
<description>I2C bus Time-out Enable. When disabled, the time-out
function is internally reset.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Time-out function is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Time-out function is enabled. Both types
of time-out flags will be generated and will cause
interrupts if they are enabled. Typically, only one time-out
will be used in a system.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONCLKSTR</name>
<description>Monitor function Clock Stretching.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The monitor function will not perform
clock stretching. Software or DMA may not always be able to
read data provided by the monitor function before it is
overwritten. This mode may be used when non-invasive
monitoring is critical.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The monitor function will perform clock
stretching in order to ensure that software or DMA can read
all incoming data supplied by the monitor
function.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSCAPABLE</name>
<description>High-speed mode Capable enable. Since High Speed mode
alters the way I2C pins drive and filter, as well as the timing for
certain I2C signalling, enabling High-speed mode applies to all
functions: master, slave, and monitor.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FAST_MODE_PLUS</name>
<description>Fast-mode plus. The I2C block will support
Standard-mode, Fast-mode, and Fast-mode Plus, to the extent
that the pin electronics support these modes. Any changes
that need to be made to the pin controls, such as changing
the drive strength or filtering, must be made by software
via the IOCON register associated with each I2C
pin,</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_SPEED</name>
<description>High-speed. In addition to Standard-mode,
Fast-mode, and Fast-mode Plus, the I 2C block will support
High-speed mode to the extent that the pin electronics
support these modes. See Section 23.7.1.2 for more
information.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>Status register for Master, Slave, and Monitor
functions.</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0x0801</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTPENDING</name>
<description>Master Pending. Indicates that the Master is waiting to
continue communication on the I2C-bus (pending) or is idle. When the
master is pending, the MSTSTATE bits indicate what type of software
service if any the master expects. This flag will cause an interrupt
when set if, enabled via the INTENSET register. The MSTPENDING flag
is not set when the DMA is handling an event (if the MSTDMA bit in
the MSTCTL register is set). If the master is in the idle state, and
no communication is needed, mask this interrupt.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>In progress. Communication is in progress and the
Master function is busy and cannot currently accept a
command.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. The Master function needs software service
or is in the idle state. If the master is not in the idle
state, it is waiting to receive or transmit data or the NACK
bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTATE</name>
<description>Master State code. The master state code reflects the
master state when the MSTPENDING bit is set, that is the master is
pending or in the idle state. Each value of this field indicates a
specific required service for the Master function. All other values
are reserved. See Table 346 for details of state values and
appropriate responses.</description>
<bitRange>[3:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IDLE</name>
<description>Idle. The Master function is available to be used
for a new transaction.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVE_READY</name>
<description>Receive ready. Received data available (Master
Receiver mode). Address plus Read was previously sent and
Acknowledged by slave.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT_READY</name>
<description>Transmit ready. Data can be transmitted (Master
Transmitter mode). Address plus Write was previously sent
and Acknowledged by slave.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK_ADDRESS</name>
<description>NACK Address. Slave NACKed address.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK_DATA</name>
<description>NACK Data. Slave NACKed transmitted
data.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTARBLOSS</name>
<description>Master Arbitration Loss flag. This flag can be cleared by
software writing a 1 to this bit. It is also cleared automatically a
1 is written to MSTCONTINUE.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_ARBITRATION_LOSS</name>
<description>No Arbitration Loss has occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ARBITRATION_LOSS</name>
<description>Arbitration loss. The Master function has
experienced an Arbitration Loss. At this point, the Master
function has already stopped driving the bus and gone to an
idle state. Software can respond by doing nothing, or by
sending a Start in order to attempt to gain control of the
bus when it next becomes idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MSTSTSTPERR</name>
<description>Master Start/Stop Error flag. This flag can be cleared by
software writing a 1 to this bit. It is also cleared automatically a
1 is written to MSTCONTINUE.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_STARTSTOP_ERROR</name>
<description>No Start/Stop Error has occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_MASTER_FUNCTION</name>
<description>The Master function has experienced a Start/Stop
Error. A Start or Stop was detected at a time when it is not
allowed by the I2C specification. The Master interface has
stopped driving the bus and gone to an idle state, no action
is required. A request for a Start could be made, or
software could attempt to insure that the bus has not
stalled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SLVPENDING</name>
<description>Slave Pending. Indicates that the Slave function is waiting
to continue communication on the I2C-bus and needs software service.
This flag will cause an interrupt when set if enabled via INTENSET.
The SLVPENDING flag is not set when the DMA is handling an event (if
the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag
is read-only and is automatically cleared when a 1 is written to the
SLVCONTINUE bit in the MSTCTL register. The point in time when
SlvPending is set depends on whether the I2C block is in HSCAPABLE
mode. See Section 23.7.1.2.2. When the I2C block is configured to be
HSCAPABLE, HS master codes are detected automatically. Due to the
requirements of the HS I2C specification, slave addresses must also
be detected automatically, since the address must be acknowledged
before the clock can be stretched.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>In progress. The Slave function does not currently
need service.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. The Slave function needs service.
Information on what is needed can be found in the adjacent
SLVSTATE field.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSTATE</name>
<description>Slave State code. Each value of this field indicates a
specific required service for the Slave function. All other values
are reserved. See Table 347 for state values and
actions.</description>
<bitRange>[10:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLAVE_ADDRESS</name>
<description>Slave address. Address plus R/W received. At least
one of the four slave addresses has been matched by
hardware.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE_RECEIVE</name>
<description>Slave receive. Received data is available (Slave
Receiver mode).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE_TRANSMIT</name>
<description>Slave transmit. Data can be transmitted (Slave
Transmitter mode).</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVNOTSTR</name>
<description>Slave Not Stretching. Indicates when the slave function is
stretching the I2C clock. This is needed in order to gracefully
invoke Deep Sleep or Power-down modes during slave operation. This
read-only flag reflects the slave function status in real
time.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STRETCHING</name>
<description>Stretching. The slave function is currently
stretching the I2C bus clock. Deep-Sleep or Power-down mode
cannot be entered at this time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_STRETCHING</name>
<description>Not stretching. The slave function is not currently
stretching the I 2C bus clock. Deep-sleep or Power-down mode
could be entered at this time.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVIDX</name>
<description>Slave address match Index. This field is valid when the I2C
slave function has been selected by receiving an address that
matches one of the slave addresses defined by any enabled slave
address registers, and provides an identification of the address
that was matched. It is possible that more than one address could be
matched, but only one match can be reported here.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ADDRESS_0</name>
<description>Address 0. Slave address 0 was
matched.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS_1</name>
<description>Address 1. Slave address 1 was
matched.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS_2</name>
<description>Address 2. Slave address 2 was
matched.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS_3</name>
<description>Address 3. Slave address 3 was
matched.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSEL</name>
<description>Slave selected flag. SLVSEL is set after an address match
when software tells the Slave function to acknowledge the address.
It is cleared when another address cycle presents an address that
does not match an enabled address on the Slave function, when slave
software decides to NACK a matched address, or when there is a Stop
detected on the bus. SLVSEL is not cleared if software NACKs
data.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_SELECTED</name>
<description>Not selected. The Slave function is not currently
selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SELECTED</name>
<description>Selected. The Slave function is currently
selected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVDESEL</name>
<description>Slave Deselected flag. This flag will cause an interrupt
when set if enabled via INTENSET. This flag can be cleared by
writing a 1 to this bit.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_DESELECTED</name>
<description>Not deselected. The Slave function has not become
deselected. This does not mean that it is currently
selected. That information can be found in the SLVSEL
flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DESELECTED</name>
<description>Deselected. The Slave function has become
deselected. This is specifically caused by the SLVSEL flag
changing from 1 to 0. See the description of SLVSEL for
details on when that event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRDY</name>
<description>Monitor Ready. This flag is cleared when the MONRXDAT
register is read.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_DATA</name>
<description>No data. The Monitor function does not currently
have data available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_WAITING</name>
<description>Data waiting. The Monitor function has data waiting
to be read.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONOV</name>
<description>Monitor Overflow flag.</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_OVERRUN</name>
<description>No overrun. Monitor data has not
overrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OVERRUN</name>
<description>Overrun. A Monitor data overrun has occurred. This
can only happen when Monitor clock stretching not enabled
via the MONCLKSTR bit in the CFG register. Writing 1 to this
bit clears the flag.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONACTIVE</name>
<description>Monitor Active flag. Indicates when the Monitor function
considers the I 2C bus to be active. Active is defined here as when
some Master is on the bus: a bus Start has occurred more recently
than a bus Stop.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. The Monitor function considers the I2C
bus to be inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Active. The Monitor function considers the I2C bus
to be active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONIDLE</name>
<description>Monitor Idle flag. This flag is set when the Monitor
function sees the I2C bus change from active to inactive. This can
be used by software to decide when to process data accumulated by
the Monitor function. This flag will cause an interrupt when set if
enabled via the INTENSET register. The flag can be cleared by
writing a 1 to this bit.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_IDLE</name>
<description>Not idle. The I2C bus is not idle, or this flag has
been cleared by software.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDLE</name>
<description>Idle. The I2C bus has gone idle at least once since
the last time this flag was cleared by
software.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:20]</bitRange>
</field>
<field>
<name>EVENTTIMEOUT</name>
<description>Event Time-out Interrupt flag. Indicates when the time
between events has been longer than the time specified by the
TIMEOUT register. Events include Start, Stop, and clock edges. The
flag is cleared by writing a 1 to this bit. No time-out is created
when the I2C-bus is idle.</description>
<bitRange>[24:24]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_TIME_OUT</name>
<description>No time-out. I2C bus events have not caused a
time-out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_TIME_OUT</name>
<description>Event time-out. The time between I2C bus events has
been longer than the time specified by the I2C TIMEOUT
register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCLTIMEOUT</name>
<description>SCL Time-out Interrupt flag. Indicates when SCL has
remained low longer than the time specific by the TIMEOUT register.
The flag is cleared by writing a 1 to this bit.</description>
<bitRange>[25:25]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_TIME_OUT</name>
<description>No time-out. SCL low time has not caused a
time-out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIME_OUT</name>
<description>Time-out. SCL low time has caused a
time-out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt Enable Set and read register.</description>
<addressOffset>0x08</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTPENDINGEN</name>
<description>Master Pending interrupt Enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstPending interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstPending interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:1]</bitRange>
</field>
<field>
<name>MSTARBLOSSEN</name>
<description>Master Arbitration Loss interrupt Enable.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstArbLoss interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstArbLoss interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MSTSTSTPERREN</name>
<description>Master Start/Stop Error interrupt Enable.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstStStpErr interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstStStpErr interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SLVPENDINGEN</name>
<description>Slave Pending interrupt Enable.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvPending interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvPending interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>SLVNOTSTREN</name>
<description>Slave Not Stretching interrupt Enable.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvNotStr interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvNotStr interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>SLVDESELEN</name>
<description>Slave Deselect interrupt Enable.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvDeSel interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvDeSel interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRDYEN</name>
<description>Monitor data Ready interrupt Enable.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonRdy interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonRdy interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONOVEN</name>
<description>Monitor Overrun interrupt Enable.</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonOv interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonOv interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MONIDLEEN</name>
<description>Monitor Idle interrupt Enable.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonIdle interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonIdle interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:20]</bitRange>
</field>
<field>
<name>EVENTTIMEOUTEN</name>
<description>Event time-out interrupt Enable.</description>
<bitRange>[24:24]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Event time-out interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Event time-out interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCLTIMEOUTEN</name>
<description>SCL time-out interrupt Enable.</description>
<bitRange>[25:25]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SCL time-out interrupt is
disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SCL time-out interrupt is
enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt Enable Clear register.</description>
<addressOffset>0x0C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>MSTPENDINGCLR</name>
<description>Master Pending interrupt clear. Writing 1 to this bit
clears the corresponding bit in the INTENSET register if
implemented.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[3:1]</bitRange>
</field>
<field>
<name>MSTARBLOSSCLR</name>
<description>Master Arbitration Loss interrupt clear.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MSTSTSTPERRCLR</name>
<description>Master Start/Stop Error interrupt clear.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SLVPENDINGCLR</name>
<description>Slave Pending interrupt clear.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>SLVNOTSTRCLR</name>
<description>Slave Not Stretching interrupt clear.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>SLVDESELCLR</name>
<description>Slave Deselect interrupt clear.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MONRDYCLR</name>
<description>Monitor data Ready interrupt clear.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MONOVCLR</name>
<description>Monitor Overrun interrupt clear.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MONIDLECLR</name>
<description>Monitor Idle interrupt clear.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:20]</bitRange>
</field>
<field>
<name>EVENTTIMEOUTCLR</name>
<description>Event time-out interrupt clear.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SCLTIMEOUTCLR</name>
<description>SCL time-out interrupt clear.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>Time-out value register.</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TOMIN</name>
<description>Time-out time value, bottom four bits. These are hard-wired
to 0xF. This gives a minimum time-out of 16 I2C function clocks and
also a time-out resolution of 16 I2C function clocks.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>TO</name>
<description>Time-out time value. Specifies the time-out interval value
in increments of 16 I2C function clocks, as defined by the CLKDIV
register. To change this value while I 2C is in operation, disable
all time-outs, write a new value to TIMEOUT, then re-enable
time-outs. 0x000 = A time-out will occur after 16 counts of the I2C
function clock. 0x001 = A time-out will occur after 32 counts of the
I2C function clock. ... 0xFFF = A time-out will occur after 65,536
counts of the I2C function clock.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Clock pre-divider for the entire I2C block. This determines what
time increments are used for the MSTTIME register, and controls some timing
of the Slave function.</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVVAL</name>
<description>This field controls how the clock (PCLK) is used by the I2C
functions that need an internal clock in order to operate. 0x0000 =
PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2
before use. 0x0002 = PCLK is divided by 3 before use. ... 0xFFFF =
PCLK is divided by 65,536 before use.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt Status register for Master, Slave, and Monitor
functions.</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTPENDING</name>
<description>Master Pending.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:1]</bitRange>
</field>
<field>
<name>MSTARBLOSS</name>
<description>Master Arbitration Loss flag.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MSTSTSTPERR</name>
<description>Master Start/Stop Error flag.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SLVPENDING</name>
<description>Slave Pending.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>SLVNOTSTR</name>
<description>Slave Not Stretching status.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>SLVDESEL</name>
<description>Slave Deselected flag.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MONRDY</name>
<description>Monitor Ready.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MONOV</name>
<description>Monitor Overflow flag.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MONIDLE</name>
<description>Monitor Idle flag.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:20]</bitRange>
</field>
<field>
<name>EVENTTIMEOUT</name>
<description>Event time-out Interrupt flag.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SCLTIMEOUT</name>
<description>SCL time-out Interrupt flag.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>MSTCTL</name>
<description>Master control register.</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTCONTINUE</name>
<description>Master Continue. This bit is write-only.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUE</name>
<description>Continue. Informs the Master function to continue
to the next operation. This must done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTART</name>
<description>Master Start control. This bit is write-only.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start. A Start will be generated on the I2C bus at
the next allowed time.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTOP</name>
<description>Master Stop control. This bit is write-only.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP</name>
<description>Stop. A Stop will be generated on the I2C bus at
the next allowed time, preceded by a NACK to the slave if
the master is receiving data from the slave (Master Receiver
mode).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTDMA</name>
<description>Master DMA enable. Data operations of the I2C can be
performed with DMA. Protocol type operations such as Start, address,
Stop, and address match must always be done with software, typically
via an interrupt. When a DMA data transfer is complete, MSTDMA must
be cleared prior to beginning the next operation, typically a Start
or Stop.This bit is read/write.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. No DMA requests are generated for master
operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. A DMA request is generated for I2C master
data operations. When this I2C master is generating
Acknowledge bits in Master Receiver mode, the acknowledge is
generated automatically.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>MSTTIME</name>
<description>Master timing configuration.</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x77</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTSCLLOW</name>
<description>Master SCL Low time. Specifies the minimum low time that
will be asserted by this master on SCL. Other devices on the bus
(masters or slaves) could lengthen this time. This corresponds to
the parameter tLOW in the I2C bus specification. I2C bus
specification parameters tBUF and t SU;STA have the same values and
are also controlled by MSTSCLLOW.</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>2_CLOCKS</name>
<description>2 clocks. Minimum SCL low time is 2 clocks of the
I2C clock pre-divider.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCKS</name>
<description>3 clocks. Minimum SCL low time is 3 clocks of the
I2C clock pre-divider.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_CLOCKS</name>
<description>4 clocks. Minimum SCL low time is 4 clocks of the
I2C clock pre-divider.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>5_CLOCKS</name>
<description>5 clocks. Minimum SCL low time is 5 clocks of the
I2C clock pre-divider.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>6_CLOCKS</name>
<description>6 clocks. Minimum SCL low time is 6 clocks of the
I2C clock pre-divider.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>7_CLOCKS</name>
<description>7 clocks. Minimum SCL low time is 7 clocks of the
I2C clock pre-divider.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>8_CLOCKS</name>
<description>8 clocks. Minimum SCL low time is 8 clocks of the
I2C clock pre-divider.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>9_CLOCKS</name>
<description>9 clocks. Minimum SCL low time is 9 clocks of the
I2C clock pre-divider.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MSTSCLHIGH</name>
<description>Master SCL High time. Specifies the minimum high time that
will be asserted by this master on SCL. Other masters in a
multi-master system could shorten this time. This corresponds to the
parameter tHIGH in the I2C bus specification. I2C bus specification
parameters tSU;STO and tHD;STA have the same values and are also
controlled by MSTSCLHIGH.</description>
<bitRange>[6:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>2_CLOCKS</name>
<description>2 clocks. Minimum SCL high time is 2 clock of the
I2C clock pre-divider.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCKS</name>
<description>3 clocks. Minimum SCL high time is 3 clocks of the
I2C clock pre-divider .</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_CLOCKS</name>
<description>4 clocks. Minimum SCL high time is 4 clock of the
I2C clock pre-divider.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>5_CLOCKS</name>
<description>5 clocks. Minimum SCL high time is 5 clock of the
I2C clock pre-divider.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>6_CLOCKS</name>
<description>6 clocks. Minimum SCL high time is 6 clock of the
I2C clock pre-divider.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>7_CLOCKS</name>
<description>7 clocks. Minimum SCL high time is 7 clock of the
I2C clock pre-divider.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>8_CLOCKS</name>
<description>8 clocks. Minimum SCL high time is 8 clock of the
I2C clock pre-divider.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>9_CLOCKS</name>
<description>9 clocks. Minimum SCL high time is 9 clocks of the
I2C clock pre-divider.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>MSTDAT</name>
<description>Combined Master receiver and transmitter data
register.</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Master function data register. Read: read the most recently
received data for the Master function. Write: transmit data using
the Master function.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SLVCTL</name>
<description>Slave control register.</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SLVCONTINUE</name>
<description>Slave Continue.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUE</name>
<description>Continue. Informs the Slave function to continue to
the next operation. This must be done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVNACK</name>
<description>Slave NACK.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK</name>
<description>NACK. Causes the Slave function to NACK the master
when the slave is receiving data from the master (Slave
Receiver mode).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVDMA</name>
<description>Slave DMA enable.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No DMA requests are issued for Slave mode
operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. DMA requests are issued for I2C slave data
transmission and reception.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>SLVDAT</name>
<description>Combined Slave receiver and transmitter data
register.</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Slave function data register. Read: read the most recently
received data for the Slave function. Write: transmit data using the
Slave function.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>SLVADR%s</name>
<description>Slave address 0.</description>
<addressOffset>0x48</addressOffset>
<access>read-write</access>
<resetValue>0x01</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SADISABLE</name>
<description>Slave Address n Disable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Slave Address n is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IGNORED_SLAVE_ADDRES</name>
<description>Ignored Slave Address n is ignored.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVADR</name>
<description>Slave Address. Seven bit slave address that is compared to
received addresses if enabled.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SLVQUAL0</name>
<description>Slave Qualification for address 0.</description>
<addressOffset>0x58</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>QUALMODE0</name>
<description>Qualify mode for slave address 0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MASK</name>
<description>Mask. The SLVQUAL0 field is used as a logical mask
for matching address 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTEND</name>
<description>Extend. The SLVQUAL0 field is used to extend
address 0 matching in a range of addresses.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVQUAL0</name>
<description>Slave address Qualifier for address 0. A value of 0 causes
the address in SLVADR0 to be used as-is, assuming that it is
enabled. If QUALMODE0 = 0, any bit in this field which is set to 1
will cause an automatic match of the corresponding bit of the
received address when it is compared to the SLVADR0 register. If
QUALMODE0 = 1, an address range is matched for address 0. This range
extends from the value defined by SLVADR0 to the address defined by
SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address
&lt;= SLVQUAL0[7:1]).</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MONRXDAT</name>
<description>Monitor receiver data register.</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MONRXDAT</name>
<description>Monitor function Receiver Data. This reflects every data
byte that passes on the I2C pins.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>MONSTART</name>
<description>Monitor Received Start.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_START_DETECTED</name>
<description>No start detected. The monitor function has not
detected a Start event on the I2C bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_DETECTED</name>
<description>Start detected. The monitor function has detected a
Start event on the I2C bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRESTART</name>
<description>Monitor Received Repeated Start.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_REPEATED_START_DE</name>
<description>No repeated start detected. The monitor function
has not detected a Repeated Start event on the I2C
bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATED_START_DETEC</name>
<description>Repeated start detected. The monitor function has
detected a Repeated Start event on the I2C
bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONNACK</name>
<description>Monitor Received NACK.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ACKNOWLEDGED</name>
<description>Acknowledged. The data currently being provided by
the monitor function was acknowledged by at least one master
or slave receiver.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ACKNOWLEDGED</name>
<description>Not acknowledged. The data currently being provided
by the monitor function was not acknowledged by any
receiver.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C0">
<name>I2C1</name>
<description>I2C-bus interface 1</description>
<baseAddress>0x40098000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1</name>
<value>22</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="I2C0">
<name>I2C2</name>
<description>I2C-bus interface 2</description>
<baseAddress>0x4009C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C2</name>
<value>23</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>SPI0</description>
<groupName>SPI0</groupName>
<baseAddress>0x400A4000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>SPI Configuration register</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>SPI enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SPI is disabled and the internal
state machine and counters are reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SPI is enabled for
operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MASTER</name>
<description>Master mode select.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLAVE_MODE</name>
<description>Slave mode. The SPI will operate in slave mode.
SCK, MOSI, and the SSEL signals are inputs, MISO is an
output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER_MODE</name>
<description>Master mode. The SPI will operate in master mode.
SCK, MOSI, and the SSEL signals are outputs, MISO is an
input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSBF</name>
<description>LSB First mode enable.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. Data is transmitted and received in
standard MSB first order.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REVERSE</name>
<description>Reverse. Data is transmitted and received in
reverse order (LSB first).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase select.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CHANGE</name>
<description>Change. The SPI captures serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is changed on the following
edge.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE</name>
<description>Capture. The SPI changes serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is captured on the following
edge.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity select.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. The rest state of the clock (between
transfers) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The rest state of the clock (between
transfers) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>LOOP</name>
<description>Loopback mode enable. Loopback mode applies only to Master
mode, and connects transmit and receive data connected together to
allow simple software testing.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL0</name>
<description>SSEL0 Polarity select.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL0 pin is active low. The value in the
SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is not inverted relative to the
pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL0 pin is active high. The value in
the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is inverted relative to the
pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL1</name>
<description>SSEL1 Polarity select.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL1 pin is active low. The value in the
SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is not inverted relative to the
pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL1 pin is active high. The value in
the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is inverted relative to the
pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL2</name>
<description>SSEL2 Polarity select.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL2 pin is active low. The value in the
SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is not inverted relative to the
pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL2 pin is active high. The value in
the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is inverted relative to the
pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL3</name>
<description>SSEL3 Polarity select.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL3 pin is active low. The value in the
SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is not inverted relative to the
pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL3 pin is active high. The value in
the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is inverted relative to the
pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>DLY</name>
<description>SPI Delay register</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRE_DELAY</name>
<description>Controls the amount of time between SSEL assertion and the
beginning of a data transfer. There is always one SPI clock time
between SSEL assertion and the first clock edge. This is not
considered part of the pre-delay. 0x0 = No additional time is
inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
times are inserted. ... 0xF = 15 SPI clock times are
inserted.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>POST_DELAY</name>
<description>Controls the amount of time between the end of a data
transfer and SSEL deassertion. 0x0 = No additional time is inserted.
0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are
inserted. ... 0xF = 15 SPI clock times are inserted.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>FRAME_DELAY</name>
<description>If the EOF flag is set, controls the minimum amount of time
between the current frame and the next frame (or SSEL deassertion if
EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time
is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI
clock times are inserted.</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>TRANSFER_DELAY</name>
<description>Controls the minimum amount of time that the SSEL is
deasserted between transfers. 0x0 = The minimum time that SSEL is
deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum
time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum
time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The
minimum time that SSEL is deasserted is 16 SPI clock
times.</description>
<bitRange>[15:12]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>SPI Status. Some status flags can be cleared by writing a 1 to that
bit position</description>
<addressOffset>0x08</addressOffset>
<access>read-write</access>
<resetValue>0x0102</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag. When 1, indicates that data is
available to be read from the receiver buffer. Cleared after a read
of the RXDAT register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag. When 1, this bit indicates that
data may be written to the transmit buffer. Previous data may still
be in the process of being transmitted. Cleared when data is written
to TXDAT or TXDATCTL until the data is moved to the transmit shift
register.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXOV</name>
<description>Receiver Overrun interrupt flag. This flag applies only to
slave mode (Master = 0). This flag is set when the beginning of a
received character is detected while the receiver buffer is still in
use. If this occurs, the receiver buffer contents are preserved, and
the incoming data is lost. Data received by the SPI should be
considered undefined if RxOv is set.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXUR</name>
<description>Transmitter Underrun interrupt flag. This flag applies only
to slave mode (Master = 0). In this case, the transmitter must begin
sending new data on the next input clock if the transmitter is idle.
If that data is not available in the transmitter holding register at
that point, there is no data to transmit and the TXUR flag is set.
Data transmitted by the SPI should be considered undefined if TXUR
is set.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SSA</name>
<description>Slave Select Assert. This flag is set whenever any slave
select transitions from deasserted to asserted, in both master and
slave modes. This allows determining when the SPI transmit/receive
functions become busy, and allows waking up the device from reduced
power modes when a slave mode access begins. This flag is cleared by
software.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SSD</name>
<description>Slave Select Deassert. This flag is set whenever any
asserted slave selects transition to deasserted, in both master and
slave modes. This allows determining when the SPI transmit/receive
functions become idle. This flag is cleared by
software.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>STALLED</name>
<description>Stalled status flag. This indicates whether the SPI is
currently in a stall condition.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENDTRANSFER</name>
<description>End Transfer control bit. Software can set this bit to
force an end to the current transfer when the transmitter finishes
any activity already in progress, as if the EOT flag had been set
prior to the last transmission. This capability is included to
support cases where it is not known when transmit data is written
that it will be the end of a transfer. The bit is cleared when the
transmitter becomes idle as the transfer comes to an end. Forcing an
end of transfer in this manner causes any specified FRAME_DELAY and
TRANSFER_DELAY to be inserted.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MSTIDLE</name>
<description>Master idle status flag. This bit is 1 whenever the SPI
master function is fully idle. This means that the transmit holding
register is empty and the transmitter is not in the process of
sending data.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>SPI Interrupt Enable read and Set. A complete value may be read
from this register. Writing a 1 to any implemented bit position causes that
bit to be set.</description>
<addressOffset>0x0C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>RX ready interrupt enable. Determines whether an interrupt
occurs when receiver data is available.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when
receiver data is available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated when
receiver data is available in the RXDAT
register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRDYEN</name>
<description>TX ready interrupt enable. Determines whether an interrupt
occurs when the transmitter holding register is
available.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when the
transmitter holding register is available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated when data
may be written to TXDAT.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOVEN</name>
<description>RX overrun interrupt enable. Determines whether an
interrupt occurs when a receiver overrun occurs. This happens in
slave mode when there is a need for the receiver to move newly
received data to the RXDAT register when it is already in use. The
interface prevents receiver overrun in Master mode by not allowing a
new transmission to begin when a receiver overrun would otherwise
occur.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when a
receiver overrun occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated if a
receiver overrun occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXUREN</name>
<description>TX underrun interrupt enable. Determines whether an
interrupt occurs when a transmitter underrun occurs. This happens in
slave mode when there is a need to transmit data when none is
available.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when the
transmitter underruns.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated if the
transmitter underruns.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSAEN</name>
<description>Slave select assert interrupt enable. Determines whether an
interrupt occurs when the Slave Select is asserted.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSDEN</name>
<description>Slave select deassert interrupt enable. Determines whether
an interrupt occurs when the Slave Select is
deasserted.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when all
asserted Slave Selects transition to
deasserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated when all
asserted Slave Selects transition to
deasserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>MSTIDLEEN</name>
<description>Master idle interrupt enable</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. No interrupt will be generated when the
SPI master function is idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. An interrupt will be generated when the
SPI master function is idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
position causes the corresponding bit in INTENSET to be
cleared.</description>
<addressOffset>0x10</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXRDYEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXOVEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXUREN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SSAEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SSDEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET
register.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>MSTIDLE</name>
<description>Writing 1 clears the corresponding bits in the MSTIDLE
register.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>RXDAT</name>
<description>SPI Receive Data</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RXDAT</name>
<description>Receiver Data. This contains the next piece of received
data. The number of bits that are used depends on the LEN setting in
TXCTL / TXDATCTL.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RXSSEL0_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL0 pin to be saved along with received data. The value will
reflect the SSEL0 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RXSSEL1_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL1 pin to be saved along with received data. The value will
reflect the SSEL1 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RXSSEL2_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL2 pin to be saved along with received data. The value will
reflect the SSEL2 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>RXSSEL3_N</name>
<description>Slave Select for receive. This field allows the state of
the SSEL3 pin to be saved along with received data. The value will
reflect the SSEL3 pin for both master and slave operation. A zero
indicates that a slave select is active. The actual polarity of each
slave select pin is configured by the related SPOL bit in
CFG.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>SOT</name>
<description>Start of Transfer flag. This flag will be 1 if this is the
first data after the SSELs went from deasserted to asserted (i.e.,
any previous transfer has ended). This information can be used to
identify the first piece of data in cases where the transfer length
is greater than 16 bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not
defined.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<name>TXDATCTL</name>
<description>SPI Transmit Data with Control</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Transmit Data. This field provides from 1 to 16 bits of
data to be transmitted.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>TXSSEL0_N</name>
<description>Transmit Slave Select. This field asserts SSEL0 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL0 pin is configured by bits in the CFG
register.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSEL0_ASSERTED</name>
<description>SSEL0 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL0_NOT_ASSERTED</name>
<description>SSEL0 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL1_N</name>
<description>Transmit Slave Select. This field asserts SSEL1 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL1 pin is configured by bits in the CFG
register.</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSEL1_ASSERTED</name>
<description>SSEL1 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL1_NOT_ASSERTED</name>
<description>SSEL1 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL2_N</name>
<description>Transmit Slave Select. This field asserts SSEL2 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL2 pin is configured by bits in the CFG
register.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSEL2_ASSERTED</name>
<description>SSEL2 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL2_NOT_ASSERTED</name>
<description>SSEL2 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL3_N</name>
<description>Transmit Slave Select. This field asserts SSEL3 in master
mode. The output on the pin is active LOW by default. The active
state of the SSEL3 pin is configured by bits in the CFG
register.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSEL3_ASSERTED</name>
<description>SSEL3 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL3_NOT_ASSERTED</name>
<description>SSEL3 not asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOT</name>
<description>End of Transfer. The asserted SSEL will be deasserted at
the end of a transfer, and remain so for at least the time specified
by the Transfer_delay value in the DLY register.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SSEL_NOT_DEASSERTED</name>
<description>SSEL not deasserted. This piece of data is not
treated as the end of a transfer. SSEL will not be
deasserted at the end of this data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL_DEASSERTED</name>
<description>SSEL deasserted. This piece of data is treated as
the end of a transfer. SSEL will be deasserted at the end of
this piece of data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOF</name>
<description>End of Frame. Between frames, a delay may be inserted, as
defined by the FRAME_DELAY value in the DLY register. The end of a
frame may not be particularly meaningful if the FRAME_DELAY value =
0. This control can be used as part of the support for frame lengths
greater than 16 bits.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DATA_NOT_EOF</name>
<description>Data not EOF. This piece of data transmitted is not
treated as the end of a frame.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_EOF</name>
<description>Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXIGNORE</name>
<description>Receive Ignore. This allows data to be transmitted using
the SPI without the need to read unneeded data from the
receiver.Setting this bit simplifies the transmit process and can be
used with the DMA.</description>
<bitRange>[22:22]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>READ_RECEIVED_DATA</name>
<description>Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IGNORE_RECEIVED_DATA</name>
<description>Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>LEN</name>
<description>Data Length. Specifies the data length from 1 to 16 bits.
Note that transfer lengths greater than 16 bits are supported by
implementing multiple sequential transmits. 0x0 = Data transfer is 1
bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data
transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in
length.</description>
<bitRange>[27:24]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>TXDAT</name>
<description>SPI Transmit Data</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Transmit Data. This field provides from 4 to 16 bits of
data to be transmitted.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Only zero should be written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>TXCTL</name>
<description>SPI Transmit Control</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>TXSSEL0_N</name>
<description>Transmit Slave Select 0.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>TXSSEL1_N</name>
<description>Transmit Slave Select 1.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>TXSSEL2_N</name>
<description>Transmit Slave Select 2.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>TXSSEL3_n</name>
<description>Transmit Slave Select 3.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>EOT</name>
<description>End of Transfer.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>EOF</name>
<description>End of Frame.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>RXIGNORE</name>
<description>Receive Ignore.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>LEN</name>
<description>Data transfer Length.</description>
<bitRange>[27:24]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<description>SPI clock Divider</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVVAL</name>
<description>Rate divider value. Specifies how the PCLK for the SPI is
divided to produce the SPI clock rate in master mode. DIVVAL is -1
encoded such that the value 0 results in PCLK/1, the value 1 results
in PCLK/2, up to the maximum possible divide value of 0xFFFF, which
results in PCLK/65536.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>SPI Interrupt Status</description>
<addressOffset>0x28</addressOffset>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXOV</name>
<description>Receiver Overrun interrupt flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXUR</name>
<description>Transmitter Underrun interrupt flag.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SSA</name>
<description>Slave Select Assert.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SSD</name>
<description>Slave Select Deassert.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>MSTIDLE</name>
<description>Master Idle status flag.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be
written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI0">
<name>SPI1</name>
<description>SPI1</description>
<baseAddress>0x400A8000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<value>25</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="CT32B2">
<name>CT32B0</name>
<description>Standard counter/timer 0 </description>
<groupName>CT32B0</groupName>
<baseAddress>0x400B4000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B0</name>
<value>11</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="CT32B2">
<name>CT32B1</name>
<description>Standard counter/timer 1 </description>
<baseAddress>0x400B8000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B1</name>
<value>12</value>
</interrupt>
</peripheral>
</peripherals>
</device>
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