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RMUL2025/lib/cmsis_svd/data/NXP/LPC11E6x_v0.8.svd

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>LPC11E6x</name>
<version>0.8</version>
<description>LPC11E6x ARM cortex-m0+</description>
<cpu>
<name>CM0PLUS</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>0</mpuPresent>
<fpuPresent>0</fpuPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>0</vendorSystickConfig>
</cpu>
<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<!--
Software that is described herein is for illustrative purposes only
which provides customers with programming information regarding the
products. This software is supplied "AS IS" without any warranties.
NXP Semiconductors assumes no responsibility or liability for the
use of the software, conveys no license or title under any patent,
copyright, or mask work right to the product. NXP Semiconductors
reserves the right to make changes in the software without
notification. NXP Semiconductors also make no representation or
warranty that such application will be suitable for the specified
use without further testing or modification.
-->
<peripherals>
<peripheral>
<name>I2C0</name>
<description>I2C-bus controller</description>
<groupName>I2C0</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0</name>
<value>15</value>
</interrupt>
<registers>
<register>
<name>CONSET</name>
<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>AA</name>
<description>Assert acknowledge flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SI</name>
<description>I2C interrupt flag.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>STO</name>
<description>STOP flag.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>STA</name>
<description>START flag.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2EN</name>
<description>I2C interface enable.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<resetValue>0xF8</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>These bits are unused and are always 0.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>Status</name>
<description>These bits give the actual status information about the I2C interface.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DAT</name>
<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Data</name>
<description>This register holds data values that have been received or are to be transmitted.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADR0</name>
<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call enable bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>Address</name>
<description>The I2C device address for slave mode.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCLH</name>
<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x04</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCLH</name>
<description>Count for SCL HIGH time period selection.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCLL</name>
<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x04</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCLL</name>
<description>Count for SCL low time period selection.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONCLR</name>
<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>AAC</name>
<description>Assert acknowledge Clear bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SIC</name>
<description>I2C interrupt Clear bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>STAC</name>
<description>START flag Clear bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2ENC</name>
<description>I2C interface Disable bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MMCTRL</name>
<description>Monitor mode control register.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MM_ENA</name>
<description>Monitor mode enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MONITOR_MODE_DISABLE</name>
<description>Monitor mode disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_I2C_MODULE_WILL_</name>
<description>The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENA_SCL</name>
<description>SCL output enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>HIGH</name>
<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NORMAL</name>
<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATCH_ALL</name>
<description>Select interrupt register match.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ANYADDRESS</name>
<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from reserved bits is not defined.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1-3</dimIndex>
<name>ADR%s</name>
<description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call enable bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>Address</name>
<description>The I2C device address for slave mode.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DATA_BUFFER</name>
<description>Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Data</name>
<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MASK%s</name>
<description>I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MASK</name>
<description>Mask bits.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from reserved bits is undefined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDT</name>
<description>Windowed Watchdog Timer (WWDT)</description>
<groupName>WWDT</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MOD</name>
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDEN</name>
<description>Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STOPPED</name>
<description>The watchdog timer is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUNNING</name>
<description>The watchdog timer is running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRESET</name>
<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INTERRUPT</name>
<description>A watchdog timeout will not cause a chip reset.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOF</name>
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>WDINT</name>
<description>Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>WDPROTECT</name>
<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_LOCKED</name>
<description>The watchdog time-out value (TC) can be changed at any time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7).</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Watchdog time-out value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>FEED</name>
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>FEED</name>
<description>Feed value should be 0xAA followed by 0x55.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>TV</name>
<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter timer value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKSEL</name>
<description>Watchdog clock select register.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKSEL</name>
<description>Selects source of WDT clock</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC</name>
<description>IRC</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR_</name>
<description>Watchdog oscillator (WDOSC)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[30:1]</bitRange>
</field>
<field>
<name>LOCK</name>
<description>If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>WARNINT</name>
<description>Watchdog Warning Interrupt compare value.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WARNINT</name>
<description>Watchdog warning interrupt compare value.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>WINDOW</name>
<description>Watchdog Window compare value.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WINDOW</name>
<description>Watchdog window value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART0</name>
<description>USART0</description>
<groupName>USART0</groupName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>RBR</name>
<description>Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)</description>
<addressOffset>0x000</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RBR</name>
<description>The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)</description>
<alternateRegister>RBR</alternateRegister>
<addressOffset>0x000</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>THR</name>
<description>Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DLL</name>
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
<alternateRegister>RBR</alternateRegister>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x01</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLLSB</name>
<description>The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DLM</name>
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLMSB</name>
<description>The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)</description>
<alternateRegister>DLM</alternateRegister>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RBRINTEN</name>
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_RDA_INTE</name>
<description>Disable the RDA interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_RDA_INTER</name>
<description>Enable the RDA interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THREINTEN</name>
<description>THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_THRE_INT</name>
<description>Disable the THRE interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_THRE_INTE</name>
<description>Enable the THRE interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RLSINTEN</name>
<description>Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_RLS_INTE</name>
<description>Disable the RLS interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_RLS_INTER</name>
<description>Enable the RLS interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSINTEN</name>
<description>Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_MS_INTER</name>
<description>Disable the MS interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_MS_INTERR</name>
<description>Enable the MS interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>ABEOINTEN</name>
<description>Enables the end of auto-baud interrupt.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_END_OF_AUTO_</name>
<description>Disable end of auto-baud Interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_END_OF_AUTO_B</name>
<description>Enable end of auto-baud Interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABTOINTEN</name>
<description>Enables the auto-baud time-out interrupt.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_BAUD_TI</name>
<description>Disable auto-baud time-out Interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_BAUD_TIM</name>
<description>Enable auto-baud time-out Interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>IIR</name>
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
<addressOffset>0x008</addressOffset>
<access>read-only</access>
<resetValue>0x01</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTSTATUS</name>
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AT_LEAST_ONE_INTERRU</name>
<description>At least one interrupt is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_INTERRUPT_IS_PEND</name>
<description>No interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTID</name>
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.</description>
<bitRange>[3:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_RECEIVE_LINE_S</name>
<description>1 - Receive Line Status (RLS).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>2A__RECEIVE_DATA_AV</name>
<description>2a - Receive Data Available (RDA).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>2B__CHARACTER_TIME_</name>
<description>2b - Character Time-out Indicator (CTI).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>3_THRE_INTERRUPT</name>
<description>3 - THRE Interrupt.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_MODEM_STATUS</name>
<description>4 - Modem status</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>FIFOEN</name>
<description>These bits are equivalent to FCR[0].</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>ABEOINT</name>
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ABTOINT</name>
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<description>FIFO Control Register. Controls USART FIFO usage and modes.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FIFOEN</name>
<description>FIFO enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>USART FIFOs are disabled. Must not be used in the application.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFIFORES</name>
<description>RX FIFO Reset</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>No impact on either of USART FIFOs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFORES</name>
<description>TX FIFO Reset</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>No impact on either of USART FIFOs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>RXTL</name>
<description>RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TRIGGER_LEVEL_0_1_C</name>
<description>Trigger level 0 (1 character or 0x01).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_1_4_C</name>
<description>Trigger level 1 (4 characters or 0x04).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_2_8_C</name>
<description>Trigger level 2 (8 characters or 0x08).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_3_14_</name>
<description>Trigger level 3 (14 characters or 0x0E).</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>LCR</name>
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WLS</name>
<description>Word Length Select</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>5_BIT_CHARACTER_LENG</name>
<description>5-bit character length.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BIT_CHARACTER_LENG</name>
<description>6-bit character length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BIT_CHARACTER_LENG</name>
<description>7-bit character length.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_CHARACTER_LENG</name>
<description>8-bit character length.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBS</name>
<description>Stop Bit Select</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_STOP_BIT_</name>
<description>1 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP_BITS_1_5_IF_</name>
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_PARITY_GENER</name>
<description>Disable parity generation and checking.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_PARITY_GENERA</name>
<description>Enable parity generation and checking.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PS</name>
<description>Parity Select</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ODD_PARITY_NUMBER_O</name>
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_PARITY_NUMBER_</name>
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_1_STICK_PARIT</name>
<description>Forced 1 stick parity.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_0_STICK_PARIT</name>
<description>Forced 0 stick parity.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BC</name>
<description>Break Control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_BREAK_TRANSM</name>
<description>Disable break transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_BREAK_TRANSMI</name>
<description>Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLAB</name>
<description>Divisor Latch Access Bit</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_ACCESS_TO_DI</name>
<description>Disable access to Divisor Latches.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_ACCESS_TO_DIV</name>
<description>Enable access to Divisor Latches.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Modem Control Register.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRCTRL</name>
<description>Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTSCTRL</name>
<description>Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>LMS</name>
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_MODEM_LOOPBA</name>
<description>Disable modem loopback mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_MODEM_LOOPBAC</name>
<description>Enable modem loopback mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RTSEN</name>
<description>RTS enable</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_RTS_FLO</name>
<description>Disable auto-rts flow control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_RTS_FLOW</name>
<description>Enable auto-rts flow control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS enable</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_CTS_FLO</name>
<description>Disable auto-cts flow control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_CTS_FLOW</name>
<description>Enable auto-cts flow control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>LSR</name>
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
<addressOffset>0x014</addressOffset>
<access>read-only</access>
<resetValue>0x60</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RDR</name>
<description>Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RBR_IS_EMPTY_</name>
<description>RBR is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RBR_CONTAINS_VALID_D</name>
<description>RBR contains valid data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OE</name>
<description>Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Overrun error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Overrun error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Parity error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Parity error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Framing error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Framing error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BI</name>
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Break interrupt status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Break interrupt status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THRE</name>
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THR_CONTAINS_VALID_D</name>
<description>THR contains valid data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THR_IS_EMPTY_</name>
<description>THR is empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEMT</name>
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>VALID_D</name>
<description>THR and/or the TSR contains valid data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>THR and the TSR are empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_ERROR</name>
<description>RBR contains no USART RX errors or FCR[0]=0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ERRO</name>
<description>USART RBR contains at least one USART RX error.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXERR</name>
<description>Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>MSR</name>
<description>Modem Status Register.</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>DCTS</name>
<description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, CTS.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, CTS.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDSR</name>
<description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, DSR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, DSR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TERI</name>
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, RI.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_TO_HIGH_TRANSITI</name>
<description>Low-to-high transition detected on RI.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDCD</name>
<description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, DCD.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, DCD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTS</name>
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DSR</name>
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RI</name>
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>DCD</name>
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>Scratch Pad Register. Eight-bit temporary storage for software.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PAD</name>
<description>A readable, writable byte.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>ACR</name>
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>START</name>
<description>This bit is automatically cleared after auto-baud completion.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AUTO_BAUD_STOP_AUTO</name>
<description>Auto-baud stop (auto-baud is not running).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_BAUD_START_AUT</name>
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Auto-baud mode select bit.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MODE_0_</name>
<description>Mode 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE_1_</name>
<description>Mode 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTORESTART</name>
<description>Start mode</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_RESTART</name>
<description>No restart</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESTART_IN_CASE_OF_T</name>
<description>Restart in case of time-out (counter restarts at next USART Rx falling edge)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>ABEOINTCLR</name>
<description>End of auto-baud interrupt clear bit (write only accessible).</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>Writing a 0 has no impact.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABTOINTCLR</name>
<description>Auto-baud time-out interrupt clear bit (write only accessible).</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>Writing a 0 has no impact.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>IrDA Control Register. Enables and configures the IrDA (remote control) mode.</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRDAEN</name>
<description>IrDA mode enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRDA_MODE_IS_DISABLE</name>
<description>IrDA mode is disabled, USARTn acts as a standard USART.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IRDA_MODE_IS_ENABLED</name>
<description>IrDA mode is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRDAINV</name>
<description>Serial input inverter</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INVERTED</name>
<description>The serial input is not inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>The serial input is inverted. This has no effect on the serial output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIXPULSEEN</name>
<description>IrDA fixed pulse width mode.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>IrDA fixed pulse width mode disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>IrDA fixed pulse width mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PULSEDIV</name>
<description>Configures the pulse width when FixPulseEn = 1.</description>
<bitRange>[5:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>3_DIV_16_X_BAUD_RATE</name>
<description>3 / (16 x baud rate)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_TPCLK</name>
<description>2 x TPCLK</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_TPCLK</name>
<description>4 x TPCLK</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_X_TPCLK</name>
<description>8 x TPCLK</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>16_X_TPCLK</name>
<description>16 x TPCLK</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>32_X_TPCLK</name>
<description>32 x TPCLK</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>64_X_TPCLK</name>
<description>64 x TPCLK</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>128_X_TPCLK</name>
<description>128 x TPCLK</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>FDR</name>
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVADDVAL</name>
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>MULVAL</name>
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Oversampling Register. Controls the degree of oversampling during each bit time.</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0xF0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>OSFRAC</name>
<description>Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)</description>
<bitRange>[3:1]</bitRange>
</field>
<field>
<name>OSINT</name>
<description>Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>FDINT</name>
<description>In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.</description>
<bitRange>[14:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:15]</bitRange>
</field>
</fields>
</register>
<register>
<name>TER</name>
<description>Transmit Enable Register. Turns off USART transmitter for use with software flow control.</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[6:0]</bitRange>
</field>
<field>
<name>TXEN</name>
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>HDEN</name>
<description>Half duplex enable register.</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HDEN</name>
<description>Half-duplex mode enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_HALF_DUPLEX_</name>
<description>Disable half-duplex mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_HALF_DUPLEX_M</name>
<description>Enable half-duplex mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCICTRL</name>
<description>Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCIEN</name>
<description>Smart Card Interface Enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SMART_CARD_INTERFACE</name>
<description>Smart card interface disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ASYNCHRONOUS_HALF_DU</name>
<description>Asynchronous half duplex smart card interface is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NACKDIS</name>
<description>NACK response disable. Only applicable in T=0.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>A NACK response is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>A NACK response is inhibited.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROTSEL</name>
<description>Protocol selection as defined in the ISO7816-3 standard.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>T_EQ_0</name>
<description>T = 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>T_EQ_1</name>
<description>T = 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[4:3]</bitRange>
</field>
<field>
<name>TXRETRY</name>
<description>When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>XTRAGUARD</name>
<description>When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485CTRL</name>
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
<addressOffset>0x04C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMMEN</name>
<description>NMM enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDIS</name>
<description>Receiver enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_RECEIVER_IS_ENAB</name>
<description>The receiver is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_RECEIVER_IS_DISA</name>
<description>The receiver is disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AADEN</name>
<description>AAD enable.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AUTO_ADDRESS_DETECT_</name>
<description>Auto Address Detect (AAD) is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_ADDRESS_DETECT_</name>
<description>Auto Address Detect (AAD) is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEL</name>
<description>Select direction control pin</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RTS</name>
<description>If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTR</name>
<description>If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCTRL</name>
<description>Auto direction control enable.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_DIRECTI</name>
<description>Disable Auto Direction Control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_DIRECTIO</name>
<description>Enable Auto Direction Control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OINV</name>
<description>Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485ADRMATCH</name>
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADRMATCH</name>
<description>Contains the address match value.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485DLY</name>
<description>RS-485/EIA-485 direction control delay.</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYNCCTRL</name>
<description>Synchronous mode control register.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYNC</name>
<description>Enables synchronous mode.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSRC</name>
<description>Clock source select.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYNCHRONOUS_SLAVE_MO</name>
<description>Synchronous slave mode (SCLK in)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCHRONOUS_MASTER_M</name>
<description>Synchronous master mode (SCLK out)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FES</name>
<description>Falling edge sampling.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RISING</name>
<description>RxD is sampled on the rising edge of SCLK </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>RxD is sampled on the falling edge of SCLK</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSBYPASS</name>
<description>Transmit synchronization bypass in synchronous slave mode.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYNC</name>
<description>The input clock is synchronized prior to being used in clock edge detection logic</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOSYNC</name>
<description>The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSCEN</name>
<description>Continuous master clock enable (used only when CSRC is 1)</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SCLK_CYCLES_ONLY_WHE</name>
<description>SCLK cycles only when characters are being sent on TxD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCLK_RUNS_CONTINUOUS</name>
<description>SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSDIS</name>
<description>Start/stop bits</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SEND_START_AND_STOP_</name>
<description>Send start and stop bits as in other modes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DO_NOT_SEND_STARTSTOP</name>
<description>Do not send start/stop bits.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCCLR</name>
<description>Continuous clock clear</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CSCEN_IS_UNDER_SOFTW</name>
<description>CSCEN is under software control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HARDWARE_CLEARS_CSCE</name>
<description>Hardware clears CSCEN after each character is received.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CT16B0</name>
<description>16-bit counter/timers CT16B0</description>
<groupName>CT16B0</groupName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT16B0</name>
<value>16</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCVAL</name>
<description>Timer counter value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescale value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PC</name>
<description>Prescale counter value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MR%s</name>
<description>Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0FE</name>
<description>Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0I</name>
<description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1RE</name>
<description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1FE</name>
<description>Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1I</name>
<description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2RE</name>
<description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2FE</name>
<description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2I</name>
<description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>CR%s</name>
<description>Capture Register. CR is loaded with the value of TC when there is an event on the CAP input.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
<addressOffset>0x03C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding
External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding
External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding
External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding
External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTM</name>
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_MODE</name>
<description>Timer Mode. Increments every rising PCLK edge</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL</name>
<description>Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIS</name>
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CAPTURE_CHANNEL_0</name>
<description>Capture channel 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE_CHANNEL_1</name>
<description>Capture channel 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE_CHANNEL_2</name>
<description>Capture channel 2.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SELCC</name>
<description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CAP0RISING</name>
<description>Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP0FALLING</name>
<description>Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP1RISING</name>
<description>Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP1FALLING</name>
<description>Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP2RISING</name>
<description>Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP1FALLING</name>
<description>Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM0</name>
<description>CT16Bn_MAT0 is controlled by EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT16Bn_MAT0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM1</name>
<description>CT16Bn_MAT01 is controlled by EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT16Bn_MAT1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM2</name>
<description>CT16Bn_MAT2 is controlled by EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT16Bn_MAT2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM3</name>
<description>CT16Bn_MAT3 is controlled by EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT16Bn_MAT3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CT16B0">
<name>CT16B1</name>
<description>16-bit counter/timers CT16B1</description>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT16B1</name>
<value>17</value>
</interrupt>
</peripheral>
<peripheral>
<name>CT32B0</name>
<description>32-bit counter/timers CT32B0</description>
<groupName>CT32B0</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B0</name>
<value>18</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCVAL</name>
<description>Timer counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescaler value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PC</name>
<description>Prescale counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MR%s</name>
<description>Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0FE</name>
<description>Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0I</name>
<description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1RE</name>
<description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1FE</name>
<description>Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1I</name>
<description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2RE</name>
<description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2FE</name>
<description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP2I</name>
<description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>CR%s</name>
<description>Capture Register. CR is loaded with the value of TC when there is an event on the CAP input.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0].</description>
<addressOffset>0x03C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOP</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTM</name>
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_MODE</name>
<description>Timer Mode. Increments every rising PCLK edge</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_RISING</name>
<description>Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_FALLING</name>
<description>Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_MODE_DUAL_ED</name>
<description>Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIS</name>
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CAPTURE_CHANNEL_0</name>
<description>Capture channel 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE_CHANNEL_1</name>
<description>Capture channel 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE_CHANNEL_2</name>
<description>Capture channel 2.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SELCC</name>
<description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CAP0RISING</name>
<description>Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP0FALLING</name>
<description>Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP1RISING</name>
<description>Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP1FALLING</name>
<description>Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP2RISING</name>
<description>Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CAP2FALLING</name>
<description>Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM0</name>
<description>CT32Bn_MAT0 is controlled by EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT32Bn_MAT0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM1</name>
<description>CT32Bn_MAT01 is controlled by EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT32Bn_MAT1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM2</name>
<description>CT32Bn_MAT2 is controlled by EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT32Bn_MAT2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM3</name>
<description>CT32Bn_MAT3 is controlled by EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM mode is enabled for CT132Bn_MAT3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CT32B0">
<name>CT32B1</name>
<description>32-bit counter/timers CT32B1</description>
<baseAddress>0x40018000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B1</name>
<value>19</value>
</interrupt>
</peripheral>
<peripheral>
<name>ADC</name>
<description>12-bit Analog-to-Digital Converter (ADC)</description>
<groupName>ADC</groupName>
<baseAddress>0x4001C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC_A</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>The system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>LPWRMODE</name>
<description>Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The low-power ADC mode is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAL_MODE</name>
<description>Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEQA_CTRL</name>
<description>A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHANNELS</name>
<description>Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.</description>
<bitRange>[11:0]</bitRange>
</field>
<field>
<name>TRIGGER</name>
<description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field.</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[17:15]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Select the polarity of the selected input trigger for this conversion sequence.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NEGATIVE_EDGE</name>
<description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE_EDGE</name>
<description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCBYPASS</name>
<description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLE_SYNCHRONIZATI</name>
<description>Enable synchronization. The hardware trigger bypass is not enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_SYNCHRONIZATI</name>
<description>Bypass synchronization. The hardware trigger bypass is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>START</name>
<description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>BURST</name>
<description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SINGLESTEP</name>
<description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>LOWPRIO</name>
<description>Set priority for sequence A.</description>
<bitRange>[29:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW_PRIORITY</name>
<description>Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_PRIORITY</name>
<description>High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below:</description>
<bitRange>[30:30]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>END_OF_CONVERSION</name>
<description>End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>END_OF_SEQUENCE</name>
<description>End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQA_ENA</name>
<description>Sequence Enable</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Sequence A is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQB_CTRL</name>
<description>A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHANNELS</name>
<description>Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write.</description>
<bitRange>[11:0]</bitRange>
</field>
<field>
<name>TRIGGER</name>
<description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field.</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[17:15]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Select the polarity of the selected input trigger for this conversion sequence.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NEGATIVE_EDGE</name>
<description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE_EDGE</name>
<description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCBYPASS</name>
<description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLE_SYNCHRONIZATI</name>
<description>Enable synchronization. The hardware trigger bypass is not enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_SYNCHRONIZATI</name>
<description>Bypass synchronization. The hardware trigger bypass is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>START</name>
<description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>BURST</name>
<description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SINGLESTEP</name>
<description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below:</description>
<bitRange>[30:30]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>END_OF_CONVERSION</name>
<description>End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>END_OF_SEQUENCE</name>
<description>End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQB_ENA</name>
<description>Sequence Enable</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Sequence B is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQA_GDAT</name>
<description>A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...).</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled).</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEQB_GDAT</name>
<description>A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...).</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled).</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-11</dimIndex>
<name>DAT[%s]</name>
<displayName>DAT[%s]</displayName>
<description>A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.</description>
<addressOffset>0x020</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>THCMPRANGE</name>
<description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>THCMPCROSS</name>
<description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
<bitRange>[19:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[25:20]</bitRange>
</field>
<field>
<name>CHANNEL</name>
<description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
<bitRange>[29:26]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR0_LOW</name>
<description>A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THRLOW</name>
<description>Low threshold value against which A/D results will be compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR1_LOW</name>
<description>A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THRLOW</name>
<description>Low threshold value against which A/D results will be compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR0_HIGH</name>
<description>A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THRHIGH</name>
<description>High threshold value against which A/D results will be compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR1_HIGH</name>
<description>A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
<addressOffset>0x05C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THRHIGH</name>
<description>High threshold value against which A/D results will be compared</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CHAN_THRSEL</name>
<description>A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel</description>
<addressOffset>0x060</addressOffset>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH10_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH11_THRSEL</name>
<description>Threshold select by channel.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THRESHOLD_0</name>
<description>Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD_1</name>
<description>Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTEN</name>
<description>A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.</description>
<addressOffset>0x064</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEQA_INTEN</name>
<description>Sequence A interrupt enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence A interrupt/DMA request is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQB_INTEN</name>
<description>Sequence B interrupt enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence B interrupt/DMA request is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVR_INTEN</name>
<description>Overrun interrupt enable.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The overrun interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN0</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN1</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[6:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN2</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[8:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN3</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[10:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN4</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN5</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[14:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN6</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[16:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN7</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[18:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN8</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[20:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN9</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[22:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN10</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[24:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN11</name>
<description>Threshold comparison interrupt enable.</description>
<bitRange>[26:25]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:27]</bitRange>
</field>
</fields>
</register>
<register>
<name>FLAGS</name>
<description>A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).</description>
<addressOffset>0x068</addressOffset>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THCMP0</name>
<description>Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>THCMP1</name>
<description>Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>THCMP2</name>
<description>Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>THCMP3</name>
<description>Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>THCMP4</name>
<description>Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>THCMP5</name>
<description>Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>THCMP6</name>
<description>Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>THCMP7</name>
<description>Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>THCMP8</name>
<description>Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>THCMP9</name>
<description>Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>THCMP10</name>
<description>Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>THCMP11</name>
<description>Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>OVERRUN0</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 0</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>OVERRUN1</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 1</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>OVERRUN2</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 2</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>OVERRUN3</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 3</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>OVERRUN4</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 4</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>OVERRUN5</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 5</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>OVERRUN6</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 6</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>OVERRUN7</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 7</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>OVERRUN8</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 8</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>OVERRUN9</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 9</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>OVERRUN10</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 10</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>OVERRUN11</name>
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 11</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>SEQA_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQA_GDAT register</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SEQB_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQB_GDAT register</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[27:26]</bitRange>
</field>
<field>
<name>SEQA_INT</name>
<description>Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>SEQB_INT</name>
<description>Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>THCMP_INT</name>
<description>Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>OVR_INT</name>
<description>Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>TRM</name>
<description>ADC trim register.</description>
<addressOffset>0x06C</addressOffset>
<access>read-write</access>
<resetValue>0x00000F00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>VRANGE</name>
<description>Reserved.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>HIGH_VOLTAGE</name>
<description>High voltage. VDDA = 2.7 V to 3.6 V.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_VOLTAGE</name>
<description>Low voltage. VDDA = 1.8 V to 2.7 V.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C0">
<name>I2C1</name>
<description>I2C1</description>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1</name>
<value>10</value>
</interrupt>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real-Time Clock (RTC)</description>
<groupName>RTC</groupName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC</name>
<value>25</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>RTC control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SWRESET</name>
<description>Software reset control</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_IN_RESET</name>
<description>Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN_RESET</name>
<description>In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OFD</name>
<description>Oscillator fail detect status.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RUN</name>
<description>Run. The RTC oscillator is running properly. Writing a 0 has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAIL</name>
<description>Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARM1HZ</name>
<description>RTC 1 Hz timer alarm flag status.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_MATCH</name>
<description>No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MATCH</name>
<description>Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE1KHZ</name>
<description>RTC 1 kHz timer wake-up flag status.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RUN</name>
<description>Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIME_OUT</name>
<description>Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARMDPD_EN</name>
<description>RTC 1 Hz timer alarm enable for Deep power-down.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKEDPD_EN</name>
<description>RTC 1 kHz timer wake-up enable for Deep power-down.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC1KHZ_EN</name>
<description>RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. The 1 kHz RTC timer is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC_EN</name>
<description>RTC enable.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MATCH</name>
<description>RTC match register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATVAL</name>
<description>Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>RTC counter register</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>WAKE</name>
<description>RTC high-resolution/wake-up timer control register</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMATRIGMUX</name>
<description>DMA controller</description>
<groupName>DMATRIGMUX</groupName>
<baseAddress>0x40028000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>16</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-15</dimIndex>
<name>DMA_ITRIG_PINMUX[%s]</name>
<displayName>DMA_ITRIG_PINMUX[%s]</displayName>
<description>Trigger input select register for DMA channel 0.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INP_N</name>
<description>Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0 = ADC0_SEQA_IRQ 1 = ADC0_SEQB_IRQ 2 = CT16B0_MAT0 3 = CT16B1_MAT0 4 = CT32B0_MAT0 5 = CT16B1_MAT0 6 = PINT0 ( pin interrupt 0) 7 = PINT1 (pin interrupt1 ) 8 = SCT0_DMA0 9 = SCT0_DMA1 10 = SCT1_DMA0 11 = SCT1_DMA1</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMU</name>
<description>Power Management Unit (PMU)</description>
<groupName>PMU</groupName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCON</name>
<description>Power control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Power mode</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DEFAULT</name>
<description>Default. The part is in active or sleep mode.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_SLEEP</name>
<description>Deep-sleep. ARM WFI will enter Deep-sleep mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWER_DOWN</name>
<description>Power-down. ARM WFI will enter Power-down mode.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_POWER_DOWN</name>
<description>Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NODPD</name>
<description>A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to this bit.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>SLEEPFLAG</name>
<description>Sleep mode flag</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ACTIVE_MODE</name>
<description>Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER_MODE</name>
<description>Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to this bit.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DPDFLAG</name>
<description>Deep power-down flag</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_DEEP_POWER_DOWN</name>
<description>Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_POWER_DOWN</name>
<description>Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to this bit.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>GPREG%s</name>
<description>General purpose register 0</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPDATA</name>
<description>Data retained during Deep power-down mode.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPREG4</name>
<description>Deep power down control register</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to this bit.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>WAKEUPHYS</name>
<description>WAKEUP pin hysteresis enable</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_HYSTERESIS_F</name>
<description>Disable Hysteresis for WAKUP pin disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. Hysteresis for WAKEUP pin enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKEPAD_DISABLE</name>
<description>WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the RTC wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. The wake-up function is enabled on pin PIO0_16.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable. Setting this bit disables the wake-up function on pin PIO0_16.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPDATA</name>
<description>Data retained during Deep power-down mode.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASHCTRL</name>
<description> Flash controller </description>
<groupName>FLASHCTRL</groupName>
<baseAddress>0x4003C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<value>27</value>
</interrupt>
<registers>
<register>
<name>FLASHCFG</name>
<description>Flash configuration register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>FLASHTIM</name>
<description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_SYSTEM_CLOCK_FLASH</name>
<description>1 system clock flash access time (for system clock frequencies of up to 20 MHz).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_SYSTEM_CLOCKS_FLAS</name>
<description>2 system clocks flash access time (for system clock frequencies of up to 30 MHz).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED_</name>
<description>Reserved.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED_</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSSTART</name>
<description>Signature start address register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>START</name>
<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
<bitRange>[16:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSSTOP</name>
<description>Signature stop-address register</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STOPA</name>
<description>Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111.</description>
<bitRange>[16:0]</bitRange>
</field>
<field>
<name>STRTBIST</name>
<description>When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSW0</name>
<description>Signature Word </description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SIG</name>
<description>32-bit signature.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SSP0</name>
<description>SSP/SPI </description>
<groupName>SSP0</groupName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SSP0</name>
<value>20</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DSS</name>
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
<bitRange>[3:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>4_BIT_TRANSFER</name>
<description>4-bit transfer</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>5_BIT_TRANSFER</name>
<description>5-bit transfer</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BIT_TRANSFER</name>
<description>6-bit transfer</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BIT_TRANSFER</name>
<description>7-bit transfer</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_TRANSFER</name>
<description>8-bit transfer</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BIT_TRANSFER</name>
<description>9-bit transfer</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>10_BIT_TRANSFER</name>
<description>10-bit transfer</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>11_BIT_TRANSFER</name>
<description>11-bit transfer</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>12_BIT_TRANSFER</name>
<description>12-bit transfer</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>13_BIT_TRANSFER</name>
<description>13-bit transfer</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>14_BIT_TRANSFER</name>
<description>14-bit transfer</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>15_BIT_TRANSFER</name>
<description>15-bit transfer</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>16_BIT_TRANSFER</name>
<description>16-bit transfer</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRF</name>
<description>Frame Format.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SPI</name>
<description>SPI</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TI</name>
<description>TI</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MICROWIRE</name>
<description>Microwire</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>This combination is not supported and should not be used.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>SPI controller maintains the bus clock low between frames.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>SPI controller maintains the bus clock high between frames.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FIRSTCLOCK</name>
<description>SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SECONDCLOCK</name>
<description>SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCR</name>
<description>Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>Control Register 1. Selects master/slave and other modes.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LBM</name>
<description>Loop Back Mode.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DURING_NORMAL_OPERAT</name>
<description>During normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SERIAL_INPUT_IS_TAKE</name>
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSE</name>
<description>SPI Enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The SPI controller is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MS</name>
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MASTER</name>
<description>The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE</name>
<description>The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOD</name>
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>DR</name>
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>DATA</name>
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0x00000003</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TFE</name>
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TNF</name>
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RNE</name>
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RFF</name>
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BSY</name>
<description>Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>CPSR</name>
<description>Clock Prescale Register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPSDVSR</name>
<description>This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IMSC</name>
<description>Interrupt Mask Set and Clear Register</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORIM</name>
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTIM</name>
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXIM</name>
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIM</name>
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>RIS</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORRIS</name>
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTRIS</name>
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXRIS</name>
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXRIS</name>
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>MIS</name>
<description>Masked Interrupt Status Register</description>
<addressOffset>0x01C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORMIS</name>
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTMIS</name>
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXMIS</name>
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXMIS</name>
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>SSPICR Interrupt Clear Register</description>
<addressOffset>0x020</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RORIC</name>
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTIC</name>
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IOCON</name>
<description>I/O control (IOCON) </description>
<groupName>IOCON</groupName>
<baseAddress>0x40044000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>PIO0_%s</name>
<description>I/O configuration for port PIO0</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_4</name>
<description>I/O configuration for open-drain pin PIO0_4</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function. </description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>I2CMODE</name>
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE_FAST</name>
<description>Standard mode/ Fast-mode I2C.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STANDARD_IO_FUNCTIO</name>
<description>Standard I/O functionality</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE_PLUS_I2C</name>
<description>Fast-mode Plus I2C</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_5</name>
<description>I/O configuration for open-drain pin PIO0_5</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function. </description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>I2CMODE</name>
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE_FAST</name>
<description>Standard mode/ Fast-mode I2C.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STANDARD_IO_FUNCTIO</name>
<description>Standard I/O functionality</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE_PLUS_I2C</name>
<description>Fast-mode Plus I2C</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>18</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>6-23</dimIndex>
<name>PIO0_%s</name>
<description>I/O configuration for port PIO0</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-31</dimIndex>
<name>PIO1_%s</name>
<description>I/O configuration for port PIO1</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PIO2_%s</name>
<description>I/O configuration for port PIO2</description>
<addressOffset>0x0F0</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>2-23</dimIndex>
<name>PIO2_%s</name>
<description>I/O configuration for port PIO2</description>
<addressOffset>0x0FC</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCON</name>
<description>System configuration (SYSCON)</description>
<groupName>SYSCON</groupName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>BOD_WDT</name>
<value>26</value>
</interrupt>
<registers>
<register>
<name>SYSMEMREMAP</name>
<description>System memory remap</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAP</name>
<description>System memory remap. Value 0x3 is reserved.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BOOT_LOADER_MODE</name>
<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_RAM_MODE</name>
<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_FLASH_MODE</name>
<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL</name>
<description>Peripheral reset control</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSP0_RST_N</name>
<description>SSP0 reset control</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the SSP0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. SSP0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0_RST_N</name>
<description>I2C0 reset control</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the I2C0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. I2C0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSP1_RST_N</name>
<description>SSP1 reset control</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the SSP1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. SSP1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1_RST_N</name>
<description>I2C1 reset control</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the I2C1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. I2C1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRG_RST_N</name>
<description>FRG reset control</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the FRG peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. FRG reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1_RST_N</name>
<description>USART1 reset control</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the USART1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. USART1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2_RST_N</name>
<description>USART2 reset control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the USART2 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. USART2 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3_RST_N</name>
<description>USART3 reset control</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the USART3 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. USART3 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART4_RST_N</name>
<description>USART4 reset control</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the USART4 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. USART4 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCT0_RST_N</name>
<description>SCT0 reset control</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the SCT0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. SCT0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCT1_RST_N</name>
<description>SCT1 reset control</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset. Resets the SCT1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_RESET</name>
<description>Clear reset. SCT1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCTRL</name>
<description>System PLL control</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>PSEL</name>
<description>Post divider ratio P. The division ratio is 2 x P.</description>
<bitRange>[6:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>P_EQ_1</name>
<description>P = 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_2</name>
<description>P = 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_4</name>
<description>P = 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_8</name>
<description>P = 8</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to reserved bits.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLSTAT</name>
<description>System PLL status</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCK</name>
<description>PLL lock status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_LOCK</name>
<description>No lock. PLL not locked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCK</name>
<description>Lock. PLL locked</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>RTCOSCCTRL</name>
<description>RTC oscillator 32 kHz output control</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTCOSCEN</name>
<description>Enable the RTC 32 kHz output.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. 32 kHz output disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. 32 kHz output enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSOSCCTRL</name>
<description>System oscillator control</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BYPASS</name>
<description>Bypass system oscillator</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OSCILLATOR_IS_NOT_BY</name>
<description>Oscillator is not bypassed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_ENABLED</name>
<description>Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FREQRANGE</name>
<description>Determines frequency range for Low-power oscillator.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. 1 - 20 MHz frequency range.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. 15 - 25 MHz frequency range.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>WDTOSCCTRL</name>
<description>Watchdog oscillator control</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVSEL</name>
<description>Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>FREQSEL</name>
<description>Select watchdog oscillator analog output frequency (Fclkana).</description>
<bitRange>[8:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>0</name>
<description>0.6 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1.05 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1.4 MHz</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1.75 MHz</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>2.1 MHz</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>2.4 MHz</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>2.7 MHz</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>3.0 MHz</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>3.25 MHz</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>3.5 MHz</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>3.75 MHz</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>4.0 MHz</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>4.2 MHz</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>4.4 MHz</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>4.6 MHz</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRCCTRL</name>
<description>IRC control</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0x080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>Trim value</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSRSTSTAT</name>
<description>System reset status register</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POR</name>
<description>POR reset status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_POR_DETECTED</name>
<description>No POR detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POR_DETECTED</name>
<description>POR detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTRST</name>
<description>Status of the external RESET pin</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_RESET_EVENT_DETEC</name>
<description>No reset event detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_DETECTED</name>
<description>Reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT</name>
<description>Status of the Watchdog reset</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_WDT_RESET_DETECTE</name>
<description>No WDT reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WDT_RESET_DETECTED</name>
<description>WDT reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD</name>
<description>Status of the Brown-out detect reset</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_BOD_RESET_DETECTE</name>
<description>No BOD reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BOD_RESET_DETECTED</name>
<description>BOD reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSRST</name>
<description>Status of the software system reset</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_SYSTEM_RESET_DETE</name>
<description>No System reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_RESET_DETECTE</name>
<description>System reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCLKSEL</name>
<description>System PLL clock source select</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>System PLL clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC</name>
<description>IRC</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_OSCILLATOR</name>
<description>System oscillator. Crystal Oscillator (SYSOSC)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>32_KHZ_CLOCK</name>
<description>32 kHz clock.Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register. Do not use the 32 kHz clock with the PLL.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCLKUEN</name>
<description>System PLL clock source update enable</description>
<addressOffset>0x044</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable system PLL clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKSEL</name>
<description>Main clock source select</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for main clock</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_INPUT</name>
<description>PLL input</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_OUTPUT</name>
<description>PLL output</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKUEN</name>
<description>Main clock source update enable</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable main clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKDIV</name>
<description>System clock divider</description>
<addressOffset>0x078</addressOffset>
<access>read-write</access>
<resetValue>0x001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKCTRL</name>
<description>System clock control</description>
<addressOffset>0x080</addressOffset>
<access>read-write</access>
<resetValue>0x3F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYS</name>
<description>This bit is read-only and always reads as 1. It configures the always-on clock for the AHB, the APB bridges, the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU. Writes to this bit are ignored.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ROM</name>
<description>Enables clock for ROM.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM0</name>
<description>Enables clock for Main SRAM0.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHREG</name>
<description>Enables clock for flash register interface.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHARRAY</name>
<description>Enables clock for flash access.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0</name>
<description>Enables clock for I2C.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIO</name>
<description>Enables clock for GPIO port registers.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B0</name>
<description>Enables clock for 16-bit counter/timer 0.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B1</name>
<description>Enables clock for 16-bit counter/timer 1.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B0</name>
<description>Enables clock for 32-bit counter/timer 0.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B1</name>
<description>Enables clock for 32-bit counter/timer 1.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSP0</name>
<description>Enables clock for SSP0.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART0</name>
<description>Enables clock for USART0.</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC</name>
<description>Enables clock for ADC.</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>WWDT</name>
<description>Enables clock for WWDT.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOCON</name>
<description>Enables clock for I/O configuration block.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SSP1</name>
<description>Enables clock for SSP1.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT</name>
<description>Enables clock to GPIO Pin interrupt register interface.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1</name>
<description>Enables clock to USART1 register interface.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2</name>
<description>Enables clock to USART2 register interface.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3_4</name>
<description>Enables clock to USART3 and USART4 register interfaces.</description>
<bitRange>[22:22]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GROUP0INT</name>
<description>Enables clock to GPIO GROUP0 interrupt register interface.</description>
<bitRange>[23:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GROUP1INT</name>
<description>Enables clock to GPIO GROUP1 interrupt register interface.</description>
<bitRange>[24:24]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>Enables clock for I2C1.</description>
<bitRange>[25:25]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM1</name>
<description>Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.</description>
<bitRange>[26:26]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBSRAM</name>
<description>Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800.</description>
<bitRange>[27:27]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC</name>
<description>Enables clock for CRC.</description>
<bitRange>[28:28]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>Enables clock for DMA.</description>
<bitRange>[29:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC</name>
<description>Enables clock for RTC register interface.</description>
<bitRange>[30:30]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCT0_1</name>
<description>Enables clock for SCT0 and SCT1.</description>
<bitRange>[31:31]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSP0CLKDIV</name>
<description>SSP0 clock divider</description>
<addressOffset>0x094</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>USART0CLKDIV</name>
<description>USART0 clock divider</description>
<addressOffset>0x098</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SSP1CLKDIV</name>
<description>SSP1 clock divider</description>
<addressOffset>0x09C</addressOffset>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FRGCLKDIV</name>
<description>Clock divider for the common fractional baud rate generator of USART1, USART2, USART3, USART4</description>
<addressOffset>0x0A0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTSEL</name>
<description>CLKOUT clock source select</description>
<addressOffset>0x0E0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>CLKOUT clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRYSTAL_OSCILLATOR</name>
<description>Crystal oscillator (SYSOSC)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR</name>
<description>Watchdog oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLOCK</name>
<description>Main clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTUEN</name>
<description>CLKOUT clock source update enable</description>
<addressOffset>0x0E4</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable CLKOUT clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTDIV</name>
<description>CLKOUT clock divider</description>
<addressOffset>0x0E8</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>UARTFRGDIV</name>
<description>USART fractional generator divider value</description>
<addressOffset>0x0F0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>UARTFRGMULT</name>
<description>USART fractional generator multiplier value</description>
<addressOffset>0x0F4</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MULT</name>
<description>Numerator of the fractional divider. MULT is equal to the programmed value.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>EXTTRACECMD</name>
<description>External trace buffer command register</description>
<addressOffset>0x0FC</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>START</name>
<description>Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>STOP</name>
<description>Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP0</name>
<description>POR captured PIO status 0</description>
<addressOffset>0x100</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO0_23 through PIO0_0 at power-on reset</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP1</name>
<description>POR captured PIO status 1</description>
<addressOffset>0x104</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO1_31 through PIO1_0 at power-on reset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP2</name>
<description>POR captured PIO status 1</description>
<addressOffset>0x108</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO2_23 through PIO2_0 at power-on reset</description>
<bitRange>[23:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV6</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x134</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV5</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x138</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV4</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x13C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV3</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x140</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV2</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x144</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV1</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x148</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IOCONCLKDIV0</name>
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
<addressOffset>0x14C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>BODCTRL</name>
<description>Brown-Out Detect</description>
<addressOffset>0x150</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BODRSTLEV</name>
<description>BOD reset level</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_0</name>
<description>Level 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_1</name>
<description>Level 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>Level 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3</name>
<description>Level 3.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODINTVAL</name>
<description>BOD interrupt level</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>Level 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3</name>
<description>Level 3.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODRSTENA</name>
<description>BOD reset enable</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_RESET_FUNCTI</name>
<description>Disable reset function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_RESET_FUNCTIO</name>
<description>Enable reset function.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSTCKCAL</name>
<description>System tick counter calibration</description>
<addressOffset>0x154</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CAL</name>
<description>System tick timer calibration value</description>
<bitRange>[25:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRQLATENCY</name>
<description>IRQ delay. Allows trade-off between interrupt latency and determinism.</description>
<addressOffset>0x170</addressOffset>
<access>read-write</access>
<resetValue>0x00000010</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LATENCY</name>
<description>8-bit latency value</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>NMISRC</name>
<description>NMI Source Control</description>
<addressOffset>0x174</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRQN</name>
<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 6 for the list of interrupt sources and their IRQ numbers.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[30:5]</bitRange>
</field>
<field>
<name>NMIEN</name>
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>PINTSEL%s</name>
<description>GPIO Pin Interrupt Select register 0</description>
<addressOffset>0x178</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTPIN</name>
<description>Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERP0</name>
<description>Start logic 0 interrupt wake-up enable register 0</description>
<addressOffset>0x204</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PINT0</name>
<description>Pin interrupt 0 wake-up</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT1</name>
<description>Pin interrupt 1 wake-up</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT2</name>
<description>Pin interrupt 2 wake-up</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT3</name>
<description>Pin interrupt 3 wake-up</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT4</name>
<description>Pin interrupt 4 wake-up</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT5</name>
<description>Pin interrupt 5 wake-up</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT6</name>
<description>Pin interrupt 6 wake-up</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT7</name>
<description>Pin interrupt 7 wake-up</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>STARTERP1</name>
<description>Start logic 1 interrupt wake-up enable register 1</description>
<addressOffset>0x214</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTCINT</name>
<description>RTC interrupt wake-up</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDT_BODINT</name>
<description>Combined WWDT interrupt or Brown Out Detect (BOD) interrupt wake-up</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[18:14]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>GROUP0INT</name>
<description>GPIO GROUP0 interrupt wake-up</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GROUP1INT</name>
<description>GPIO GROUP1 interrupt wake-up</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>USART1_4</name>
<description>Combined USART1 and USART4 interrupt wake-up</description>
<bitRange>[23:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2_3</name>
<description>Combined USART2 and USART3 interrupt wake-up</description>
<bitRange>[24:24]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDSLEEPCFG</name>
<description>Power-down states in deep-sleep mode</description>
<addressOffset>0x230</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>BOD_PD</name>
<description>BOD power-down control for Deep-sleep and Power-down mode</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>WDTOSC_PD</name>
<description>Watchdog oscillator power-down control for Deep-sleep and Power-down mode</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDAWAKECFG</name>
<description>Power-down states for wake-up from deep-sleep</description>
<addressOffset>0x234</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>IRCOUT_PD</name>
<description>IRC oscillator output wake-up configuration</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRC_PD</name>
<description>IRC oscillator power-down wake-up configuration</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH_PD</name>
<description>Flash wake-up configuration</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD_PD</name>
<description>BOD wake-up configuration</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_PD</name>
<description>ADC wake-up configuration</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSOSC_PD</name>
<description>Crystal oscillator wake-up configuration</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOSC_PD</name>
<description>Watchdog oscillator wake-up configuration</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSPLL_PD</name>
<description>System PLL wake-up configuration</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always write this bit as 0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. This bit must be set to one in Run mode.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>TEMPSENSE_PD</name>
<description>Temperature sensor wake-up configuration</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:14]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDRUNCFG</name>
<description>Power configuration register</description>
<addressOffset>0x238</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>IRCOUT_PD</name>
<description>IRC oscillator output power-down</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRC_PD</name>
<description>IRC oscillator power-down</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH_PD</name>
<description>Flash power-down</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD_PD</name>
<description>BOD power-down</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_PD</name>
<description>ADC power-down</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSOSC_PD</name>
<description>Crystal oscillator power-down. After power-up, add a software delay of approximately 500 us before using.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOSC_PD</name>
<description>Watchdog oscillator power-down</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSPLL_PD</name>
<description>System PLL power-down</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always write this bit as 0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. This bit must be set to one in Run mode.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>TEMPSENSE_PD</name>
<description>Temperature sensor wake-up configuration</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always write these bits as 0b11.</description>
<bitRange>[15:14]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVICE_ID</name>
<description>Device ID</description>
<addressOffset>0x3F4</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>DEVICEID</name>
<description>PARTID</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART4</name>
<description>USART4 </description>
<groupName>USART4</groupName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1_4</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>USART Configuration register. Basic USART configuration settings that typically are not changed during operation.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>USART Enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART is enabled for operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>DATALEN</name>
<description>Selects the data size for the USART.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>7_BIT_DATA_LENGTH</name>
<description>7 bit Data length.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_DATA_LENGTH</name>
<description>8 bit Data length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BIT_DATA_LENGTH</name>
<description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARITYSEL</name>
<description>Selects what type of parity is used by the USART.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_PARITY</name>
<description>No parity.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_PARITY</name>
<description>Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ODD_PARITY</name>
<description>Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPLEN</name>
<description>Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_STOP_BIT</name>
<description>1 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP_BITS</name>
<description>2 stop bits. This setting should only be used for asynchronous communication.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE32K</name>
<description>Selects standard or 32 kHz clocking mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>UART uses standard clocking.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>32KHZ</name>
<description>UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>CTSEN</name>
<description>CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_FLOW_CONTROL</name>
<description>No flow control. The transmitter does not receive any automatic flow control signal.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FLOW_CONTROL_ENABLED</name>
<description>Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>SYNCEN</name>
<description>Selects synchronous or asynchronous operation.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ASYNCHRONOUS</name>
<description>Asynchronous mode is selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCHRONOUS</name>
<description>Synchronous mode is selected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPOL</name>
<description>Selects the clock polarity and sampling edge of received data in synchronous mode.</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Un_RXD is sampled on the falling edge of SCLK.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Un_RXD is sampled on the rising edge of SCLK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>SYNCMST</name>
<description>Synchronous mode Master select.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Master. When synchronous mode is enabled, the USART is a master.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOP</name>
<description>Selects data loopback mode.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL_OPERATION</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOOPBACK_MODE</name>
<description>Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>OETA</name>
<description>Output Enable Turnaround time enable for RS-485 operation.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DEASSERTED</name>
<description>Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ASSERTED</name>
<description>Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOADDR</name>
<description>Automatic Address matching enable.</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OESEL</name>
<description>Output Enable Select.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FLOW_CONTROL</name>
<description>Flow control. The RTS signal is used as the standard flow control function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTPUT_ENABLE</name>
<description>Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OEPOL</name>
<description>Output Enable Polarity.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>Low. If selected by OESEL, the output enable is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. If selected by OESEL, the output enable is active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXPOL</name>
<description>Receive data polarity.</description>
<bitRange>[22:22]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_CHANGED</name>
<description>Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXPOL</name>
<description>Transmit data polarity.</description>
<bitRange>[23:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_CHANGED</name>
<description>Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTL</name>
<description>USART Control register. USART control settings that are more likely to change during operation.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TXBRKEN</name>
<description>Break Enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NORMAL_OPERATION</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS_BREAK_IS</name>
<description>Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADDRDET</name>
<description>Enable address detect mode.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART presents all incoming data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[5:3]</bitRange>
</field>
<field>
<name>TXDIS</name>
<description>Transmit Disable.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_DISABLED</name>
<description>Not disabled. USART transmitter is not disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CC</name>
<description>Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CLOCK_ON_CHARACTER</name>
<description>Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS_CLOCK</name>
<description>Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCCONRX</name>
<description>Clear Continuous Clock.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect on the CC bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_CLEAR</name>
<description>Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[15:10]</bitRange>
</field>
<field>
<name>AUTOBAUD</name>
<description>Autobaud enable.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. UART is in normal operating mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0x000E</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RXIDLE</name>
<description>Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CTS</name>
<description>This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISSTAT</name>
<description>Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1).</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RXBRK</name>
<description>Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver break detection occurs. Cleared by software.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERR</name>
<description>Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDYEN</name>
<description>When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLEEN</name>
<description>When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTSEN</name>
<description>When 1, enables an interrupt when there is a change in the state of the CTS input.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISEN</name>
<description>When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNEN</name>
<description>When 1, enables an interrupt when an overrun error occurred.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRKEN</name>
<description>When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>STARTEN</name>
<description>When 1, enables an interrupt when a received start bit has been detected.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERREN</name>
<description>When 1, enables an interrupt when a framing error has been detected.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERREN</name>
<description>When 1, enables an interrupt when a parity error has been detected.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEEN</name>
<description>When 1, enables an interrupt when noise is detected.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERREN</name>
<description>When 1, enables an interrupt when an auto-baud error occurs.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.</description>
<addressOffset>0x010</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTSCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISINTCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRKCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>STARTCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>RXDAT</name>
<description>Receiver Data register. Contains the last character received.</description>
<addressOffset>0x014</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RXDAT</name>
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>RXDATSTAT</name>
<description>Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<readAction>modify</readAction>
<fields>
<field>
<name>RXDAT</name>
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[12:9]</bitRange>
</field>
<field>
<name>FRAMERR</name>
<description>Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERR</name>
<description>Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISE</name>
<description>Received Noise flag. See description of the RXNOISEINT bit in Table 133.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>TXDAT</name>
<description>Transmit Data register. Data to be transmitted is written here.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.</description>
<bitRange>[8:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Only zero should be written.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>BRG</name>
<description>Baud Rate Generator register. 16-bit integer baud rate divisor value.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BRGVAL</name>
<description>This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status register. Reflects interrupts that are currently enabled.</description>
<addressOffset>0x024</addressOffset>
<access>read-only</access>
<resetValue>0x0005</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter idle status.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state of the CTS input is detected.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>TXDISINT</name>
<description>Transmitter Disabled Interrupt flag.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[10:9]</bitRange>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver break detection occurs.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver input.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ABERR</name>
<description>Auto-baud Error flag.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Oversample selection register for asynchronous communication.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OSRVAL</name>
<description>Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description>Address register for automatic address matching.</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDRESS</name>
<description>8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SSP0">
<name>SSP1</name>
<description>SSP1</description>
<baseAddress>0x40058000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SSP1</name>
<value>14</value>
</interrupt>
</peripheral>
<peripheral>
<name>GINT0</name>
<description>GPIO group interrupt 0</description>
<groupName>GINT0</groupName>
<baseAddress>0x4005C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT0</name>
<value>8</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>GPIO grouped interrupt control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT</name>
<description>Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INTERRUPT_REQUEST</name>
<description>No interrupt request is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERRUPT_REQUEST_IS</name>
<description>Interrupt request is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMB</name>
<description>Combine enabled inputs for group interrupt</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OR_FUNCTIONALITY_A_</name>
<description>OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AND_FUNCTIONALITY_A</name>
<description>AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG</name>
<description>Group interrupt trigger</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EDGE_TRIGGERED</name>
<description>Edge-triggered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_TRIGGERED</name>
<description>Level-triggered</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>PORT_POL[%s]</name>
<displayName>PORT_POL[%s]</displayName>
<description>GPIO grouped interrupt port 0 polarity register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL0</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>POL1</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>POL2</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>POL3</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>POL4</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>POL5</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>POL6</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>POL7</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>POL8</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>POL9</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>POL10</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>POL11</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>POL12</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>POL13</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>POL14</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>POL15</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>POL16</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>POL17</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>POL18</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>POL19</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>POL20</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>POL21</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>POL22</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>POL23</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>POL24</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>POL25</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>POL26</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>POL27</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>POL28</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>POL29</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>POL30</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>POL31</name>
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>PORT_ENA[%s]</name>
<displayName>PORT_ENA[%s]</displayName>
<description>GPIO grouped interrupt port enable register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA0</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENA1</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENA2</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENA3</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENA4</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENA5</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENA6</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENA7</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>ENA8</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ENA9</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>ENA10</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>ENA11</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>ENA12</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>ENA13</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>ENA14</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>ENA15</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ENA16</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>ENA17</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>ENA18</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>ENA19</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>ENA20</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>ENA21</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>ENA22</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>ENA23</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>ENA24</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>ENA25</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>ENA26</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>ENA27</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>ENA28</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>ENA29</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>ENA30</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>ENA31</name>
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GINT0">
<name>GINT1</name>
<description>GINT1</description>
<baseAddress>0x40060000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT1</name>
<value>9</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART4">
<name>USART1</name>
<description>USART1</description>
<baseAddress>0x4006C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral derivedFrom="USART4">
<name>USART2</name>
<description>USART2</description>
<baseAddress>0x40070000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART2_3</name>
<value>12</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART4">
<name>USART3</name>
<description>USART3</description>
<baseAddress>0x40074000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cyclic Redundancy Check (CRC) engine</description>
<groupName>CRC</groupName>
<baseAddress>0x50000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODE</name>
<description>CRC mode register</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_POLY</name>
<description>CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>BIT_RVS_WR</name>
<description>Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CMPL_WR</name>
<description>Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BIT_RVS_SUM</name>
<description>CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CMPL_SUM</name>
<description>CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>Reserved</name>
<description>Always 0 when read</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEED</name>
<description>CRC seed register</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SEED</name>
<description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>SUM</name>
<description>CRC checksum register</description>
<addressOffset>0x08</addressOffset>
<access>read-only</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SUM</name>
<description>The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>WR_DATA</name>
<description>CRC data register</description>
<alternateRegister>SUM</alternateRegister>
<addressOffset>0x08</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CRC_WR_DATA</name>
<description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x50004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA</name>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>DMA control.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>DMA controller master enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The DMA controller is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ACTIVEINT</name>
<description>Summarizes whether any enabled interrupts are pending.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_PENDING</name>
<description>Not pending. No enabled interrupts are pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. At least one enabled interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEERRINT</name>
<description>Summarizes whether any error interrupts are pending.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_PENDING</name>
<description>Not pending. No error interrupts are pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. At least one error interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<name>SRAMBASE</name>
<description>SRAM address of the channel configuration table.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>OFFSET</name>
<description>Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>ENABLESET0</name>
<description>Channel Enable read and Set for all DMA channels.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable for DMA channels 15:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>ENABLECLR0</name>
<description>Channel Enable Clear for all DMA channels.</description>
<addressOffset>0x028</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLR</name>
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
<bitRange>[15:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ACTIVE0</name>
<description>Channel Active status for all DMA channels.</description>
<addressOffset>0x030</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ACT</name>
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>BUSY0</name>
<description>Channel Busy status for all DMA channels.</description>
<addressOffset>0x038</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BSY</name>
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>ERRINT0</name>
<description>Error Interrupt status for all DMA channels.</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERR</name>
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENSET0</name>
<description>Interrupt Enable read and Set for all DMA channels.</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTEN</name>
<description>Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTENCLR0</name>
<description>Interrupt Enable Clear for all DMA channels.</description>
<addressOffset>0x050</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLR</name>
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTA0</name>
<description>Interrupt A status for all DMA channels.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IA</name>
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTB0</name>
<description>Interrupt B status for all DMA channels.</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IB</name>
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SETVALID0</name>
<description>Set ValidPending control bits for all DMA channels.</description>
<addressOffset>0x068</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SV</name>
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SETTRIG0</name>
<description>Set Trigger control bits for all DMA channels.</description>
<addressOffset>0x070</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>TRIG</name>
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>ABORT0</name>
<description>Channel Abort control for all DMA channels.</description>
<addressOffset>0x078</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>AORTCTRL</name>
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-15</dimIndex>
<name>CFG%s</name>
<description>Configuration register for DMA channel 0.</description>
<addressOffset>0x400</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PERIPHREQEN</name>
<description>Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Peripheral DMA requests are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Peripheral DMA requests are enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWTRIGEN</name>
<description>Hardware Triggering Enable for this channel.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Hardware triggering is not used.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Use hardware triggering.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>TRIGPOL</name>
<description>Trigger Polarity. Selects the polarity of a hardware trigger for this channel.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ACTIVE_LOW__FALLING</name>
<description>Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH__RISING</name>
<description>Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGTYPE</name>
<description>Trigger Type. Selects hardware trigger as edge triggered or level triggered.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EDGE</name>
<description>Edge. Hardware trigger is edge triggered.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL</name>
<description>Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGBURST</name>
<description>Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SINGLE_TRANSFER</name>
<description>Single transfer. Hardware trigger causes a single transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BURST_TRANSFER</name>
<description>Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>BURSTPOWER</name>
<description>Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported.</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[13:12]</bitRange>
</field>
<field>
<name>SRCBURSTWRAP</name>
<description>Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Source burst wrapping is not enabled for this DMA channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Source burst wrapping is enabled for this DMA channel.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTBURSTWRAP</name>
<description>Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Destination burst wrapping is not enabled for this DMA channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Destination burst wrapping is enabled for this DMA channel.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHPRIORITY</name>
<description>Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority.</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-15</dimIndex>
<name>CTLSTAT%s</name>
<description>Control and status register for DMA channel 0.</description>
<addressOffset>0x404</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>VALIDPENDING</name>
<description>Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT_ON_DMA_OPE</name>
<description>No effect on DMA operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALID_PENDING</name>
<description>Valid pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>TRIG</name>
<description>Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_TRIGGERED</name>
<description>Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGERED</name>
<description>Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0-15</dimIndex>
<name>XFERCFG%s</name>
<description>Transfer configuration register for DMA channel 0.</description>
<addressOffset>0x408</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CFGVALID</name>
<description>Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_VALID</name>
<description>Not valid. The current channel descriptor is not considered valid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALID</name>
<description>Valid. The current channel descriptor is considered valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RELOAD</name>
<description>Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Reload the channels' control structure when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWTRIG</name>
<description>Software Trigger.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>WHEN_WRITTEN_BY_SOFT</name>
<description>When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WHEN_WRITTEN_BY_SOFT</name>
<description>When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRTRIG</name>
<description>Clear Trigger.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_CLEARED</name>
<description>Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEARED</name>
<description>Cleared. The trigger is cleared when this descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETINTA</name>
<description>Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. The INTA flag for this channel will be set when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETINTB</name>
<description>Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. The INTB flag for this channel will be set when the current descriptor is exhausted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>WIDTH</name>
<description>Transfer width used for this DMA channel.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>8_BIT_TRANSFERS</name>
<description>8-bit transfers are performed (8-bit source reads and destination writes).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>16_BIT_TRANSFERS</name>
<description>16-bit transfers are performed (16-bit source reads and destination writes).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>32_BIT_TRANSFERS</name>
<description>32-bit transfers are performed (32-bit source reads and destination writes).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved setting, do not use.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[11:10]</bitRange>
</field>
<field>
<name>SRCINC</name>
<description>Determines whether the source address is incremented for each DMA transfer.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INCREMENT</name>
<description>No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_X_WIDTH</name>
<description>1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_WIDTH</name>
<description>2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_WIDTH</name>
<description>4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTINC</name>
<description>Determines whether the destination address is incremented for each DMA transfer.</description>
<bitRange>[15:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INCREMENT</name>
<description>No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_X_WIDTH</name>
<description>1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_WIDTH</name>
<description>2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_WIDTH</name>
<description>4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XFERCOUNT</name>
<description>Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.</description>
<bitRange>[25:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Read value is undefined, only zero should be written.</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCT0</name>
<description>State Configurable Timers (SCTimer/PWM)</description>
<groupName>SCT0</groupName>
<baseAddress>0x5000C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SCT0_1</name>
<value>13</value>
</interrupt>
<registers>
<register>
<name>CONFIG</name>
<description>SCT configuration register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00007E00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UNIFY</name>
<description>SCT operation</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_SCT_OPERATES_AS</name>
<description>The SCT operates as two 16-bit counters named L and H.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_SCT_OPERATES_AS</name>
<description>The SCT operates as a unified 32-bit counter.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKMODE</name>
<description>SCT clock mode</description>
<bitRange>[2:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_BUS_CLOCK_CLOCKS</name>
<description>The bus clock clocks the SCT and prescalers.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_SCT_CLOCK_IS_THE</name>
<description>The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_INPUT_SELECTED_B</name>
<description>The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESCALED_SCT_INPUT</name>
<description>Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKSEL</name>
<description>SCT clock select</description>
<bitRange>[6:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RISING_EDGES_ON_INPU</name>
<description>Rising edges on input 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGES_ON_INP</name>
<description>Falling edges on input 0.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGES_ON_INPU</name>
<description>Rising edges on input 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGES_ON_INP</name>
<description>Falling edges on input 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGES_ON_INPU</name>
<description>Rising edges on input 2.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGES_ON_INP</name>
<description>Falling edges on input 2.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGES_ON_INPU</name>
<description>Rising edges on input 3.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGES_ON_INP</name>
<description>Falling edges on input 3.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NORELAOD_L</name>
<description>A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>NORELOAD_H</name>
<description>A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>INSYNC</name>
<description>Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.</description>
<bitRange>[16:9]</bitRange>
</field>
<field>
<name>AUTOLIMIT_L</name>
<description>A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>AUTOLIMIT_H</name>
<description>A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:19]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>SCT control register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0x00040004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOWN_L</name>
<description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>STOP_L</name>
<description>When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>HALT_L</name>
<description>When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CLRCTR_L</name>
<description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BIDIR_L</name>
<description>L or unified counter direction select</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_COUNTER_COUNTS_U</name>
<description>The counter counts up to its limit condition, then is cleared to zero.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_COUNTER_COUNTS_U</name>
<description>The counter counts up to its limit, then counts down to a limit condition or to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRE_L</name>
<description>Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
<bitRange>[12:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[15:13]</bitRange>
</field>
<field>
<name>DOWN_H</name>
<description>This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>STOP_H</name>
<description>When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>HALT_H</name>
<description>When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>CLRCTR_H</name>
<description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>BIDIR_H</name>
<description>Direction select</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_H_COUNTER_COUNTS</name>
<description>The H counter counts up to its limit condition, then is cleared to zero.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_H_COUNTER_COUNTS</name>
<description>The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRE_H</name>
<description>Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
<bitRange>[28:21]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:29]</bitRange>
</field>
</fields>
</register>
<register>
<name>LIMIT</name>
<description>SCT limit register</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LIMMSK_L</name>
<description>If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>LIMMSK_H</name>
<description>If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21).</description>
<bitRange>[21:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>HALT</name>
<description>SCT halt condition register</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HALTMSK_L</name>
<description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>HALTMSK_H</name>
<description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21).</description>
<bitRange>[21:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>STOP</name>
<description>SCT stop condition register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STOPMSK_L</name>
<description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>STOPMSK_H</name>
<description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21).</description>
<bitRange>[21:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>START</name>
<description>SCT start condition register</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STARTMSK_L</name>
<description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>STARTMSK_H</name>
<description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21).</description>
<bitRange>[21:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>SCT counter register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTR_L</name>
<description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>CTR_H</name>
<description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>SCT state register</description>
<addressOffset>0x044</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATE_L</name>
<description>State variable.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:5]</bitRange>
</field>
<field>
<name>STATE_H</name>
<description>State variable.</description>
<bitRange>[20:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<name>INPUT</name>
<description>SCT input register</description>
<addressOffset>0x048</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AIN0</name>
<description>Real-time status of input 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>AIN1</name>
<description>Real-time status of input 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>AIN2</name>
<description>Real-time status of input 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>AIN3</name>
<description>Real-time status of input 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>SIN0</name>
<description>Input 0 state synchronized to the SCT clock.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>SIN1</name>
<description>Input 1 state synchronized to the SCT clock.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SIN2</name>
<description>Input 2 state synchronized to the SCT clock.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>SIN3</name>
<description>Input 3 state synchronized to the SCT clock.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:20]</bitRange>
</field>
</fields>
</register>
<register>
<name>REGMODE</name>
<description>SCT match/capture registers mode register</description>
<addressOffset>0x04C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REGMOD_L</name>
<description>Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:5]</bitRange>
</field>
<field>
<name>REGMOD_H</name>
<description>Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
<bitRange>[20:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:21]</bitRange>
</field>
</fields>
</register>
<register>
<name>OUTPUT</name>
<description>SCT output register</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUT</name>
<description>Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>OUTPUTDIRCTRL</name>
<description>SCT output counter direction control register</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETCLR0</name>
<description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SET_AND_CLEAR_DO_NOT</name>
<description>Set and clear do not depend on any counter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETCLR1</name>
<description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SET_AND_CLEAR_DO_NOT</name>
<description>Set and clear do not depend on any counter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETCLR2</name>
<description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SET_AND_CLEAR_DO_NOT</name>
<description>Set and clear do not depend on any counter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SETCLR3</name>
<description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SET_AND_CLEAR_DO_NOT</name>
<description>Set and clear do not depend on any counter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_AND_CLEAR_ARE_RE</name>
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RES</name>
<description>SCT conflict resolution register</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>O0RES</name>
<description>Effect of simultaneous set and clear on output 0.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT_OR_CLEAR</name>
<description>Set output (or clear based on the SETCLR0 field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT_OR_SET</name>
<description>Clear output (or set based on the SETCLR0 field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O1RES</name>
<description>Effect of simultaneous set and clear on output 1.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT_OR_CLEAR</name>
<description>Set output (or clear based on the SETCLR1 field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT_OR_SET</name>
<description>Clear output (or set based on the SETCLR1 field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O2RES</name>
<description>Effect of simultaneous set and clear on output 2.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT_OR_CLEAR</name>
<description>Set output (or clear based on the SETCLR2 field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT_N_OR_S</name>
<description>Clear output n (or set based on the SETCLR2 field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>O3RES</name>
<description>Effect of simultaneous set and clear on output 3.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT_OR_CLEAR</name>
<description>Set output (or clear based on the SETCLR3 field).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT_OR_SET</name>
<description>Clear output (or set based on the SETCLR3 field).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DMAREQ0</name>
<description>SCT DMA request 0 register</description>
<addressOffset>0x05C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEV_0</name>
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[29:6]</bitRange>
</field>
<field>
<name>DRL0</name>
<description>A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DRQ0</name>
<description>This read-only bit indicates the state of DMA Request 0</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>DMAREQ1</name>
<description>SCT DMA request 1 register</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEV_1</name>
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[29:6]</bitRange>
</field>
<field>
<name>DRL1</name>
<description>A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DRQ1</name>
<description>This read-only bit indicates the state of DMA Request 1.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>EVEN</name>
<description>SCT event enable register</description>
<addressOffset>0x0F0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IEN</name>
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>EVFLAG</name>
<description>SCT event flag register</description>
<addressOffset>0x0F4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLAG</name>
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONEN</name>
<description>SCT conflict enable register</description>
<addressOffset>0x0F8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NCEN</name>
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONFLAG</name>
<description>SCT conflict flag register</description>
<addressOffset>0x0FC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NCFLAG</name>
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[29:4]</bitRange>
</field>
<field>
<name>BUSERRL</name>
<description>The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>BUSERRH</name>
<description>The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-4</dimIndex>
<name>MATCH%s</name>
<description>SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCHn_L</name>
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>MATCHn_H</name>
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-4</dimIndex>
<name>CAP%s</name>
<description>SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1</description>
<alternateRegister>MATCH%s</alternateRegister>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPn_L</name>
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>CAPn_H</name>
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-4</dimIndex>
<name>MATCHREL%s</name>
<description>SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0</description>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELOADn_L</name>
<description>When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RELOADn_H</name>
<description>When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-4</dimIndex>
<name>CAPCTRL%s</name>
<description>SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1</description>
<alternateRegister>MATCHREL%s</alternateRegister>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPCONn_L</name>
<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>CAPCONn_H</name>
<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21).</description>
<bitRange>[21:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:22]</bitRange>
</field>
</fields>
</register>
<register>
<dim>6</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-5</dimIndex>
<name>EV%s_STATE</name>
<description>SCT event state register 0</description>
<addressOffset>0x300</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATEMSKn</name>
<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7).</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<dim>6</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-5</dimIndex>
<name>EV%s_CTRL</name>
<description>SCT event control register 0</description>
<addressOffset>0x304</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCHSEL</name>
<description>Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>HEVENT</name>
<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SELECTS_THE_L_STATE</name>
<description>Selects the L state and the L match register selected by MATCHSEL.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SELECTS_THE_H_STATE</name>
<description>Selects the H state and the H match register selected by MATCHSEL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTSEL</name>
<description>Input/output select</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SELECTS_THE_INPUTS_E</name>
<description>Selects the inputs elected by IOSEL.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SELECTS_THE_OUTPUTS</name>
<description>Selects the outputs selected by IOSEL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOSEL</name>
<description>Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.</description>
<bitRange>[9:6]</bitRange>
</field>
<field>
<name>IOCOND</name>
<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>LOW</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE</name>
<description>Rise</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL</name>
<description>Fall</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>HIGH</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBMODE</name>
<description>Selects how the specified match and I/O condition are used and combined.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OR</name>
<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MATCH</name>
<description>MATCH. Uses the specified match only.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IO</name>
<description>IO. Uses the specified I/O condition only.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>AND</name>
<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATELD</name>
<description>This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STATEV_VALUE_IS_ADDE</name>
<description>STATEV value is added into STATE (the carry-out is ignored).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATEV_VALUE_IS_LOAD</name>
<description>STATEV value is loaded into STATE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATEV</name>
<description>This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.</description>
<bitRange>[19:15]</bitRange>
</field>
<field>
<name>MATCHMEM</name>
<description>If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>DIRECTION</name>
<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>
<bitRange>[22:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DIRECTION_INDEPENDEN</name>
<description>Direction independent. This event is triggered regardless of the count direction.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTING_UP</name>
<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTING_DOWN</name>
<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:23]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>OUT%s_SET</name>
<description>SCT output 0 set register</description>
<addressOffset>0x500</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SET</name>
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>OUT%s_CLR</name>
<description>SCT output 0 clear register</description>
<addressOffset>0x504</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLR</name>
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SCT0">
<name>SCT1</name>
<description>SCT1</description>
<baseAddress>0x5000E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>GPIO_PORT</name>
<description>General Purpose I/O (GPIO) </description>
<groupName>GPIO</groupName>
<baseAddress>0xA0000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3FFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>88</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0-87</dimIndex>
<name>B[%s]</name>
<displayName>B[%s]</displayName>
<description>Byte pin registers</description>
<addressOffset>0x0000</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>88</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-87</dimIndex>
<name>W[%s]</name>
<displayName>W[%s]</displayName>
<description>Word pin registers </description>
<addressOffset>0x1000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>DIR[%s]</name>
<displayName>DIR[%s]</displayName>
<description>Port Direction registers </description>
<addressOffset>0x2000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIRP0</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>DIRP1</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>DIRP2</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>DIRP3</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>DIRP4</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DIRP5</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>DIRP6</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>DIRP7</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>DIRP8</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>DIRP9</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>DIRP10</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>DIRP11</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>DIRP12</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>DIRP13</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>DIRP14</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>DIRP15</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>DIRP16</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>DIRP17</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>DIRP18</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>DIRP19</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>DIRP20</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>DIRP21</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>DIRP22</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>DIRP23</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>DIRP24</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>DIRP25</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>DIRP26</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>DIRP27</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>DIRP28</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>DIRP29</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>DIRP30</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DIRP31</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>MASK[%s]</name>
<displayName>MASK[%s]</displayName>
<description>Port Mask register </description>
<addressOffset>0x2080</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASKP0</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MASKP1</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MASKP2</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MASKP3</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MASKP4</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>MASKP5</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MASKP6</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>MASKP7</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MASKP8</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>MASKP9</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MASKP10</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>MASKP11</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>MASKP12</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>MASKP13</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>MASKP14</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>MASKP15</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MASKP16</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MASKP17</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>MASKP18</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MASKP19</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MASKP20</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>MASKP21</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>MASKP22</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>MASKP23</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>MASKP24</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>MASKP25</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>MASKP26</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>MASKP27</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>MASKP28</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>MASKP29</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MASKP30</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>MASKP31</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>PIN[%s]</name>
<displayName>PIN[%s]</displayName>
<description>Port pin register </description>
<addressOffset>0x2100</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PORT0</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PORT1</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PORT2</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PORT3</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PORT4</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PORT5</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PORT6</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PORT7</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>PORT8</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>PORT9</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>PORT10</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>PORT11</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>PORT12</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>PORT13</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PORT14</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>PORT15</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>PORT16</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>PORT17</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>PORT18</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>PORT19</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>PORT20</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>PORT21</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>PORT22</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>PORT23</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>PORT24</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>PORT25</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>PORT26</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>PORT27</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>PORT28</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>PORT29</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>PORT30</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>PORT31</name>
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>MPIN[%s]</name>
<displayName>MPIN[%s]</displayName>
<description>Masked port register </description>
<addressOffset>0x2180</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>MPORTP0</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MPORTP1</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MPORTP2</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MPORTP3</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MPORTP4</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>MPORTP5</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MPORTP6</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>MPORTP7</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MPORTP8</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>MPORTP9</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MPORTP10</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>MPORTP11</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>MPORTP12</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>MPORTP13</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>MPORTP14</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>MPORTP15</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MPORTP16</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MPORTP17</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>MPORTP18</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MPORTP19</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MPORTP20</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>MPORTP21</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>MPORTP22</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>MPORTP23</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>MPORTP24</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>MPORTP25</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>MPORTP26</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>MPORTP27</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>MPORTP28</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>MPORTP29</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MPORTP30</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>MPORTP31</name>
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>SET[%s]</name>
<displayName>SET[%s]</displayName>
<description>Write: Set port register Read: port output bits </description>
<addressOffset>0x2200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETP00</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETP01</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETP02</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETP03</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETP04</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETP05</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETP06</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETP07</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SETP08</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>SETP09</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>SETP010</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>SETP011</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>SETP012</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>SETP013</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>SETP014</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>SETP015</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>SETP016</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>SETP017</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SETP018</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>SETP019</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>SETP020</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>SETP021</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>SETP022</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>SETP023</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>SETP024</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SETP025</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>SETP026</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>SETP027</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SETP028</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>SETP029</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>SETP030</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>SETP031</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>CLR[%s]</name>
<displayName>CLR[%s]</displayName>
<description>Clear port</description>
<addressOffset>0x2280</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLRP00</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CLRP01</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CLRP02</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CLRP03</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CLRP04</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CLRP05</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CLRP06</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CLRP07</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CLRP08</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>CLRP09</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>CLRP010</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>CLRP011</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>CLRP012</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>CLRP013</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>CLRP014</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>CLRP015</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>CLRP016</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>CLRP017</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>CLRP018</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>CLRP019</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>CLRP020</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>CLRP021</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>CLRP022</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>CLRP023</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>CLRP024</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>CLRP025</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>CLRP026</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>CLRP027</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>CLRP028</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>CLRP029</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>CLRP030</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>CLRP031</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-2</dimIndex>
<name>NOT[%s]</name>
<displayName>NOT[%s]</displayName>
<description>Toggle port </description>
<addressOffset>0x2300</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>NOTP00</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>NOTP01</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>NOTP02</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>NOTP03</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>NOTP04</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>NOTP05</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>NOTP06</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>NOTP07</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>NOTP08</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>NOTP09</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>NOTP010</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>NOTP011</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>NOTP012</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>NOTP013</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>NOTP014</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>NOTP015</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>NOTP016</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>NOTP017</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>NOTP018</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>NOTP019</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>NOTP020</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>NOTP021</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>NOTP022</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>NOTP023</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>NOTP024</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>NOTP025</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>NOTP026</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>NOTP027</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>NOTP028</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>NOTP029</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>NOTP030</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>NOTP031</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PINT</name>
<description> Pin interrupt
and pattern match (PINT) </description>
<groupName>PINT</groupName>
<baseAddress>0xA0004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIN_INT0</name>
<value>0</value>
</interrupt>
<interrupt>
<name>PIN_INT1</name>
<value>1</value>
</interrupt>
<interrupt>
<name>PIN_INT2</name>
<value>2</value>
</interrupt>
<interrupt>
<name>PIN_INT3</name>
<value>3</value>
</interrupt>
<interrupt>
<name>PIN_INT4</name>
<value>4</value>
</interrupt>
<interrupt>
<name>PIN_INT5</name>
<value>5</value>
</interrupt>
<interrupt>
<name>PIN_INT6</name>
<value>6</value>
</interrupt>
<interrupt>
<name>PIN_INT7</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>ISEL</name>
<description>Pin Interrupt Mode register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMODE0</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PMODE1</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PMODE2</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PMODE3</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PMODE4</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PMODE5</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PMODE6</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PMODE7</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENR</name>
<description>Pin interrupt level or rising edge interrupt enable register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENRL0</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENRL1</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENRL2</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENRL3</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENRL4</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENRL5</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENRL6</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENRL7</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENR</name>
<description>Pin interrupt level or rising edge interrupt set register</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENRL0</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETENRL1</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETENRL2</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETENRL3</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETENRL4</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETENRL5</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETENRL6</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETENRL7</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENR</name>
<description>Pin interrupt level (rising edge interrupt) clear register</description>
<addressOffset>0x00C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENRL0</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CENRL1</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CENRL2</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CENRL3</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CENRL4</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CENRL5</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CENRL6</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CENRL7</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENF</name>
<description>Pin interrupt active level or falling edge interrupt enable register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENAF0</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENAF1</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENAF2</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENAF3</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENAF4</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENAF5</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENAF6</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENAF7</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENF</name>
<description>Pin interrupt active level or falling edge interrupt set register</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENAF0</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETENAF1</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETENAF2</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETENAF3</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETENAF4</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETENAF5</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETENAF6</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETENAF7</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENF</name>
<description>Pin interrupt active level or falling edge interrupt clear register</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENAF0</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CENAF1</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CENAF2</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CENAF3</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CENAF4</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CENAF5</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CENAF6</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CENAF7</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RISE</name>
<description>Pin interrupt rising edge register</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDET0</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RDET1</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RDET2</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RDET3</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RDET4</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RDET5</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RDET6</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RDET7</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FALL</name>
<description>Pin interrupt falling edge register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FDET0</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>FDET1</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>FDET2</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>FDET3</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>FDET4</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>FDET5</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>FDET6</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>FDET7</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IST</name>
<description>Pin interrupt status register</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PSTAT0</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PSTAT1</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PSTAT2</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PSTAT3</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PSTAT4</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PSTAT5</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PSTAT6</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PSTAT7</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Pattern match interrupt control register</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL_PMATCH</name>
<description>Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIN_INTERRUPT_INTER</name>
<description>Pin interrupt. Interrupts are driven in response to the standard pin interrupt function</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PATTERN_MATCH_INTER</name>
<description>Pattern match. Interrupts are driven in response to pattern matches.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENA_RXEV</name>
<description>Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED_RXEV_OUTPU</name>
<description>Disabled. RXEV output to the cpu is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED_RXEV_OUTPUT</name>
<description>Enabled. RXEV output to the cpu is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write 1s to unused bits.</description>
<bitRange>[23:2]</bitRange>
</field>
<field>
<name>PMAT</name>
<description>This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>PMSRC</name>
<description>Pattern match interrupt bit-slice source register</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Reserved</name>
<description>Software should not write 1s to unused bits.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>SRC0</name>
<description>Selects the input source for bit slice 0</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC1</name>
<description>Selects the input source for bit slice 1</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 1.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 1.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 1.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 1.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC2</name>
<description>Selects the input source for bit slice 2</description>
<bitRange>[16:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 2.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 2.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 2.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 2.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 2.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 2.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC3</name>
<description>Selects the input source for bit slice 3</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 3.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 3.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 3.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 3.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 3.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 3.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 3.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC4</name>
<description>Selects the input source for bit slice 4</description>
<bitRange>[22:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 4.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 4.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 4.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 4.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 4.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 4.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC5</name>
<description>Selects the input source for bit slice 5</description>
<bitRange>[25:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 5.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 5.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 5.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 5.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 5.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 5.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 5.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC6</name>
<description>Selects the input source for bit slice 6</description>
<bitRange>[28:26]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 6.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 6.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 6.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 6.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 6.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 6.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 6.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 6.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC7</name>
<description>Selects the input source for bit slice 7</description>
<bitRange>[31:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_0_SELECTS_PIN</name>
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 7.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_1_SELECTS_PIN</name>
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 7.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_2_SELECTS_PIN</name>
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 7.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_3_SELECTS_PIN</name>
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 7.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_4_SELECTS_PIN</name>
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 7.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_5_SELECTS_PIN</name>
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 7.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_6_SELECTS_PIN</name>
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 7.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_7_SELECTS_PIN</name>
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 7.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCFG</name>
<description>Pattern match interrupt bit slice configuration register</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PROD_ENDPTS</name>
<description>A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice).</description>
<bitRange>[6:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Bit slice 7 is automatically considered a product end point.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CFG0</name>
<description>Specifies the match contribution condition for bit slice 0.</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG1</name>
<description>Specifies the match contribution condition for bit slice 1.</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG2</name>
<description>Specifies the match contribution condition for bit slice 2.</description>
<bitRange>[16:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG3</name>
<description>Specifies the match contribution condition for bit slice 3.</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG4</name>
<description>Specifies the match contribution condition for bit slice 4.</description>
<bitRange>[22:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG5</name>
<description>Specifies the match contribution condition for bit slice 5.</description>
<bitRange>[25:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG6</name>
<description>Specifies the match contribution condition for bit slice 6.</description>
<bitRange>[28:26]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG7</name>
<description>Specifies the match contribution condition for bit slice 7.</description>
<bitRange>[31:29]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONSTANT_HIGH_THIS_</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGEMA</name>
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE_</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_OR_FAL</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL_MATCH_F</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL_MATCH_OCC</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_0_THIS_BIT</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT_NON_STICKY_RI</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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