RMUL2025/lib/cmsis_svd/data/Freescale/MKM14ZA5.svd

42331 lines
1.6 MiB
Executable File

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<vendor>Freescale Semiconductor, Inc.</vendor>
<vendorID>Freescale</vendorID>
<series>Kinetis_M</series>
<name>MKM14ZA5</name>
<version>1.6</version>
<description>MKM14ZA5 Freescale Microcontroller</description>
<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
<cpu>
<name>CM0PLUS</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<mpuPresent>false</mpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>FTFA_FlashConfig</name>
<description>Flash configuration field</description>
<prependToName>NV_</prependToName>
<baseAddress>0x400</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>BACKKEY3</name>
<description>Backdoor Comparison Key 3.</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY2</name>
<description>Backdoor Comparison Key 2.</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY1</name>
<description>Backdoor Comparison Key 1.</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY0</name>
<description>Backdoor Comparison Key 0.</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY7</name>
<description>Backdoor Comparison Key 7.</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY6</name>
<description>Backdoor Comparison Key 6.</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY5</name>
<description>Backdoor Comparison Key 5.</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY4</name>
<description>Backdoor Comparison Key 4.</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT3</name>
<description>Non-volatile P-Flash Protection 1 - Low Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT2</name>
<description>Non-volatile P-Flash Protection 1 - High Register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT1</name>
<description>Non-volatile P-Flash Protection 0 - Low Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT0</name>
<description>Non-volatile P-Flash Protection 0 - High Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Non-volatile Flash Security Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Non-volatile Flash Option Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LPBOOT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low-power boot</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Normal boot</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NMI_EN</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>NMI interrupts are always blocked</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>NMI_b pin/interrupts reset default to enabled</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXE_MODE</name>
<description>no description available</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Execution Mode is RUN Mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Execution Mode is VLPR Mode</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK_SRC</name>
<description>no description available</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Externally supplied clock used by Flash</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Internal clock source used by Flash</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AIPS</name>
<description>AIPS-Lite Bridge</description>
<prependToName>AIPS_</prependToName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x20</offset>
<size>0x50</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PACRA</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRB</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRE</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRF</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRG</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRH</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRI</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRJ</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRK</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRL</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRM</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRN</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRO</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PACRP</name>
<description>Peripheral Access Control Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AC7</name>
<description>Attribute Check</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO7</name>
<description>Read Only</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC6</name>
<description>Attribute Check</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO6</name>
<description>Read Only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC5</name>
<description>Attribute Check</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO5</name>
<description>Read Only</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC4</name>
<description>Attribute Check</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO4</name>
<description>Read Only</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC3</name>
<description>Attribute Check</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO3</name>
<description>Read Only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC2</name>
<description>Attribute Check</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO2</name>
<description>Read Only</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC1</name>
<description>Attribute Check</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO1</name>
<description>Read Only</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AC0</name>
<description>Attribute Check</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RO0</name>
<description>Read Only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to corresponding AC field are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to corresponding AC field are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA</name>
<description>DMA Controller</description>
<prependToName>DMA_</prependToName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0x100</offset>
<size>0x40</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA0</name>
<value>0</value>
</interrupt>
<interrupt>
<name>DMA1</name>
<value>1</value>
</interrupt>
<interrupt>
<name>DMA2</name>
<value>2</value>
</interrupt>
<interrupt>
<name>DMA3</name>
<value>3</value>
</interrupt>
<registers>
<register>
<name>SAR0</name>
<description>Source Address Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>SAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR0</name>
<description>Destination Address Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>DAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR0</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>BCR</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR0</name>
<description>DMA_DSR0 register.</description>
<addressOffset>0x10B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR0</name>
<description>DMA Control Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UMNSM</name>
<description>User Mode, Nonsecure Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Channel attributes are set to the current mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHACR</name>
<description>Channel Access Control</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR1</name>
<description>Source Address Register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>SAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR1</name>
<description>Destination Address Register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>DAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR1</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>BCR</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR1</name>
<description>DMA_DSR1 register.</description>
<addressOffset>0x11B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR1</name>
<description>DMA Control Register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UMNSM</name>
<description>User Mode, Nonsecure Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Channel attributes are set to the current mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHACR</name>
<description>Channel Access Control</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR2</name>
<description>Source Address Register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>SAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR2</name>
<description>Destination Address Register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>DAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR2</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>BCR</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR2</name>
<description>DMA_DSR2 register.</description>
<addressOffset>0x12B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR2</name>
<description>DMA Control Register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UMNSM</name>
<description>User Mode, Nonsecure Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Channel attributes are set to the current mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHACR</name>
<description>Channel Access Control</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR3</name>
<description>Source Address Register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>SAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR3</name>
<description>Destination Address Register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>DAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR3</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>BCR</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR3</name>
<description>DMA_DSR3 register.</description>
<addressOffset>0x13B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR3</name>
<description>DMA Control Register</description>
<addressOffset>0x13C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UMNSM</name>
<description>User Mode, Nonsecure Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Channel attributes are set to the current mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHACR</name>
<description>Channel Access Control</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory protection unit</description>
<prependToName>MPU_</prependToName>
<baseAddress>0x4000A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x820</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CESR</name>
<description>Control/Error Status Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x812001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VLD</name>
<description>Valid</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MPU is disabled. All accesses from all bus masters are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MPU is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NRGD</name>
<description>Number Of Region Descriptors</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>8 region descriptors</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>12 region descriptors</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>16 region descriptors</description>
<value>#0010</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSP</name>
<description>Number Of Slave Ports</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HRL</name>
<description>Hardware Revision Level</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SPERR</name>
<description>Slave Port n Error</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No error has occurred for slave port n.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An error has occurred for slave port n.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>EAR%s</name>
<description>Error Address Register, slave port n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EADDR</name>
<description>Error Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>EDR%s</name>
<description>Error Detail Register, slave port n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERW</name>
<description>Error Read/Write</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EATTR</name>
<description>Error Attributes</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User mode, instruction access</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User mode, data access</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Supervisor mode, instruction access</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Supervisor mode, data access</description>
<value>#011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMN</name>
<description>Error Master Number</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPID</name>
<description>Error Process Identification</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EACD</name>
<description>Error Access Control Detail</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>RGD%s_WORD0</name>
<description>Region Descriptor n, Word 0</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SRTADDR</name>
<description>Start Address</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>RGD%s_WORD1</name>
<description>Region Descriptor n, Word 1</description>
<addressOffset>0x404</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENDADDR</name>
<description>End Address</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>RGD%s_WORD2</name>
<description>Region Descriptor n, Word 2</description>
<addressOffset>0x408</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x61F7DF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>M0UM</name>
<description>Bus Master 0 User Mode Access Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M0SM</name>
<description>Bus Master 0 Supervisor Mode Access Control</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M0PE</name>
<description>Bus Master 0 Process Identifier enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1UM</name>
<description>Bus Master 1 User Mode Access Control</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1SM</name>
<description>Bus Master 1 Supervisor Mode Access Control</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1PE</name>
<description>Bus Master 1 Process Identifier enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2UM</name>
<description>Bus Master 2 User Mode Access control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2SM</name>
<description>Bus Master 2 Supervisor Mode Access Control</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2PE</name>
<description>Bus Master 2 Process Identifier Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M3UM</name>
<description>Bus Master 3 User Mode Access Control</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Allows the given access type to occur</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3SM</name>
<description>Bus Master 3 Supervisor Mode Access Control</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>r/w/x; read, write and execute allowed</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>r/x; read and execute allowed, but no write</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>r/w; read and write allowed, but no execute</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Same as User mode defined in M3UM</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3PE</name>
<description>Bus Master 3 Process Identifier Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the process identifier in the evaluation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4WE</name>
<description>Bus Master 4 Write Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 4 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 4 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4RE</name>
<description>Bus Master 4 Read Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 4 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 4 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5WE</name>
<description>Bus Master 5 Write Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 5 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 5 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5RE</name>
<description>Bus Master 5 Read Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 5 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 5 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6WE</name>
<description>Bus Master 6 Write Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 6 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 6 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6RE</name>
<description>Bus Master 6 Read Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 6 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 6 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7WE</name>
<description>Bus Master 7 Write Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 7 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 7 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7RE</name>
<description>Bus Master 7 Read Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 7 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 7 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>RGD%s_WORD3</name>
<description>Region Descriptor n, Word 3</description>
<addressOffset>0x40C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VLD</name>
<description>Valid</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Region descriptor is invalid</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Region descriptor is valid</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIDMASK</name>
<description>Process Identifier Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PID</name>
<description>Process Identifier</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>RGDAAC%s</name>
<description>Region Descriptor Alternate Access Control n</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x61F7DF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>M0UM</name>
<description>Bus Master 0 User Mode Access Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M0SM</name>
<description>Bus Master 0 Supervisor Mode Access Control</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M0PE</name>
<description>Bus Master 0 Process Identifier Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1UM</name>
<description>Bus Master 1 User Mode Access Control</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1SM</name>
<description>Bus Master 1 Supervisor Mode Access Control</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M1PE</name>
<description>Bus Master 1 Process Identifier Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2UM</name>
<description>Bus Master 2 User Mode Access Control</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2SM</name>
<description>Bus Master 2 Supervisor Mode Access Control</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M2PE</name>
<description>Bus Master 2 Process Identifier Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M3UM</name>
<description>Bus Master 3 User Mode Access Control</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Allows the given access type to occur</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3SM</name>
<description>Bus Master 3 Supervisor Mode Access Control</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>r/w/x; read, write and execute allowed</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>r/x; read and execute allowed, but no write</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>r/w; read and write allowed, but no execute</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Same as User mode defined in M3UM</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3PE</name>
<description>Bus Master 3 Process Identifier Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the process identifier in the evaluation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4WE</name>
<description>Bus Master 4 Write Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 4 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 4 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4RE</name>
<description>Bus Master 4 Read Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 4 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 4 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5WE</name>
<description>Bus Master 5 Write Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 5 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 5 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5RE</name>
<description>Bus Master 5 Read Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 5 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 5 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6WE</name>
<description>Bus Master 6 Write Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 6 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 6 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6RE</name>
<description>Bus Master 6 Read Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 6 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 6 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7WE</name>
<description>Bus Master 7 Write Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 7 writes terminate with an access error and the write is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 7 writes allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7RE</name>
<description>Bus Master 7 Read Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus master 7 reads terminate with an access error and the read is not performed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus master 7 reads allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTFA</name>
<description>Flash Memory Interface</description>
<prependToName>FTFA_</prependToName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTFA</name>
<value>13</value>
</interrupt>
<registers>
<register>
<name>FSTAT</name>
<description>Flash Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MGSTAT0</name>
<description>Memory Controller Command Completion Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FPVIOL</name>
<description>Flash Protection Violation Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No protection violation detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Protection violation detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCERR</name>
<description>Flash Access Error Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No access error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLERR</name>
<description>Flash Read Collision Error Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No collision error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Collision error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIF</name>
<description>Command Complete Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash command in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash command has completed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCNFG</name>
<description>Flash Configuration Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ERSSUSP</name>
<description>Erase Suspend</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No suspend requested</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Suspend the current Erase Flash Sector command execution.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERSAREQ</name>
<description>Erase All Request</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request or request complete</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLLIE</name>
<description>Read Collision Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read collision error interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIE</name>
<description>Command Complete Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Command complete interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Flash Security Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCU security status is secure.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCU security status is secure.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Freescale factory access granted</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Freescale factory access denied</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>Mass Erase Enable Bits</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Mass erase is enabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mass erase is enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Backdoor key access disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Flash Option Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>OPT</name>
<description>Nonvolatile Option</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
<name>FCCOB%s</name>
<description>Flash Common Command Object Registers</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CCOBn</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0</dimIndex>
<name>FPROT%s</name>
<description>Program Flash Protection Registers</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PROT</name>
<description>Program Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Program flash region is protected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Program flash region is not protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX0</name>
<description>DMA channel multiplexor</description>
<groupName>DMAMUX</groupName>
<prependToName>DMAMUX0_</prependToName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CHCFG</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX1</name>
<description>DMA channel multiplexor</description>
<groupName>DMAMUX</groupName>
<prependToName>DMAMUX1_</prependToName>
<baseAddress>0x40022000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CHCFG</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX2</name>
<description>DMA channel multiplexor</description>
<groupName>DMAMUX</groupName>
<prependToName>DMAMUX2_</prependToName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CHCFG</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX3</name>
<description>DMA channel multiplexor</description>
<groupName>DMAMUX</groupName>
<prependToName>DMAMUX3_</prependToName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CHCFG</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RNG</name>
<description>Random Number Generator Accelerator</description>
<prependToName>RNG_</prependToName>
<baseAddress>0x40029000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<description>RNGA Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GO</name>
<description>Go</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HA</name>
<description>High Assurance</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTM</name>
<description>Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not masked</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Masked</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRI</name>
<description>Clear Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLP</name>
<description>Sleep</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sleep (low-power) mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>RNGA Status Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SECV</name>
<description>Security Violation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No security violation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Security violation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRS</name>
<description>Last Read Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Underflow</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORU</name>
<description>Output Register Underflow</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Underflow</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERRI</name>
<description>Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Underflow</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLP</name>
<description>Sleep</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sleep (low-power) mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OREG_LVL</name>
<description>Output Register Level</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No words (empty)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One word (valid)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OREG_SIZE</name>
<description>Output Register Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>1</name>
<description>One word (this value is fixed)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ER</name>
<description>RNGA Entropy Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXT_ENT</name>
<description>External Entropy</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>OR</name>
<description>RNGA Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RANDOUT</name>
<description>Random Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC</name>
<description>Analog-to-Digital Converter</description>
<prependToName>ADC_</prependToName>
<baseAddress>0x4002B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x60</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC</name>
<value>16</value>
</interrupt>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B,C,D</dimIndex>
<name>SC1%s</name>
<description>ADC Status and Control Registers 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADCH</name>
<description>Input channel select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>AD0 is selected as input.</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>AD1 is selected as input.</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>AD2 is selected as input.</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>AD3 is selected as input.</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>AD4 is selected as input.</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>AD5 is selected as input.</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>AD6 is selected as input.</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>AD7 is selected as input.</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>AD8 is selected as input.</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>AD9 is selected as input.</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>AD10 is selected as input.</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>AD11 is selected as input.</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>AD12 is selected as input.</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>AD13 is selected as input.</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>AD14 is selected as input.</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>AD15 is selected as input.</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>AD16 is selected as input.</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>AD17 is selected as input.</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>AD18 is selected as input.</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>AD19 is selected as input.</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>AD20 is selected as input.</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>AD21 is selected as input.</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>AD22 is selected as input.</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>AD23 is selected as input.</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>Temp Sensor (single-ended) is selected as input.</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>Bandgap (single-ended) is selected as input.</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Module is disabled.</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AIEN</name>
<description>Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion complete interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion complete interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COCO</name>
<description>Conversion Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion is not completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion is completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG1</name>
<description>ADC Configuration Register 1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADICLK</name>
<description>Input Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bus clock divided by 2(BUSCLK/DIV2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Alternate clock (ALTCLK)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Asynchronous clock (ADACK)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Conversion mode selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>It is single-ended 8-bit conversion.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>It is single-ended 12-bit conversion .</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>It is single-ended 10-bit conversion.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>It is single-ended 16-bit conversion..</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLSMP</name>
<description>Sample Time Configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Short sample time.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Long sample time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADIV</name>
<description>Clock Divide Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The divide ratio is 1 and the clock rate is input clock.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLPC</name>
<description>Low-Power Configuration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal power configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<description>ADC Configuration Register 2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADLSTS</name>
<description>Long Sample Time Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADHSC</name>
<description>High-Speed Configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal conversion sequence selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACKEN</name>
<description>Asynchronous Clock Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUXSEL</name>
<description>ADC Mux Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADxxa channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADxxb channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B,C,D</dimIndex>
<name>R%s</name>
<description>ADC Data Result Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>D</name>
<description>Data result</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1,2</dimIndex>
<name>CV%s</name>
<description>Compare Value Registers</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CV</name>
<description>Compare Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC2</name>
<description>Status and Control Register 2</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REFSEL</name>
<description>Voltage Reference Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Internal bandgap reference and associated ground reference (V BGH and V BGL ). Consult the Chip Configuration information for details specific to this MCU.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACREN</name>
<description>Compare Function Range Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range function disabled. Only CV1 is compared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFGT</name>
<description>Compare Function Greater Than Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFE</name>
<description>Compare Function Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADTRG</name>
<description>Conversion Trigger Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACT</name>
<description>Conversion Active</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion not in progress.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion in progress.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC3</name>
<description>Status and Control Register 3</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AVGS</name>
<description>Hardware Average Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>4 samples averaged.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8 samples averaged.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16 samples averaged.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>32 samples averaged.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVGE</name>
<description>Hardware Average Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware average function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware average function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCO</name>
<description>Continuous Conversion Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALF</name>
<description>Calibration Failed Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Calibration completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAL</name>
<description>Calibration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OFS</name>
<description>ADC Offset Correction Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFS</name>
<description>Offset Error Correction Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PG</name>
<description>ADC Plus-Side Gain Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PG</name>
<description>Plus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPD</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPS</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP4</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP3</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP2</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP1</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP0</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PIT0</name>
<description>Periodic Interrupt Timer</description>
<groupName>PIT</groupName>
<prependToName>PIT0_</prependToName>
<baseAddress>0x4002D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x120</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIT0_PIT1</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>PIT Module Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timers continue to run in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timers are stopped in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable - (PIT section)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock for standard PIT timers is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock for standard PIT timers is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>LDVAL%s</name>
<description>Timer Load Value Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSV</name>
<description>Timer Start Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CVAL%s</name>
<description>Current Timer Value Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TVL</name>
<description>Current Timer Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TCTRL%s</name>
<description>Timer Control Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer n is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer n is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt requests from Timer n are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt will be requested whenever TIF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHN</name>
<description>Chain Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not chained.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TFLG%s</name>
<description>Timer Flag Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout has not yet occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PIT1</name>
<description>Periodic Interrupt Timer</description>
<groupName>PIT</groupName>
<prependToName>PIT1_</prependToName>
<baseAddress>0x4002E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x120</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIT0_PIT1</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>PIT Module Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timers continue to run in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timers are stopped in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable - (PIT section)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock for standard PIT timers is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock for standard PIT timers is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>LDVAL%s</name>
<description>Timer Load Value Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSV</name>
<description>Timer Start Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CVAL%s</name>
<description>Current Timer Value Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TVL</name>
<description>Current Timer Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TCTRL%s</name>
<description>Timer Control Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer n is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer n is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt requests from Timer n are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt will be requested whenever TIF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHN</name>
<description>Chain Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not chained.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TFLG%s</name>
<description>Timer Flag Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout has not yet occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AFE</name>
<description>Analog Front End</description>
<prependToName>AFE_</prependToName>
<baseAddress>0x40030000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x60</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AFE_CH0</name>
<value>21</value>
</interrupt>
<interrupt>
<name>AFE_CH1</name>
<value>22</value>
</interrupt>
<interrupt>
<name>AFE_CH2</name>
<value>23</value>
</interrupt>
<interrupt>
<name>AFE_CH3</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>CH0_CFR</name>
<description>Channel0 Configuration Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HW_TRG</name>
<description>Hardware Trigger Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger select</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger select</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_INP_SEL</name>
<description>Decimator Clock Input Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>On the chip modulator clock will be used</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_EDGE_SEL</name>
<description>Decimator Clock Edge Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Posedge will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Negedge will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CC</name>
<description>Continuous Conversion/Single Conversion Mode Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion following a triggering event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions following a triggering event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_EN</name>
<description>Decimation Filter enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Decimation filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Decimation filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SD_MOD_EN</name>
<description>Sigma Delta Modulator enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SD ADC1 is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SD ADC1 is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYP_MODE</name>
<description>AFE Channel bypass mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bypass mode where ADC and PGA of the appropriate channel are disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PGA_GAIN_SEL</name>
<description>PGA Gain Select</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>001</name>
<description>1x (default)</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2x</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>4x</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>8x</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>16x</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>32x</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PGA_EN</name>
<description>PGA enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PGA disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PGA enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_OSR</name>
<description>Decimator OverSampling Ratio select</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>64</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>128</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>256</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>512</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>1024</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>2048</description>
<value>#101</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CH1_CFR</name>
<description>Channel1 Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HW_TRG</name>
<description>Hardware Trigger Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger select</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger select</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_INP_SEL</name>
<description>Decimator Clock Input Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>On the chip modulator clock will be used</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_EDGE_SEL</name>
<description>Decimator Clock Edge Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Posedge will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Negedge will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CC</name>
<description>Continuous Conversion/Single Conversion Mode Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion following a triggering event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions following a triggering event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_EN</name>
<description>Decimation Filter enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Decimation filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Decimation filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SD_MOD_EN</name>
<description>Sigma Delta Modulator enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SD ADC1 is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SD ADC1 is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYP_MODE</name>
<description>AFE Channel bypass mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bypass mode where ADC and PGA of the appropriate channel are disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PGA_GAIN_SEL</name>
<description>PGA Gain Select</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>001</name>
<description>1x (default)</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2x</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>4x</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>8x</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>16x</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>32x</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PGA_EN</name>
<description>PGA enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PGA disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PGA enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_OSR</name>
<description>Decimator OverSampling Ratio select</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>64</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>128</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>256</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>512</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>1024</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>2048</description>
<value>#101</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CH2_CFR</name>
<description>Channel2 Configuration Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HW_TRG</name>
<description>Hardware Trigger Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger select</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger select</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_INP_SEL</name>
<description>Decimator Clock Input Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>On the chip modulator clock will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_EDGE_SEL</name>
<description>Decimator Clock Edge Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Posedge will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Negedge will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CC</name>
<description>Continuous Conversion/Single Conversion Mode Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion following a triggering event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions following a triggering event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_EN</name>
<description>Decimation Filter enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Decimation filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Decimation filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SD_MOD_EN</name>
<description>Sigma Delta Modulator enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SD ADC3 is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SD ADC3 is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYP_MODE</name>
<description>AFE Channel bypass mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bypass mode where ADC and PGA of the appropriate channel are disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_OSR</name>
<description>Decimator OverSampling Ratio select</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>64</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>128</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>256</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>512</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>1024</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>2048</description>
<value>#101</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CH3_CFR</name>
<description>Channel3 Configuration Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HW_TRG</name>
<description>Hardware Trigger Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger select</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger select</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_INP_SEL</name>
<description>Decimator Clock Input Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>On the chip modulator clock will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_CLK_EDGE_SEL</name>
<description>Decimator Clock Edge Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Posedge will be used.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Negedge will be used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CC</name>
<description>Continuous Conversion/Single Conversion Mode Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion following a triggering event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions following a triggering event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_EN</name>
<description>Decimation Filter enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Decimation filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Decimation filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SD_MOD_EN</name>
<description>Sigma Delta Modulator enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SD ADC3 is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SD ADC3 is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYP_MODE</name>
<description>AFE Channel bypass mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bypass mode where ADC and PGA of the appropriate channel are disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEC_OSR</name>
<description>Decimator OverSampling Ratio select</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>64</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>128</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>256</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>512</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>1024</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>2048</description>
<value>#101</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40FA00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STRTUP_CNT</name>
<description>Start up count</description>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESULT_FORMAT</name>
<description>Result Format</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Left justified 2&apos;s complement 32-bit : SVVVVVVVVVVVVVVVVVVVVVVV00000000 where (S= sign bit , V=valid result value, 0=zero)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Right justified 2&apos;s complement 32-bit : SSSSSSSSSVVVVVVVVVVVVVVVVVVVVVVV where (S= sign bit , V= valid result value, 0= zero)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLY_OK</name>
<description>Delay OK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RST_B</name>
<description>Software Reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All ADCs, PGAs and Decimation filters are disabled. Clock Configuration bits will be reset.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>.= All ADCs, PGAs and Decimation filters are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPM_EN</name>
<description>Low power Mode enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE will be in normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE will be in low power mode. Setting this bit reduce the current consumption of ADC and Buffer Amplifier , the max modulator clock frequency is below 1Mhz.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOFT_TRG3</name>
<description>Software Trigger3</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SOFT_TRG2</name>
<description>Software Trigger2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SOFT_TRG1</name>
<description>Software Trigger1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SOFT_TRG0</name>
<description>Software Trigger0</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MSTR_EN</name>
<description>AFE Master Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All ADCs are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All ADCs and filters will get simultaneously enabled .</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CKR</name>
<description>Clock Configuration Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLS</name>
<description>Clock Source Select</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mod_clk0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mod_clk1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mod_clk2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>mod_clk3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIV</name>
<description>Clock Divider Select</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>divide by 1</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>divide by 2 (default)</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>divide by 4</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>divide by 8</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>divide by 16</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>divide by 32</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>divide by 64</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>divide by 128</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1xxx</name>
<description>divide by 256</description>
<value>#1xxx</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DI</name>
<description>DMA and Interrupt Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTEN3</name>
<description>Interrupt Enable 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTEN2</name>
<description>Interrupt Enable 2</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTEN1</name>
<description>Interrupt Enable 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTEN0</name>
<description>Interrupt Enable 0</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAEN3</name>
<description>DMA Enable3</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAEN2</name>
<description>DMA Enable2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAEN1</name>
<description>DMA Enable1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAEN0</name>
<description>DMA Enable0</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH0_DR</name>
<description>Channel0 Delay Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH1_DR</name>
<description>Channel1 Delay Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH2_DR</name>
<description>Channel2 Delay Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH3_DR</name>
<description>Channel3 Delay Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH0_RR</name>
<description>Channel0 Result Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SDR</name>
<description>Sample Data Result</description>
<bitOffset>0</bitOffset>
<bitWidth>23</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SIGN_BITS</name>
<description>Sign Bits</description>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CH1_RR</name>
<description>Channel1 Result Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SDR</name>
<description>Sample Data Result</description>
<bitOffset>0</bitOffset>
<bitWidth>23</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SIGN_BITS</name>
<description>Sign Bits</description>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CH2_RR</name>
<description>Channel2 Result Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SDR</name>
<description>Sample Data Result</description>
<bitOffset>0</bitOffset>
<bitWidth>23</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SIGN_BITS</name>
<description>Sign Bits</description>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CH3_RR</name>
<description>Channel3 Result Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SDR</name>
<description>Sample Data Result</description>
<bitOffset>0</bitOffset>
<bitWidth>23</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SIGN_BITS</name>
<description>Sign Bits</description>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDY3</name>
<description>AFE Ready4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE Channel3 is disabled or has not completed its start up period</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE Channel3 is ready to initiate conversions.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDY2</name>
<description>AFE Ready3</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE Channel2 is disabled or has not completed its start up period</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE Channel2 is ready to initiate conversions.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDY1</name>
<description>AFE Ready2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE Channel1 is disabled or has not completed its start up period</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE Channel1 is ready to initiate conversions.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDY0</name>
<description>AFE Ready1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE Channel0 is disabled or has not completed its start up period</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE Channel0 is ready to initiate conversions.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVR3</name>
<description>Overflow Flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR2</name>
<description>Overflow Flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR1</name>
<description>Overflow Flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR0</name>
<description>Overflow Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COC3</name>
<description>Conversion Complete</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COC2</name>
<description>Conversion Complete</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COC1</name>
<description>Conversion Complete</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COC0</name>
<description>Conversion Complete</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cyclic Redundancy Check</description>
<prependToName>CRC_</prependToName>
<baseAddress>0x40034000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<description>CRC Data register</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LL</name>
<description>CRC Low Lower Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LU</name>
<description>CRC Low Upper Byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HL</name>
<description>CRC High Lower Byte</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HU</name>
<description>CRC High Upper Byte</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAL</name>
<description>CRC_DATAL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATAL</name>
<description>DATAL stores the lower 16 bits of the 16/32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATALL</name>
<description>CRC_DATALL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATALL</name>
<description>CRCLL stores the first 8 bits of the 32 bit DATA</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATALU</name>
<description>CRC_DATALU register.</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATALU</name>
<description>DATALL stores the second 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAH</name>
<description>CRC_DATAH register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATAH</name>
<description>DATAH stores the high 16 bits of the 16/32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAHL</name>
<description>CRC_DATAHL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATAHL</name>
<description>DATAHL stores the third 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAHU</name>
<description>CRC_DATAHU register.</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATAHU</name>
<description>DATAHU stores the fourth 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLY</name>
<description>CRC Polynomial register</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1021</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOW</name>
<description>Low Polynominal Half-word</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HIGH</name>
<description>High Polynominal Half-word</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYL</name>
<description>CRC_GPOLYL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>GPOLYL</name>
<description>POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYLL</name>
<description>CRC_GPOLYLL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYLL</name>
<description>POLYLL stores the first 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYLU</name>
<description>CRC_GPOLYLU register.</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYLU</name>
<description>POLYLL stores the second 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYH</name>
<description>CRC_GPOLYH register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>GPOLYH</name>
<description>POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYHL</name>
<description>CRC_GPOLYHL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYHL</name>
<description>POLYHL stores the third 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYHU</name>
<description>CRC_GPOLYHU register.</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYHU</name>
<description>POLYHU stores the fourth 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>CRC Control register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCRC</name>
<description>no description available</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>16-bit CRC protocol.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32-bit CRC protocol.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAS</name>
<description>Write CRC Data Register As Seed</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the CRC data register are data values.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the CRC data register are seed values.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FXOR</name>
<description>Complement Read Of CRC Data Register</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No XOR on reading.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invert or complement the read value of the CRC Data register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOTR</name>
<description>Type Of Transpose For Read</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed; bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOT</name>
<description>Type Of Transpose For Writes</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed; bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRLHU</name>
<description>CRC_CTRLHU register.</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TCRC</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>16-bit CRC protocol.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32-bit CRC protocol.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAS</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to CRC data register are data values.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to CRC data reguster are seed values.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FXOR</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No XOR on reading.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invert or complement the read value of CRC data register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOTR</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No Transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed, bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOT</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No Transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed, bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTMR</name>
<description>Low Power Timer</description>
<prependToName>LPTMR_</prependToName>
<baseAddress>0x4003C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTMR</name>
<value>30</value>
</interrupt>
<registers>
<register>
<name>CSR</name>
<description>Low Power Timer Control Status Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPTMR is disabled and internal logic is reset.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPTMR is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMS</name>
<description>Timer Mode Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time Counter mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFC</name>
<description>Timer Free-Running Counter</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNR is reset whenever TCF is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNR is reset on overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPP</name>
<description>Timer Pin Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPS</name>
<description>Timer Pin Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pulse counter input 0 is selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pulse counter input 1 is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pulse counter input 2 is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Pulse counter input 3 is selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer interrupt disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer interrupt enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The value of CNR is not equal to CMR and increments.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The value of CNR is equal to CMR and increments.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<description>Low Power Timer Prescale Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCS</name>
<description>Prescaler Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Prescaler/glitch filter clock 0 selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Prescaler/glitch filter clock 1 selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Prescaler/glitch filter clock 2 selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Prescaler/glitch filter clock 3 selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PBYP</name>
<description>Prescaler Bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prescaler/glitch filter is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prescaler/glitch filter is bypassed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALE</name>
<description>Prescale Value</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CMR</name>
<description>Low Power Timer Compare Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMPARE</name>
<description>Compare Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNR</name>
<description>Low Power Timer Counter Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SIM</name>
<description>System Integration Module</description>
<prependToName>SIM_</prependToName>
<baseAddress>0x4003E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1070</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SOPT1</name>
<description>System Options Register 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SRAMSIZE</name>
<description>Returns the size of the system RAM</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0101</name>
<description>16kB System RAM</description>
<value>#0101</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSC32KSEL</name>
<description>32K oscillator clock select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>OSC32KCLK</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>ERCLK32K</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>MCGIRCLK</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>LPO</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT1_CFG</name>
<description>SOPT1 Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPTMR1SEL</name>
<description>LP timer Channel1 Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pad PTE4</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pad PTF4</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pad PTG1</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTMR2SEL</name>
<description>LP timer Channel2 Select</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pad PTD6</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pad PTF3</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pad PTG5</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTMR3SEL</name>
<description>LP timer Channel3 Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pad PTD5</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pad PTG0</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pad PTG6</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPOLPTMR0SEL</name>
<description>Comparator output selection for LPTMR channel0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMP[1] output selected as LPTMR input[0]</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP[0] output selected as LPTMR input[0]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAMSBDIS</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source bias of System SRAM enabled during VLPR and VLPW modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source bias of System SRAM disabled during VLPR and VLPW modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAMBPEN</name>
<description>RAM Bitline Precharge Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bitline precharge of system SRAM disabled during VLPR and VLPW modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bitline precharge of system SRAM enabled during VLPR and VLPW modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRL_REG</name>
<description>System Control Register</description>
<addressOffset>0x1004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMIDIS</name>
<description>NMI Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NMI enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NMI disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL_VLP_EN</name>
<description>PLL VLP Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTC2_HD_EN</name>
<description>PTC2 HighDrive Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SAR_TRG_CLK_SEL</name>
<description>SAR ADC Trigger Clk Select</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock (During Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>ADC asynchronous Clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>ERCLK32K</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>OSCCLK</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKOUTSEL</name>
<description>Clock out Select</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Disabled</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Gated Core Clk</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Bus/Flash Clk</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>LPO clock from PMC</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IRC clock from MCG</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Muxed 32Khz source (please refer SOPT1[19:18] for possible options)</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>MHz Oscillator external reference clock</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>PLL clock output from MCG</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDID</name>
<description>System Device Identification Register</description>
<addressOffset>0x1024</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PINID</name>
<description>Pincount identification</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0011</name>
<description>44-pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>64-pin</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>100-pin</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIEID</name>
<description>Die ID</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>First cut</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REVID</name>
<description>Revision ID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>Second Cut</description>
<value>#0001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRAMSIZE</name>
<description>SRAM Size</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0101</name>
<description>16kB SRAM</description>
<value>#0101</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATTR</name>
<description>Attribute ID</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>M0+ core</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SERIESID</name>
<description>Series ID</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0011</name>
<description>Metering Series</description>
<value>#0011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUBFAMID</name>
<description>Sub-Family ID</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0010</name>
<description>Device derivatives with 2 AFE enabled (AFE Channels 0 and 2 are enabled)</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Device derivatives with 3 AFE enabled (AFE Channels 0, 1, and 2 are enabled)</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Device derivatives with 4 AFE enabled</description>
<value>#0100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAMID</name>
<description>Metering family ID</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>Device derivatives without LCD</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Device derivatives with LCD</description>
<value>#0011</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC4</name>
<description>System Clock Gating Control Register 4</description>
<addressOffset>0x1034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x78008070</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EWM</name>
<description>External Watchdog Monitor Clock gate control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCG</name>
<description>MCG clock gate control.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSC</name>
<description>Oscillator (Mhz) Clock Gate Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0</name>
<description>I2C0 Clock Gate Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>I2C1 Clock Gate Control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0</name>
<description>UART0 Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1</name>
<description>UART1 Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART2</name>
<description>UART2 Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART3</name>
<description>UART3 Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREF</name>
<description>VREF Clock Gate Control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0</name>
<description>High Speed Comparator0 Clock Gate Control.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1</name>
<description>High Speed Comparator1 Clock Gate Control.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0</name>
<description>SPI0 Clock Gate Control</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1</name>
<description>SPI1 Clock Gate Control</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC5</name>
<description>System Clock Gating Control Register 5</description>
<addressOffset>0x1038</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SLCD</name>
<description>Segmented LCD Clock Gate Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTA</name>
<description>PCTLA Clock Gate Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTB</name>
<description>PCTLB Clock Gate Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTC</name>
<description>PCTLC Clock Gate Control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTD</name>
<description>PCTLD Clock Gate Control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTE</name>
<description>PCTLE Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTF</name>
<description>PCTLF Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTG</name>
<description>PCTLG Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTH</name>
<description>PCTLH Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTI</name>
<description>PCTLI Clock Gate Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRTC</name>
<description>IRTC Clock Gate Control</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRTCREGFILE</name>
<description>IRTC_REG_FILE Clock Gate Control</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDOG</name>
<description>Watchdog Clock Gate Control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XBAR</name>
<description>Peripheral Crossbar Clock Gate Control</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0</name>
<description>Quadtimer0 Clock Gate Control</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR1</name>
<description>Quadtimer1 Clock Gate Control</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR2</name>
<description>Quadtimer2 Clock Gate Control</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR3</name>
<description>Quadtimer3 Clock Gate Control</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC6</name>
<description>System Clock Gating Control Register 6</description>
<addressOffset>0x103C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTFA</name>
<description>FTFA Clock Gate Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX0</name>
<description>DMA MUX0 Clock Gate Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX1</name>
<description>DMA MUX1 Clock Gate Control</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX2</name>
<description>DMA MUX2 Clock Gate Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX3</name>
<description>DMA MUX3 Clock Gate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGA</name>
<description>RNGA Clock Gate Control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC</name>
<description>SAR ADC Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIT0</name>
<description>PIT0 Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIT1</name>
<description>PIT1 Clock Gate Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AFE</name>
<description>AFE Clock Gate Control</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC</name>
<description>Programmable CRC Clock Gate Control</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTMR</name>
<description>LPTMR Clock Gate Control</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIM_LP</name>
<description>SIM_LP Clock Gate Control</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>1</name>
<description>Clock is enabled</description>
<value>#1</value>
</enumeratedValue>
<enumeratedValue>
<name>0</name>
<description>Clock is disabled</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIM_HP</name>
<description>SIM_HP Clock Gate Control</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>1</name>
<description>Clock is always enabled to SIM</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC7</name>
<description>System Clock Gating Control Register 7</description>
<addressOffset>0x1040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MPU</name>
<description>MPU Clock Gate control.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>DMA Clock Gate control.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV1</name>
<description>System Clock Divider Register 1</description>
<addressOffset>0x1044</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCLKMODE</name>
<description>System Clock Mode</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>1:1:1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2:1:1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSDIV</name>
<description>System Clock divider</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Divide by 1</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Divide by 2</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Divide by 3</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Divide by 4 and so on..... If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence)</description>
<value>#0011</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG1</name>
<description>Flash Configuration Register 1</description>
<addressOffset>0x104C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLASHDIS</name>
<description>Flash Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash is enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHDOZE</name>
<description>Flash Doze</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash remains enabled during Wait mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled for the duration of Wait mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFSIZE</name>
<description>Program flash size</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0101</name>
<description>64 KB of program flash memory, 2 KB protection region</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>128 KB of program flash memory, 4 KB protection region</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>(Default)</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG2</name>
<description>Flash Configuration Register 2</description>
<addressOffset>0x1050</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAXADDR</name>
<description>Max address block</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UID0</name>
<description>Unique Identification Register 0</description>
<addressOffset>0x1054</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UID1</name>
<description>Unique Identification Register 1</description>
<addressOffset>0x1058</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UID2</name>
<description>Unique Identification Register 2</description>
<addressOffset>0x105C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UID3</name>
<description>Unique Identification Register 3</description>
<addressOffset>0x1060</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MISC_CTL</name>
<description>Miscellaneous Control Register</description>
<addressOffset>0x106C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>XBARAFEMODOUTSEL</name>
<description>XBAR AFE Modulator Output Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Sigma Delta Modulator 0 data output</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Sigma Delta Modulator 1 data output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Sigma Delta Modulator 2 data output</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Sigma Delta Modulator 3 data output</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMADONESEL</name>
<description>DMA Done select</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AFECLKSEL</name>
<description>AFE Clock Source Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCG PLL Clock selected</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCG FLL Clock selected</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>OSC Clock selected</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AFECLKPADDIR</name>
<description>AFE Clock Pad Direction</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>AFE CLK PAD is input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>AFE CLK PAD is output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTMODTYPE</name>
<description>UART Modulation Type</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TypeA (ORed) Modulation selected for IRDA</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TypeB (ANDed) Modulation selected for IRDA</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0IRSEL</name>
<description>UART0 IRDA Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad RX input (PTD[0] or PTF[3], as selected in Pinmux control) selected for RX input of UART0 and UART0 TX signal is not used for modulation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART0 selected for IRDA modulation. UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1IRSEL</name>
<description>UART1 IRDA Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad RX input (PTD[2] or PTI[0], as selected in Pinmux control) selected for RX input of UART1 and UART1 TX signal is not used for modulation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART1 selected for IRDA modulation. UART1 TX modulated by XBAR_OUT[14] and UART1 RX input connected to XBAR_OUT[13]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART2IRSEL</name>
<description>UART2 IRDA Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad RX input PTE[6] selected for RX input of UART2 and UART2 TX signal is not used for modulation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART2 selected for IRDA modulation. UART2 TX modulated by XBAR_OUT[14] and UART2 RX input connected to XBAR_OUT[13].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART3IRSEL</name>
<description>UART3 IRDA Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad RX input (PTC[3] or PTD[7], as selected in Pinmux control) selected for RX input of UART3 and UART3 TX signal is not used for modulation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART3 selected for IRDA modulation. UART3 TX modulated by XBAR_OUT[14] and UART3 RX input connected to XBAR_OUT[13].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XBARPITOUTSEL</name>
<description>XBAR PIT Output select</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>PIT0[0] (default)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PIT0[1]</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PIT1[0]</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>PIT1[1]</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EWMINSEL</name>
<description>External Watchdog Monitor Input Select</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Input from PAD (PTE[2] or PTE[4] as selected from Pinmux control )</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral Crossbar (XBAR) Output[32]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0PLLCLKSEL</name>
<description>Timer CH0 PLL clock select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects Bus Clock as source for the Timer CH0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Selects the PLL_AFE clock as the source for Timer CH0. The PLL_AFE clock source is itself selected using the MISC_CTL[5:4]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0SCSSEL</name>
<description>Quadtimer Channel0 Secondary Count Source Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad PTF1 or PTD5, depending upon PCTL configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral Crossbar (XBAR) Output[5]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR1SCSSEL</name>
<description>Quadtimer Channel1 Secondary Count Source Select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad PTG0 or PTC6, depending upon PCTL configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral Crossbar (XBAR) Output[6]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR2SCSSEL</name>
<description>Quadtimer Channel2 Secondary Count Source Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad PTF7 or PTF0, depending upon PCTL configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral Crossbar (XBAR) Output[7]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR3SCSSEL</name>
<description>Quadtimer Channel3 Secondary Count Source Select</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pad PTE5 or PTD1, depending upon PCTL configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral Crossbar (XBAR) Output[8]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0PCSSEL</name>
<description>Quadtimer Channel0 Primary Count Source Select</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Peripheral Crossbar Output [9]</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Peripheral Crossbar Output [10]</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR1PCSSEL</name>
<description>Quadtimer Channel1 Primary Count Source Select</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Peripheral Crossbar Output [9]</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Peripheral Crossbar Output [10]</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR2PCSSEL</name>
<description>Quadtimer Channel2 Primary Count Source Select</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Peripheral Crossbar Output [9]</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Peripheral Crossbar Output [10]</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR3PCSSEL</name>
<description>Quadtimer Channel3 Primary Count Source Select</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Peripheral Crossbar Output [9]</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Peripheral Crossbar Output [10]</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCCLKSEL</name>
<description>RTC Clock select</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RTC OSC_32K clock selected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32K IRC Clock selected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFBUFOUTEN</name>
<description>VrefBuffer Output Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer does not drive PAD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer drives selected voltage (selected by vref_buffer_sel) on pad</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFBUFINSEL</name>
<description>VrefBuffer Input Select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal Reference selected as Buffer Input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External Reference selected as Buffer Input</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFBUFPD</name>
<description>VrefBuffer Power Down</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer Powered Down</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTA</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTA_</prependToName>
<baseAddress>0x40046000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTB</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTB_</prependToName>
<baseAddress>0x40047000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTC</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTC_</prependToName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTD</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTD_</prependToName>
<baseAddress>0x40049000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x703</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTE</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTE_</prependToName>
<baseAddress>0x4004A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xCC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFER</name>
<description>Digital Filter Enable Register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFE</name>
<description>Digital Filter Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFCR</name>
<description>Digital Filter Clock Register</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CS</name>
<description>Clock Source</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Digital filters are clocked by the bus clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Digital filters are clocked by the 1 kHz LPO clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFWR</name>
<description>Digital Filter Width Register</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FILT</name>
<description>Filter Length</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTF</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTF_</prependToName>
<baseAddress>0x4004B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTG</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTG_</prependToName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTH</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTH_</prependToName>
<baseAddress>0x4004D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTI</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTI_</prependToName>
<baseAddress>0x4004E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic zero.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic one.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real Time Clock</description>
<prependToName>RTC_</prependToName>
<baseAddress>0x40050000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x44</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC</name>
<value>25</value>
</interrupt>
<registers>
<register>
<name>YEARMON</name>
<description>RTC Year and Month Counters Register</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>MON_CNT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Illegal Value</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>January</description>
<value>#1</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>October</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>November</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YROFST</name>
<description>Year Offset Count Value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAYS</name>
<description>RTC Days and Day-of-Week Counters Register</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DAY_CNT</name>
<description>Days Counter Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DOW</name>
<description>Day of Week Counter Value.</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sunday</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Monday</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HOURMIN</name>
<description>RTC Hours and Minutes Counters Register</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>MIN_CNT</name>
<description>Minutes Counter Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HOUR_CNT</name>
<description>Hours Counter Value.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SECONDS</name>
<description>RTC Seconds Counters Register</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEC_CNT</name>
<description>Seconds Counter Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM_YEARMON</name>
<description>RTC Year and Months Alarm Register</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ALM_MON</name>
<description>Months Value for Alarm.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALM_YEAR</name>
<description>Year Value for Alarm.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM_DAYS</name>
<description>RTC Days Alarm Register</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ALM_DAY</name>
<description>Days Value for Alarm.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM_HOURMIN</name>
<description>RTC Hours and Minutes Alarm Register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ALM_MIN</name>
<description>Minutes Value for Alarm.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALM_HOUR</name>
<description>Hours Value for Alarm.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM_SECONDS</name>
<description>RTC Seconds Alarm Register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ALM_SEC</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DEC_SEC</name>
<description>Decrement Seconds Counter by 1.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>INC_SEC</name>
<description>Increment Seconds Counter by 1.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>RTC Control Register</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FINEEN</name>
<description>Fine compensation enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>1</name>
<description>Fine compensation is enabled.</description>
<value>#1</value>
</enumeratedValue>
<enumeratedValue>
<name>0</name>
<description>Fine compensation is disabled</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP_EN</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALM_MATCH</name>
<description>Alarm Match bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Only Seconds, Minutes, and Hours matched.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only Seconds, Minutes, Hours, and Days matched.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only Seconds, Minutes, Hours, Days, and Months matched.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER_STB_MASK</name>
<description>Sampling timer clocks mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>1</name>
<description>Sampling clocks are gated in standby mode</description>
<value>#1</value>
</enumeratedValue>
<enumeratedValue>
<name>0</name>
<description>Sampling clocks are not gated when in standby mode</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DST_EN</name>
<description>Daylight Saving Enable.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled. Daylight saving changes are not applied. Daylight saving registers can be modified.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled. Daylight saving changes are applied.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWR</name>
<description>Software Reset bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software Reset cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software Reset asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKOUT</name>
<description>RTC Clock Output Selection.</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No Output Clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fine 1 Hz Clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>32.768 kHz Clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Coarse 1 Hz Clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>RTC Status Register</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x8</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INVAL_BIT</name>
<description>Invalidate CPU read/write access bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time /Date Counters can be read/written. Time /Date is valid.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WRITE_PROT_EN</name>
<description>Write Protect Enable status bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Registers are unlocked and can be accessed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Registers are locked and in read-only mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPU_LOW_VOLT</name>
<description>CPU Low Voltage Warning status bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CPU in Normal Operating Voltage.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RST_SRC</name>
<description>Reset Source bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Part was reset due to Standby Mode Exit (that is when VDD is powered up and VBAT was not powered down at all).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Part was reset due to Power-On Reset (that is Power On Reset when both VBAT and VDD are powered up).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP_INT</name>
<description>Compensation Interval bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WE</name>
<description>Write Enable bits.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Enable Write Protection - Registers are locked.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUS_ERR</name>
<description>Bus Error bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read and Write accesses are normal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read or Write accesses occurred when INVAL_BIT was asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP_DONE</name>
<description>Compensation Done bit.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compensation busy or not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compensation completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>RTC Interrupt Status Register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TAMPER_IS</name>
<description>Tamper Interrupt Status bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted (Default on reset) .</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM_IS</name>
<description>Alarm Interrupt Status bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAY_IS</name>
<description>Days Interrupt Status bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOUR_IS</name>
<description>Hours Interrupt Status bit.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MIN_IS</name>
<description>Minutes Interrupt Status bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_1HZ</name>
<description>1 Hz Interval Interrupt Status bit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_2HZ</name>
<description>2 Hz Interval Interrupt Status bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_4HZ</name>
<description>4 Hz Interval Interrupt Status bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_8HZ</name>
<description>8 Hz Interval Interrupt Status bit.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_16HZ</name>
<description>16 Hz Interval Interrupt Status bit.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_32HZ</name>
<description>32 Hz Interval Interrupt Status bit.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_64HZ</name>
<description>64 Hz Interval Interrupt Status bit.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_128HZ</name>
<description>128 Hz Interval Interrupt Status bit.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_256HZ</name>
<description>256 Hz Interval Interrupt Status bit.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IS_512HZ</name>
<description>512 Hz Interval Interrupt Status bit.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is de-asserted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>RTC Interrupt Enable Register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TAMPER_IE</name>
<description>Tamper Interrupt Enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled (Default on reset).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM_IE</name>
<description>Alarm Interrupt Enable bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAY_IE</name>
<description>Days Interrupt Enable bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOUR_IE</name>
<description>Hours Interrupt Enable bit.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MIN_IE</name>
<description>Minutes Interrupt Enable bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_1HZ</name>
<description>1 Hz Interval Interrupt Enable bit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_2HZ</name>
<description>2 Hz Interval Interrupt Enable bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_4HZ</name>
<description>4 Hz Interval Interrupt Enable bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_8HZ</name>
<description>8 Hz Interval Interrupt Enable bit.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_16HZ</name>
<description>16 Hz Interval Interrupt Enable bit.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_32HZ</name>
<description>32 Hz Interval Interrupt Enable bit.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_64HZ</name>
<description>64 Hz Interval Interrupt Enable bit.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_128HZ</name>
<description>128 Hz Interval Interrupt Enable bit.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_256HZ</name>
<description>256 Hz Interval Interrupt Enable bit.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IE_512HZ</name>
<description>512 Hz Interval Interrupt Enable bit.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GP_DATA_REG</name>
<description>RTC General Purpose Data Register</description>
<addressOffset>0x20</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>GP_DATA_REG</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DST_HOUR</name>
<description>RTC Daylight Saving Hour Register</description>
<addressOffset>0x22</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DST_END_HOUR</name>
<description>Daylight Saving Time (DST) Hours End Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DST_START_HOUR</name>
<description>Daylight Saving Time (DST) Hours Start Value.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DST_MONTH</name>
<description>RTC Daylight Saving Month Register</description>
<addressOffset>0x24</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DST_END_MONTH</name>
<description>Daylight Saving Time (DST) Month End Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DST_START_MONTH</name>
<description>Daylight Saving Time (DST) Month Start Value.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DST_DAY</name>
<description>RTC Daylight Saving Day Register</description>
<addressOffset>0x26</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DST_END_DAY</name>
<description>Daylight Saving Time (DST) Day End Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DST_START_DAY</name>
<description>Daylight Saving Time (DST) Day Start Value.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMPEN</name>
<description>RTC Compensation Register</description>
<addressOffset>0x28</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPEN_VAL</name>
<description>Compensation Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TAMPER_DIRECTION</name>
<description>Tamper Direction Register</description>
<addressOffset>0x2C</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>A_P_TAMP</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I_O_TAMP</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TAMPER_QSCR</name>
<description>Tamper Queue Status and Control Register</description>
<addressOffset>0x2E</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>Q_FULL</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Q_FULL_INT_EN</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Q_CLEAR</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LFSR_CLK_SEL</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LFSR_DURATION</name>
<description>no description available</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TAMPER_SCR</name>
<description>RTC Tamper Status and Control Register</description>
<addressOffset>0x32</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x80F</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TMPR_EN</name>
<description>Tamper Control</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TMPR_STS</name>
<description>Tamper Status Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FILTER01_CFG</name>
<description>RTC Tamper 0 1 Filter Configuration Register</description>
<addressOffset>0x34</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FIL_DUR1</name>
<description>Tamper Detect Bit 1 Filter Duration</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Filtering operation disabled.</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK_SEL1</name>
<description>Tamper Filter 1 Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>32 kHz clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>512 Hz clock</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>128 Hz clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>64 Hz clock</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>16 Hz clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>8 Hz clock</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>4 Hz clock</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>2 Hz clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL1</name>
<description>Tamper Detect Input Bit 1 Polarity Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Tamper detect input bit 1 is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tamper detect input bit 1 is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIL_DUR0</name>
<description>Tamper Detect Bit 0 Filter Duration</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Filtering operation disabled.</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK_SEL0</name>
<description>Tamper Filter 0 Clock Select</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>32 kHz clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>512 Hz clock</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>128 Hz clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>64 Hz clock</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>16 Hz clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>8 Hz clock</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>4 Hz clock</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>2 Hz clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL0</name>
<description>Tamper Detect Input Bit 0 Polarity Control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Tamper detect input bit 0 is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tamper detect input bit 0 is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILTER2_CFG</name>
<description>RTC Tamper 2 Filter Configuration Register</description>
<addressOffset>0x36</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FIL_DUR2</name>
<description>Tamper Detect Bit 2 Filter Duration</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Filtering operation disabled.</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK_SEL2</name>
<description>Tamper Filter 2 Clock Select</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>32 kHz clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>512 Hz clock</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>128 Hz clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>64 Hz clock</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>16 Hz clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>8 Hz clock</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>4 Hz clock</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>2 Hz clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL2</name>
<description>Tamper Detect Input Bit 2 Polarity Control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Tamper detect input bit 2 is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tamper detect input bit 2 is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TAMPER_QUEUE</name>
<description>Tamper Queue Register</description>
<addressOffset>0x40</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TAMPER_DATA</name>
<description>Tamper type stamp and pin number information register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<description>RTC Control 2 Register</description>
<addressOffset>0x42</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TAMP_CFG_OVER</name>
<description>Tamper Configuration Over</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Tamper filter processing disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tamper filter processing enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKEUP_STATUS</name>
<description>Wakeup Status</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The wakeup/hibernation pin is in HiZ mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The wakeup/hibernation pin is at logic 0. MCU is in sleep mode.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The wakeup/ hibernation pin is at logic 1. MCU is in sleep mode.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKEUP_MODE</name>
<description>Wakeup Mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Tamper pin 0 is used as the tamper pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tamper pin 0 is used as a wakeup/hibernation pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDOG</name>
<description>Generation 2008 Watchdog Timer</description>
<prependToName>WDOG_</prependToName>
<baseAddress>0x40053000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>Watchdog</name>
<value>29</value>
</interrupt>
<registers>
<register>
<name>STCTRLH</name>
<description>Watchdog Status and Control Register High</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1D1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGEN</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSRC</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG clock sourced from LPO .</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG clock sourced from alternate clock source.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQRSTEN</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG time-out generates reset only.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG time-out initially generates an interrupt. After WCT, it generates a reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WINEN</name>
<description>no description available</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALLOWUPDATE</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No further updates allowed to WDOG write-once registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG write-once registers can be unlocked for updating.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGEN</name>
<description>no description available</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled in CPU Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled in CPU Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPEN</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled in CPU Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled in CPU Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TESTWDOG</name>
<description>no description available</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TESTSEL</name>
<description>no description available</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYTESEL</name>
<description>no description available</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Byte 0 selected</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Byte 1 selected</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Byte 2 selected</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Byte 3 selected</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DISTESTWDOG</name>
<description>no description available</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG functional test mode is not disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG functional test mode is disabled permanently until reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STCTRLL</name>
<description>Watchdog Status and Control Register Low</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INTFLG</name>
<description>no description available</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOVALH</name>
<description>Watchdog Time-out Value Register High</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x4C</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TOVALHIGH</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOVALL</name>
<description>Watchdog Time-out Value Register Low</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x4B40</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TOVALLOW</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINH</name>
<description>Watchdog Window Register High</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WINHIGH</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINL</name>
<description>Watchdog Window Register Low</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WINLOW</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>REFRESH</name>
<description>Watchdog Refresh register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xB480</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGREFRESH</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UNLOCK</name>
<description>Watchdog Unlock register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xD928</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGUNLOCK</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TMROUTH</name>
<description>Watchdog Timer Output Register High</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIMEROUTHIGH</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TMROUTL</name>
<description>Watchdog Timer Output Register Low</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIMEROUTLOW</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSTCNT</name>
<description>Watchdog Reset Count register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSTCNT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<description>Watchdog Prescaler register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x400</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PRESCVAL</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>XBAR</name>
<description>Crossbar Switch</description>
<prependToName>XBAR_</prependToName>
<baseAddress>0x40055000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>XBAR</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>SEL0</name>
<description>Crossbar Select Register 0</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL0</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL1</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL1</name>
<description>Crossbar Select Register 1</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL2</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL3</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL2</name>
<description>Crossbar Select Register 2</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL4</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL5</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL3</name>
<description>Crossbar Select Register 3</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL6</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL7</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL4</name>
<description>Crossbar Select Register 4</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL8</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL9</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL5</name>
<description>Crossbar Select Register 5</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL10</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL11</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL6</name>
<description>Crossbar Select Register 6</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL12</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL13</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL7</name>
<description>Crossbar Select Register 7</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL14</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL15</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL8</name>
<description>Crossbar Select Register 8</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL16</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL17</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL9</name>
<description>Crossbar Select Register 9</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL18</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL19</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL10</name>
<description>Crossbar Select Register 10</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL20</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL21</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL11</name>
<description>Crossbar Select Register 11</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL22</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL23</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL12</name>
<description>Crossbar Select Register 12</description>
<addressOffset>0x18</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL24</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL25</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL13</name>
<description>Crossbar Select Register 13</description>
<addressOffset>0x1A</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL26</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL27</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL14</name>
<description>Crossbar Select Register 14</description>
<addressOffset>0x1C</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL28</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL29</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL15</name>
<description>Crossbar Select Register 15</description>
<addressOffset>0x1E</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL30</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEL31</name>
<description>no description available</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEL16</name>
<description>Crossbar Select Register 16</description>
<addressOffset>0x20</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SEL32</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL0</name>
<description>Crossbar Control Register 0</description>
<addressOffset>0x22</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEN0</name>
<description>DMA Enable for XBAR_OUT0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEN0</name>
<description>Interrupt Enable for XBAR_OUT0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGE0</name>
<description>Active edge for edge detection on XBAR_OUT0</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>STS0 never asserts</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>STS0 asserts on rising edges of XBAR_OUT0</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>STS0 asserts on falling edges of XBAR_OUT0</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>STS0 asserts on rising and falling edges of XBAR_OUT0</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STS0</name>
<description>Edge detection status for XBAR_OUT0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Active edge not yet detected on XBAR_OUT0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Active edge detected on XBAR_OUT0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR0</name>
<description>Quad Timer</description>
<groupName>TMR</groupName>
<prependToName>TMR0_</prependToName>
<baseAddress>0x40057000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR0</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>COMP1</name>
<description>Timer Channel Compare Register 1</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_1</name>
<description>Comparison Value 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP2</name>
<description>Timer Channel Compare Register 2</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_2</name>
<description>Comparison Value 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAPT</name>
<description>Timer Channel Capture Register</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CAPTURE</name>
<description>Capture Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<description>Timer Channel Load Register</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>LOAD</name>
<description>Timer Load Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOLD</name>
<description>Timer Channel Hold Register</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>HOLD</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<description>Timer Channel Counter Register</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Timer Channel Control Register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OUTMODE</name>
<description>Output Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Asserted while counter is active</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Clear OFLAG output on successful compare</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Set OFLAG output on successful compare</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Toggle OFLAG output on successful compare</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Toggle OFLAG output using alternating compare registers</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Set on compare, cleared on secondary source input edge</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Set on compare, cleared on counter rollover</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Enable gated clock output while counter is active</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COINIT</name>
<description>Co-Channel Initialization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Co-channel counter/timers cannot force a re-initialization of this counter/timer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Co-channel counter/timers may force a re-initialization of this counter/timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Count Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count down.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LENGTH</name>
<description>Count Length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Roll over.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONCE</name>
<description>Count Once</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count repeatedly.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCS</name>
<description>Secondary Count Source</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Counter 0 input pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Counter 1 input pin</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Counter 2 input pin</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Counter 3 input pin</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCS</name>
<description>Primary Count Source</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Counter 0 input pin</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Counter 1 input pin</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Counter 2 input pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Counter 3 input pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Counter 0 output</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Counter 1 output</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Counter 2 output</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Counter 3 output</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>IP bus clock divide by 1 prescaler</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>IP bus clock divide by 2 prescaler</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>IP bus clock divide by 4 prescaler</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>IP bus clock divide by 8 prescaler</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>IP bus clock divide by 16 prescaler</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>IP bus clock divide by 32 prescaler</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>IP bus clock divide by 64 prescaler</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>IP bus clock divide by 128 prescaler</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM</name>
<description>Count Mode</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>No operation</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Count rising edges of primary source while secondary input high active</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Quadrature count mode, uses primary and secondary sources</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Edge of secondary source triggers primary count until compare</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCTRL</name>
<description>Timer Channel Status and Control Register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OEN</name>
<description>Output Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The external pin is configured as an input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPS</name>
<description>Output Polarity Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>True polarity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCE</name>
<description>Force OFLAG Output</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>VAL</name>
<description>Forced OFLAG Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EEOF</name>
<description>Enable External OFLAG Force</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSTR</name>
<description>Master Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPTURE_MODE</name>
<description>Input Capture Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Capture function is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Load capture register on both edges of input</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INPUT</name>
<description>External Input Signal</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IPS</name>
<description>Input Polarity Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEFIE</name>
<description>Input Edge Flag Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEF</name>
<description>Input Edge Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOFIE</name>
<description>Timer Overflow Flag Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCFIE</name>
<description>Timer Compare Flag Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD1</name>
<description>Timer Channel Comparator Load Register 1</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_1</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD2</name>
<description>Timer Channel Comparator Load Register 2</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_2</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSCTRL</name>
<description>Timer Channel Comparator Status and Control Register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CL1</name>
<description>Compare Load Control 1</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CL2</name>
<description>Compare Load Control 2</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF1</name>
<description>Timer Compare 1 Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2</name>
<description>Timer Compare 2 Interrupt Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF1EN</name>
<description>Timer Compare 1 Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2EN</name>
<description>Timer Compare 2 Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFLAG</name>
<description>Output flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The OFLAG signal is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG signal is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UP</name>
<description>Counting Direction Indicator</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The last count was in the DOWN direction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last count was in the UP direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCI</name>
<description>Triggered Count Initialization Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROC</name>
<description>Reload on Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not reload the counter on a capture event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter on a capture event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALT_LOAD</name>
<description>Alternative Load Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter can be re-initialized only with the LOAD register.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT</name>
<description>Fault Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_EN</name>
<description>Debug Actions Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Continue with normal operation during debug mode. (default)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halt TMR counter during debug mode.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both halt counter and force output to 0 during debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT</name>
<description>Timer Channel Input Filter Register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Input Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FILT_CNT</name>
<description>Input Filter Sample Count</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENBL</name>
<description>Timer Channel Enable Register</description>
<addressOffset>0x1E</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ENBL</name>
<description>Timer Channel Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer channel is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer channel is enabled. (default)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR1</name>
<description>Quad Timer</description>
<groupName>TMR</groupName>
<prependToName>TMR1_</prependToName>
<baseAddress>0x40058000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR1</name>
<value>8</value>
</interrupt>
<registers>
<register>
<name>COMP1</name>
<description>Timer Channel Compare Register 1</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_1</name>
<description>Comparison Value 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP2</name>
<description>Timer Channel Compare Register 2</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_2</name>
<description>Comparison Value 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAPT</name>
<description>Timer Channel Capture Register</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CAPTURE</name>
<description>Capture Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<description>Timer Channel Load Register</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>LOAD</name>
<description>Timer Load Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOLD</name>
<description>Timer Channel Hold Register</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>HOLD</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<description>Timer Channel Counter Register</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Timer Channel Control Register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OUTMODE</name>
<description>Output Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Asserted while counter is active</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Clear OFLAG output on successful compare</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Set OFLAG output on successful compare</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Toggle OFLAG output on successful compare</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Toggle OFLAG output using alternating compare registers</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Set on compare, cleared on secondary source input edge</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Set on compare, cleared on counter rollover</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Enable gated clock output while counter is active</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COINIT</name>
<description>Co-Channel Initialization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Co-channel counter/timers cannot force a re-initialization of this counter/timer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Co-channel counter/timers may force a re-initialization of this counter/timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Count Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count down.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LENGTH</name>
<description>Count Length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Roll over.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONCE</name>
<description>Count Once</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count repeatedly.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCS</name>
<description>Secondary Count Source</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Counter 0 input pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Counter 1 input pin</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Counter 2 input pin</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Counter 3 input pin</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCS</name>
<description>Primary Count Source</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Counter 0 input pin</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Counter 1 input pin</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Counter 2 input pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Counter 3 input pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Counter 0 output</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Counter 1 output</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Counter 2 output</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Counter 3 output</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>IP bus clock divide by 1 prescaler</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>IP bus clock divide by 2 prescaler</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>IP bus clock divide by 4 prescaler</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>IP bus clock divide by 8 prescaler</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>IP bus clock divide by 16 prescaler</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>IP bus clock divide by 32 prescaler</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>IP bus clock divide by 64 prescaler</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>IP bus clock divide by 128 prescaler</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM</name>
<description>Count Mode</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>No operation</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Count rising edges of primary source while secondary input high active</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Quadrature count mode, uses primary and secondary sources</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Edge of secondary source triggers primary count until compare</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCTRL</name>
<description>Timer Channel Status and Control Register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OEN</name>
<description>Output Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The external pin is configured as an input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPS</name>
<description>Output Polarity Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>True polarity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCE</name>
<description>Force OFLAG Output</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>VAL</name>
<description>Forced OFLAG Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EEOF</name>
<description>Enable External OFLAG Force</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSTR</name>
<description>Master Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPTURE_MODE</name>
<description>Input Capture Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Capture function is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Load capture register on both edges of input</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INPUT</name>
<description>External Input Signal</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IPS</name>
<description>Input Polarity Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEFIE</name>
<description>Input Edge Flag Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEF</name>
<description>Input Edge Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOFIE</name>
<description>Timer Overflow Flag Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCFIE</name>
<description>Timer Compare Flag Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD1</name>
<description>Timer Channel Comparator Load Register 1</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_1</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD2</name>
<description>Timer Channel Comparator Load Register 2</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_2</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSCTRL</name>
<description>Timer Channel Comparator Status and Control Register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CL1</name>
<description>Compare Load Control 1</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CL2</name>
<description>Compare Load Control 2</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF1</name>
<description>Timer Compare 1 Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2</name>
<description>Timer Compare 2 Interrupt Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF1EN</name>
<description>Timer Compare 1 Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2EN</name>
<description>Timer Compare 2 Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFLAG</name>
<description>Output flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The OFLAG signal is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG signal is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UP</name>
<description>Counting Direction Indicator</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The last count was in the DOWN direction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last count was in the UP direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCI</name>
<description>Triggered Count Initialization Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROC</name>
<description>Reload on Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not reload the counter on a capture event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter on a capture event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALT_LOAD</name>
<description>Alternative Load Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter can be re-initialized only with the LOAD register.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT</name>
<description>Fault Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_EN</name>
<description>Debug Actions Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Continue with normal operation during debug mode. (default)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halt TMR counter during debug mode.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both halt counter and force output to 0 during debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT</name>
<description>Timer Channel Input Filter Register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Input Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FILT_CNT</name>
<description>Input Filter Sample Count</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR2</name>
<description>Quad Timer</description>
<groupName>TMR</groupName>
<prependToName>TMR2_</prependToName>
<baseAddress>0x40059000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR2</name>
<value>9</value>
</interrupt>
<registers>
<register>
<name>COMP1</name>
<description>Timer Channel Compare Register 1</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_1</name>
<description>Comparison Value 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP2</name>
<description>Timer Channel Compare Register 2</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_2</name>
<description>Comparison Value 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAPT</name>
<description>Timer Channel Capture Register</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CAPTURE</name>
<description>Capture Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<description>Timer Channel Load Register</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>LOAD</name>
<description>Timer Load Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOLD</name>
<description>Timer Channel Hold Register</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>HOLD</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<description>Timer Channel Counter Register</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Timer Channel Control Register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OUTMODE</name>
<description>Output Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Asserted while counter is active</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Clear OFLAG output on successful compare</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Set OFLAG output on successful compare</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Toggle OFLAG output on successful compare</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Toggle OFLAG output using alternating compare registers</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Set on compare, cleared on secondary source input edge</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Set on compare, cleared on counter rollover</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Enable gated clock output while counter is active</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COINIT</name>
<description>Co-Channel Initialization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Co-channel counter/timers cannot force a re-initialization of this counter/timer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Co-channel counter/timers may force a re-initialization of this counter/timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Count Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count down.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LENGTH</name>
<description>Count Length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Roll over.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONCE</name>
<description>Count Once</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count repeatedly.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCS</name>
<description>Secondary Count Source</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Counter 0 input pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Counter 1 input pin</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Counter 2 input pin</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Counter 3 input pin</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCS</name>
<description>Primary Count Source</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Counter 0 input pin</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Counter 1 input pin</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Counter 2 input pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Counter 3 input pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Counter 0 output</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Counter 1 output</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Counter 2 output</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Counter 3 output</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>IP bus clock divide by 1 prescaler</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>IP bus clock divide by 2 prescaler</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>IP bus clock divide by 4 prescaler</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>IP bus clock divide by 8 prescaler</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>IP bus clock divide by 16 prescaler</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>IP bus clock divide by 32 prescaler</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>IP bus clock divide by 64 prescaler</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>IP bus clock divide by 128 prescaler</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM</name>
<description>Count Mode</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>No operation</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Count rising edges of primary source while secondary input high active</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Quadrature count mode, uses primary and secondary sources</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Edge of secondary source triggers primary count until compare</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCTRL</name>
<description>Timer Channel Status and Control Register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OEN</name>
<description>Output Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The external pin is configured as an input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPS</name>
<description>Output Polarity Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>True polarity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCE</name>
<description>Force OFLAG Output</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>VAL</name>
<description>Forced OFLAG Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EEOF</name>
<description>Enable External OFLAG Force</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSTR</name>
<description>Master Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPTURE_MODE</name>
<description>Input Capture Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Capture function is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Load capture register on both edges of input</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INPUT</name>
<description>External Input Signal</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IPS</name>
<description>Input Polarity Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEFIE</name>
<description>Input Edge Flag Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEF</name>
<description>Input Edge Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOFIE</name>
<description>Timer Overflow Flag Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCFIE</name>
<description>Timer Compare Flag Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD1</name>
<description>Timer Channel Comparator Load Register 1</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_1</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD2</name>
<description>Timer Channel Comparator Load Register 2</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_2</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSCTRL</name>
<description>Timer Channel Comparator Status and Control Register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CL1</name>
<description>Compare Load Control 1</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CL2</name>
<description>Compare Load Control 2</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF1</name>
<description>Timer Compare 1 Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2</name>
<description>Timer Compare 2 Interrupt Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF1EN</name>
<description>Timer Compare 1 Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2EN</name>
<description>Timer Compare 2 Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFLAG</name>
<description>Output flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The OFLAG signal is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG signal is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UP</name>
<description>Counting Direction Indicator</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The last count was in the DOWN direction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last count was in the UP direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCI</name>
<description>Triggered Count Initialization Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROC</name>
<description>Reload on Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not reload the counter on a capture event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter on a capture event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALT_LOAD</name>
<description>Alternative Load Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter can be re-initialized only with the LOAD register.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT</name>
<description>Fault Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_EN</name>
<description>Debug Actions Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Continue with normal operation during debug mode. (default)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halt TMR counter during debug mode.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both halt counter and force output to 0 during debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT</name>
<description>Timer Channel Input Filter Register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Input Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FILT_CNT</name>
<description>Input Filter Sample Count</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR3</name>
<description>Quad Timer</description>
<groupName>TMR</groupName>
<prependToName>TMR3_</prependToName>
<baseAddress>0x4005A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TMR3</name>
<value>10</value>
</interrupt>
<registers>
<register>
<name>COMP1</name>
<description>Timer Channel Compare Register 1</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_1</name>
<description>Comparison Value 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP2</name>
<description>Timer Channel Compare Register 2</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARISON_2</name>
<description>Comparison Value 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAPT</name>
<description>Timer Channel Capture Register</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CAPTURE</name>
<description>Capture Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<description>Timer Channel Load Register</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>LOAD</name>
<description>Timer Load Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOLD</name>
<description>Timer Channel Hold Register</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>HOLD</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<description>Timer Channel Counter Register</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Timer Channel Control Register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OUTMODE</name>
<description>Output Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Asserted while counter is active</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Clear OFLAG output on successful compare</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Set OFLAG output on successful compare</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Toggle OFLAG output on successful compare</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Toggle OFLAG output using alternating compare registers</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Set on compare, cleared on secondary source input edge</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Set on compare, cleared on counter rollover</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Enable gated clock output while counter is active</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COINIT</name>
<description>Co-Channel Initialization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Co-channel counter/timers cannot force a re-initialization of this counter/timer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Co-channel counter/timers may force a re-initialization of this counter/timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Count Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count down.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LENGTH</name>
<description>Count Length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Roll over.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONCE</name>
<description>Count Once</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Count repeatedly.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCS</name>
<description>Secondary Count Source</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Counter 0 input pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Counter 1 input pin</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Counter 2 input pin</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Counter 3 input pin</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCS</name>
<description>Primary Count Source</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Counter 0 input pin</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Counter 1 input pin</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Counter 2 input pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Counter 3 input pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Counter 0 output</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Counter 1 output</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Counter 2 output</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Counter 3 output</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>IP bus clock divide by 1 prescaler</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>IP bus clock divide by 2 prescaler</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>IP bus clock divide by 4 prescaler</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>IP bus clock divide by 8 prescaler</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>IP bus clock divide by 16 prescaler</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>IP bus clock divide by 32 prescaler</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>IP bus clock divide by 64 prescaler</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>IP bus clock divide by 128 prescaler</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CM</name>
<description>Count Mode</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>No operation</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Count rising edges of primary source while secondary input high active</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Quadrature count mode, uses primary and secondary sources</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Edge of secondary source triggers primary count until compare</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCTRL</name>
<description>Timer Channel Status and Control Register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OEN</name>
<description>Output Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The external pin is configured as an input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPS</name>
<description>Output Polarity Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>True polarity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCE</name>
<description>Force OFLAG Output</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>VAL</name>
<description>Forced OFLAG Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EEOF</name>
<description>Enable External OFLAG Force</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSTR</name>
<description>Master Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPTURE_MODE</name>
<description>Input Capture Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Capture function is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Load capture register on both edges of input</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INPUT</name>
<description>External Input Signal</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IPS</name>
<description>Input Polarity Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEFIE</name>
<description>Input Edge Flag Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEF</name>
<description>Input Edge Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOFIE</name>
<description>Timer Overflow Flag Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCFIE</name>
<description>Timer Compare Flag Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD1</name>
<description>Timer Channel Comparator Load Register 1</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_1</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPLD2</name>
<description>Timer Channel Comparator Load Register 2</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COMPARATOR_LOAD_2</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSCTRL</name>
<description>Timer Channel Comparator Status and Control Register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CL1</name>
<description>Compare Load Control 1</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CL2</name>
<description>Compare Load Control 2</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Never preload</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Load upon successful compare with the value in COMP1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Load upon successful compare with the value in COMP2</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF1</name>
<description>Timer Compare 1 Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2</name>
<description>Timer Compare 2 Interrupt Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF1EN</name>
<description>Timer Compare 1 Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCF2EN</name>
<description>Timer Compare 2 Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFLAG</name>
<description>Output flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The OFLAG signal is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The OFLAG signal is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UP</name>
<description>Counting Direction Indicator</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The last count was in the DOWN direction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last count was in the UP direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCI</name>
<description>Triggered Count Initialization Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter upon receiving a second trigger event while still counting from the first trigger event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROC</name>
<description>Reload on Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not reload the counter on a capture event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reload the counter on a capture event.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALT_LOAD</name>
<description>Alternative Load Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter can be re-initialized only with the LOAD register.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT</name>
<description>Fault Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_EN</name>
<description>Debug Actions Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Continue with normal operation during debug mode. (default)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halt TMR counter during debug mode.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both halt counter and force output to 0 during debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT</name>
<description>Timer Channel Input Filter Register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Input Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FILT_CNT</name>
<description>Input Filter Sample Count</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EWM</name>
<description>External Watchdog Monitor</description>
<prependToName>EWM_</prependToName>
<baseAddress>0x40061000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EWM</name>
<value>27</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Control Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EWMEN</name>
<description>EWM enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ASSIN</name>
<description>EWM_in&apos;s Assertion State Select.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEN</name>
<description>Input Enable.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTEN</name>
<description>Interrupt Enable.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SERV</name>
<description>Service Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SERVICE</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CMPL</name>
<description>Compare Low Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COMPAREL</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPH</name>
<description>Compare High Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COMPAREH</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCG</name>
<description>Multipurpose Clock Generator module</description>
<prependToName>MCG_</prependToName>
<baseAddress>0x40064000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MCG</name>
<value>28</value>
</interrupt>
<registers>
<register>
<name>C1</name>
<description>MCG Control 1 Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x44</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IREFSTEN</name>
<description>Internal Reference Stop Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRCLKEN</name>
<description>Internal Reference Clock Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGIRCLK inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGIRCLK active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFS</name>
<description>Internal Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slow internal reference clock is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRDIV</name>
<description>FLL External Reference Divider</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - Reserved.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>MCG Control 2 Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x83</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCS</name>
<description>Internal Reference Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slow internal reference clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fast internal reference clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LP</name>
<description>Low Power Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL or PLL is not disabled in bypass modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FLL or PLL is disabled in bypass modes (lower power)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFS0</name>
<description>External Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock requested.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Oscillator requested.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HGO0</name>
<description>High Gain Oscillator Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configure crystal oscillator for low-power operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configure crystal oscillator for high-gain operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RANGE0</name>
<description>Frequency Range Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low frequency range selected for the crystal oscillator .</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - High frequency range selected for the crystal oscillator .</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCRE0</name>
<description>Loss of Clock Reset Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a loss of OSC0 external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a loss of OSC0 external reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>MCG Control 3 Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SCTRIM</name>
<description>Slow Internal Reference Clock Trim Setting</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>MCG Control 4 Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xE0</resetMask>
<fields>
<field>
<name>SCFTRIM</name>
<description>Slow Internal Reference Clock Fine Trim</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCTRIM</name>
<description>Fast Internal Reference Clock Trim Setting</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DRST_DRS</name>
<description>DCO Range Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low range (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Mid range.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - Mid-high range.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - High range.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMX32</name>
<description>DCO Maximum Frequency with 32.768 kHz Reference</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DCO has a default range of 25%.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DCO is fine-tuned for maximum frequency with 32.768 kHz reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>MCG Control 5 Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PLLSTEN0</name>
<description>PLL Stop Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGPLLCLK is disabled in any of the Stop modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGPLLCLK is enabled if system is in Normal Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLCLKEN0</name>
<description>PLL Clock Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGPLLCLK is inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGPLLCLK is active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C6</name>
<description>MCG Control 6 Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x8</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CHGPMP_BIAS</name>
<description>Directly controls the PLL Charge Pump Current. Appropiate selection of this value is imperative to ensure stable operation of the PLL closed loop system. The default value for this field is set to 5&apos;b01000 out of reset which generates a nominal 750nA charge pump current (lcp).</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CME0</name>
<description>Clock Monitor Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External clock monitor is disabled for OSC0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock monitor is enabled for OSC0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLS</name>
<description>PLL Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is selected (PLL reference clock must be in the range of 31.25-39.0625 KHz prior to setting the PLLS bit).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOLIE0</name>
<description>Loss of Lock Interrrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt request is generated on loss of lock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate an interrupt request on loss of lock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>MCG Status Register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x15</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCST</name>
<description>Internal Reference Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of internal reference clock is the slow clock (32 kHz IRC).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of internal reference clock is the fast clock (4 MHz IRC).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCINIT0</name>
<description>OSC Initialization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CLKST</name>
<description>Clock Mode Status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of the FLL is selected (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - Output of the PLL is selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFST</name>
<description>Internal Reference Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of FLL reference clock is the external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of FLL reference clock is the internal reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLST</name>
<description>PLL Select Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of PLLS clock is FLL clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of PLLS clock is PLL output clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK0</name>
<description>Lock Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL is currently unlocked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is currently locked.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOLS0</name>
<description>Loss of Lock Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL has not lost lock since LOLS 0 was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL has lost lock since LOLS 0 was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC</name>
<description>MCG Status and Control Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCS0</name>
<description>OSC0 Loss of Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loss of OSC0 has not occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of OSC0 has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCRDIV</name>
<description>Fast Clock Internal Reference Divider</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide Factor is 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide Factor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide Factor is 4.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide Factor is 8.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide Factor is 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide Factor is 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide Factor is 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide Factor is 128.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLTPRSRV</name>
<description>FLL Filter Preserve Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL filter and FLL frequency will reset on changes to currect clock mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fll filter and FLL frequency retain their previous values during new clock mode change.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMF</name>
<description>Automatic Trim Machine Fail Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Automatic Trim Machine completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Automatic Trim Machine failed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMS</name>
<description>Automatic Trim Machine Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>32 kHz Internal Reference Clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>4 MHz Internal Reference Clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATME</name>
<description>Automatic Trim Machine Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto Trim Machine disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto Trim Machine enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ATCVH</name>
<description>MCG Auto Trim Compare Value High Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVH</name>
<description>ATM Compare Value High</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATCVL</name>
<description>MCG Auto Trim Compare Value Low Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVL</name>
<description>ATM Compare Value Low</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C7</name>
<description>MCG Control 7 Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OSCSEL</name>
<description>MCG OSC Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects Oscillator (OSCCLK).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Selects 32 kHz RTC Oscillator.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL32KREFSEL</name>
<description>MCG PLL 32Khz Reference Clock Select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Selects 32 kHz RTC Oscillator.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Selects 32 kHz IRC.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Selects FLL FRDIV clock.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C8</name>
<description>MCG Control 8 Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCS1</name>
<description>RTC Loss of Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loss of RTC has not occur.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of RTC has occur</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COARSE_LOLIE</name>
<description>Loss of Coarse Lock Interrrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt request is generated on coarse loss of lock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate an interrupt request on coarse loss of lock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CME1</name>
<description>Clock Monitor Enable1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External clock monitor is disabled for RTC clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock monitor is enabled for RTC clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOLRE</name>
<description>PLL Loss of Lock Reset Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a PLL loss of lock indication.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCRE1</name>
<description>Loss of Clock Reset Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a loss of RTC external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a loss of RTC external reference clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C9</name>
<description>MCG Control 9 Register</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COARSE_LOCK</name>
<description>Coarse Lock Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL is currently unlocked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is currently locked after first sample.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COARSE_LOLS</name>
<description>Coarse Loss of Lock Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL has not lost lock since COARSE_LOLS was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL has lost lock since COARSE_LOLS was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OSC</name>
<description>Oscillator</description>
<prependToName>OSC_</prependToName>
<baseAddress>0x40066000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<description>OSC Control Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SC16P</name>
<description>Oscillator 16 pF Capacitor Load Configure</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 16 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC8P</name>
<description>Oscillator 8 pF Capacitor Load Configure</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 8 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC4P</name>
<description>Oscillator 4 pF Capacitor Load Configure</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 4 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC2P</name>
<description>Oscillator 2 pF Capacitor Load Configure</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 2 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFSTEN</name>
<description>External Reference Stop Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERCLKEN</name>
<description>External Reference Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C0_</prependToName>
<baseAddress>0x40067000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0_I2C1</name>
<value>26</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter Register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>SSLT[15:8]</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>SSLT[7:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C1_</prependToName>
<baseAddress>0x40068000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0_I2C1</name>
<value>26</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter Register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>SSLT[15:8]</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>SSLT[7:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART0</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART0_</prependToName>
<baseAddress>0x4006A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x17</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0_UART1</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>no description available</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART1</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART1_</prependToName>
<baseAddress>0x4006B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0_UART1</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>no description available</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>C7816</name>
<description>UART 7816 Control Register</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ISO_7816E</name>
<description>ISO-7816 Functionality Enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISO-7816 functionality is turned off/not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISO-7816 functionality is turned on/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TTYPE</name>
<description>Transfer Type</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>T = 0 per the ISO-7816 specification.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>T = 1 per the ISO-7816 specification.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Detect Initial Character</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operating mode. Receiver does not seek to identify initial character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver searches for initial character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ANACK</name>
<description>Generate NACK on Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No NACK is automatically generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONACK</name>
<description>Generate NACK on Overflow</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The received data does not generate a NACK when the receipt of the data results in an overflow event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If the receiver buffer overflows, a NACK is automatically sent on a received character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IE7816</name>
<description>UART 7816 Interrupt Enable Register</description>
<addressOffset>0x19</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTE</name>
<description>Receive Threshold Exceeded Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[RXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[RXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXTE</name>
<description>Transmit Threshold Exceeded Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[TXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[TXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTVE</name>
<description>Guard Timer Violated Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[GTV] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[GTV] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITDE</name>
<description>Initial Character Detected Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[INITD] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[INITD] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWTE</name>
<description>Block Wait Timer Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[BWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[BWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWTE</name>
<description>Character Wait Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[CWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[CWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WTE</name>
<description>Wait Timer Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[WT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[WT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IS7816</name>
<description>UART 7816 Interrupt Status Register</description>
<addressOffset>0x1A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXT</name>
<description>Receive Threshold Exceeded Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXT</name>
<description>Transmit Threshold Exceeded Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTV</name>
<description>Guard Timer Violated Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A guard time (GT, CGT, or BGT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A guard time (GT, CGT, or BGT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITD</name>
<description>Initial Character Detected Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A valid initial character has not been received.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A valid initial character has been received.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWT</name>
<description>Block Wait Timer Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Block wait time (BWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Block wait time (BWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWT</name>
<description>Character Wait Timer Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Character wait time (CWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Character wait time (CWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WT</name>
<description>Wait Timer Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wait time (WT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wait time (WT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WP7816T0</name>
<description>UART 7816 Wait Parameter Register</description>
<alternateGroup>UART1</alternateGroup>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WI</name>
<description>Wait Time Integer (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816T1</name>
<description>UART 7816 Wait Parameter Register</description>
<alternateGroup>UART1</alternateGroup>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BWI</name>
<description>Block Wait Time Integer(C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CWI</name>
<description>Character Wait Time Integer (C7816[TTYPE] = 1)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WN7816</name>
<description>UART 7816 Wait N Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTN</name>
<description>Guard Band N</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WF7816</name>
<description>UART 7816 Wait FD Register</description>
<addressOffset>0x1D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTFD</name>
<description>FD Multiplier</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ET7816</name>
<description>UART 7816 Error Threshold Register</description>
<addressOffset>0x1E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTHRESHOLD</name>
<description>Receive NACK Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXTHRESHOLD</name>
<description>Transmit NACK Threshold</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXT asserts on the first NACK that is received.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXT asserts on the second NACK that is received.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TL7816</name>
<description>UART 7816 Transmit Length Register</description>
<addressOffset>0x1F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TLEN</name>
<description>Transmit Length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART2</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART2_</prependToName>
<baseAddress>0x4006C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x17</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART2_UART3</name>
<value>20</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>no description available</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART3</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART3_</prependToName>
<baseAddress>0x4006D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART2_UART3</name>
<value>20</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>no description available</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>C7816</name>
<description>UART 7816 Control Register</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ISO_7816E</name>
<description>ISO-7816 Functionality Enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISO-7816 functionality is turned off/not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISO-7816 functionality is turned on/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TTYPE</name>
<description>Transfer Type</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>T = 0 per the ISO-7816 specification.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>T = 1 per the ISO-7816 specification.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Detect Initial Character</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operating mode. Receiver does not seek to identify initial character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver searches for initial character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ANACK</name>
<description>Generate NACK on Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No NACK is automatically generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONACK</name>
<description>Generate NACK on Overflow</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The received data does not generate a NACK when the receipt of the data results in an overflow event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If the receiver buffer overflows, a NACK is automatically sent on a received character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IE7816</name>
<description>UART 7816 Interrupt Enable Register</description>
<addressOffset>0x19</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTE</name>
<description>Receive Threshold Exceeded Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[RXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[RXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXTE</name>
<description>Transmit Threshold Exceeded Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[TXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[TXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTVE</name>
<description>Guard Timer Violated Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[GTV] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[GTV] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITDE</name>
<description>Initial Character Detected Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[INITD] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[INITD] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWTE</name>
<description>Block Wait Timer Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[BWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[BWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWTE</name>
<description>Character Wait Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[CWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[CWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WTE</name>
<description>Wait Timer Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[WT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[WT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IS7816</name>
<description>UART 7816 Interrupt Status Register</description>
<addressOffset>0x1A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXT</name>
<description>Receive Threshold Exceeded Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXT</name>
<description>Transmit Threshold Exceeded Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTV</name>
<description>Guard Timer Violated Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A guard time (GT, CGT, or BGT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A guard time (GT, CGT, or BGT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITD</name>
<description>Initial Character Detected Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A valid initial character has not been received.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A valid initial character has been received.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWT</name>
<description>Block Wait Timer Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Block wait time (BWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Block wait time (BWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWT</name>
<description>Character Wait Timer Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Character wait time (CWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Character wait time (CWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WT</name>
<description>Wait Timer Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wait time (WT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wait time (WT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WP7816T0</name>
<description>UART 7816 Wait Parameter Register</description>
<alternateGroup>UART3</alternateGroup>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WI</name>
<description>Wait Time Integer (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816T1</name>
<description>UART 7816 Wait Parameter Register</description>
<alternateGroup>UART3</alternateGroup>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BWI</name>
<description>Block Wait Time Integer(C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CWI</name>
<description>Character Wait Time Integer (C7816[TTYPE] = 1)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WN7816</name>
<description>UART 7816 Wait N Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTN</name>
<description>Guard Band N</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WF7816</name>
<description>UART 7816 Wait FD Register</description>
<addressOffset>0x1D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTFD</name>
<description>FD Multiplier</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ET7816</name>
<description>UART 7816 Error Threshold Register</description>
<addressOffset>0x1E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTHRESHOLD</name>
<description>Receive NACK Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXTHRESHOLD</name>
<description>Transmit NACK Threshold</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXT asserts on the first NACK that is received.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXT asserts on the second NACK that is received.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TL7816</name>
<description>UART 7816 Transmit Length Register</description>
<addressOffset>0x1F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TLEN</name>
<description>Transmit Length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VREF</name>
<description>Voltage Reference</description>
<prependToName>VREF_</prependToName>
<baseAddress>0x4006F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>VREFH_TRM</name>
<description>VREF Trim Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x40</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>Trim bits</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000000</name>
<description>Min</description>
<value>#000000</value>
</enumeratedValue>
<enumeratedValue>
<name>111111</name>
<description>Max</description>
<value>#111111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHOPEN</name>
<description>Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Chop oscillator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Chop oscillator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>VREFH_SC</name>
<description>VREF Status and Control Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE_LV</name>
<description>Buffer Mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bandgap on only, for stabilization and startup</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>High power buffer mode enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Low-power buffer mode enabled</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFST</name>
<description>Internal Voltage Reference stable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The module is disabled or not stable.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The module is stable.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ICOMPEN</name>
<description>Second order curvature compensation enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGEN</name>
<description>Regulator enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 1.75 V regulator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 1.75 V regulator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFEN</name>
<description>Internal Voltage Reference enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The module is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The module is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>VREFL_TRM</name>
<description>VREFL TRIM Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF8</resetMask>
<fields>
<field>
<name>VREFL_TRIM</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VREFL_EN</name>
<description>no description available</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFL_SEL</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal reference</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP0</name>
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
<groupName>CMP</groupName>
<prependToName>CMP0_</prependToName>
<baseAddress>0x40072000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP0_CMP1</name>
<value>14</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>CMP Control Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HYSTCTR</name>
<description>Comparator hard block hysteresis control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Level 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Level 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Level 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Level 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_CNT</name>
<description>Filter Sample Count</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>One sample must agree. The comparator output is simply sampled.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 consecutive samples must agree.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>3 consecutive samples must agree.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>4 consecutive samples must agree.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>5 consecutive samples must agree.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>6 consecutive samples must agree.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>7 consecutive samples must agree.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>CMP Control Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>Comparator Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Analog Comparator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Analog Comparator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPE</name>
<description>Comparator Output Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMPO is not available on the associated CMPO output pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMPO is available on the associated CMPO output pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COS</name>
<description>Comparator Output Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Comparator INVERT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Does not invert the comparator output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverts the comparator output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMODE</name>
<description>Power Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGM</name>
<description>Trigger Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WE</name>
<description>Windowing Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Sample Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sampling mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sampling mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FPR</name>
<description>CMP Filter Period Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>CMP Status and Control Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COUT</name>
<description>Analog Comparator Output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFF</name>
<description>Analog Comparator Flag Falling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFR</name>
<description>Analog Comparator Flag Rising</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEF</name>
<description>Comparator Interrupt Enable Falling</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IER</name>
<description>Comparator Interrupt Enable Rising</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACCR</name>
<description>DAC Control Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VOSEL</name>
<description>DAC Output Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRSEL</name>
<description>Supply Voltage Reference Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Vin1 is selected as resistor ladder network supply reference.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Vin2 is selected as resistor ladder network supply reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MUXCR</name>
<description>MUX Control Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Minus Input Mux Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSEL</name>
<description>Plus Input Mux Control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP1</name>
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
<groupName>CMP</groupName>
<prependToName>CMP1_</prependToName>
<baseAddress>0x40072008</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP0_CMP1</name>
<value>14</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>CMP Control Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HYSTCTR</name>
<description>Comparator hard block hysteresis control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Level 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Level 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Level 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Level 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_CNT</name>
<description>Filter Sample Count</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>One sample must agree. The comparator output is simply sampled.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 consecutive samples must agree.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>3 consecutive samples must agree.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>4 consecutive samples must agree.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>5 consecutive samples must agree.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>6 consecutive samples must agree.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>7 consecutive samples must agree.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>CMP Control Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>Comparator Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Analog Comparator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Analog Comparator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPE</name>
<description>Comparator Output Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMPO is not available on the associated CMPO output pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMPO is available on the associated CMPO output pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COS</name>
<description>Comparator Output Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Comparator INVERT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Does not invert the comparator output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverts the comparator output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMODE</name>
<description>Power Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGM</name>
<description>Trigger Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WE</name>
<description>Windowing Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Sample Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sampling mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sampling mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FPR</name>
<description>CMP Filter Period Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>CMP Status and Control Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COUT</name>
<description>Analog Comparator Output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFF</name>
<description>Analog Comparator Flag Falling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFR</name>
<description>Analog Comparator Flag Rising</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEF</name>
<description>Comparator Interrupt Enable Falling</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IER</name>
<description>Comparator Interrupt Enable Rising</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACCR</name>
<description>DAC Control Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VOSEL</name>
<description>DAC Output Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRSEL</name>
<description>Supply Voltage Reference Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Vin1 is selected as resistor ladder network supply reference.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Vin2 is selected as resistor ladder network supply reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MUXCR</name>
<description>MUX Control Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Minus Input Mux Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSEL</name>
<description>Plus Input Mux Control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI0_</prependToName>
<baseAddress>0x40075000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>4</value>
</interrupt>
<registers>
<register>
<name>S</name>
<description>SPI Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RFIFOEF</name>
<description>SPI read FIFO empty flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read FIFO is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFULLF</name>
<description>Transmit FIFO full flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has less than 8 bytes</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has 8 bytes of data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF</name>
<description>Transmit FIFO nearly empty flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF</name>
<description>Receive FIFO nearly full flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODF</name>
<description>Master Mode Fault Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No mode fault error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTEF</name>
<description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMF</name>
<description>SPI Match Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Value in the receive data buffer matches the value in the MH:ML registers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPRF</name>
<description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BR</name>
<description>SPI Baud Rate Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPR</name>
<description>SPI Baud Rate Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Baud rate divisor is 2.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Baud rate divisor is 4.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Baud rate divisor is 8.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Baud rate divisor is 16.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Baud rate divisor is 32.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Baud rate divisor is 64.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Baud rate divisor is 128.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Baud rate divisor is 256.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Baud rate divisor is 512.</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPPR</name>
<description>SPI Baud Rate Prescale Divisor</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Baud rate prescaler divisor is 1.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Baud rate prescaler divisor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Baud rate prescaler divisor is 3.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Baud rate prescaler divisor is 4.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Baud rate prescaler divisor is 5.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Baud rate prescaler divisor is 6.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Baud rate prescaler divisor is 7.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Baud rate prescaler divisor is 8.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>SPI Control Register 2</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPC0</name>
<description>SPI Pin Control 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPISWAI</name>
<description>SPI Stop in Wait Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI clocks continue to operate in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI clocks stop when the MCU enters Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDMAE</name>
<description>Receive DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIDIROE</name>
<description>Bidirectional Mode Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI I/O pin enabled as an output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODFEN</name>
<description>Master Mode-Fault Function Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDMAE</name>
<description>Transmit DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIMODE</name>
<description>SPI 8-bit or 16-bit mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>8-bit SPI shift register, match register, and buffers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>16-bit SPI shift register, match register, and buffers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMIE</name>
<description>SPI Match Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPMF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPMF is 1, requests a hardware interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>SPI Control Register 1</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LSBFE</name>
<description>LSB First (shifter direction)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI serial data transfers start with the most significant bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI serial data transfers start with the least significant bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSOE</name>
<description>Slave Select Output Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Active-high SPI clock (idles low)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Active-low SPI clock (idles high)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI module configured as a slave SPI device</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI module configured as a master SPI device</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTIE</name>
<description>SPI Transmit Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPTEF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPTEF is 1, hardware interrupt requested</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPE</name>
<description>SPI System Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI system inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI system enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIE</name>
<description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ML</name>
<description>SPI Match Register low</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MH</name>
<description>SPI match register high</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DL</name>
<description>SPI Data Register low</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DH</name>
<description>SPI data register high</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CI</name>
<description>SPI clear interrupt register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPRFCI</name>
<description>Receive FIFO full flag clear interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SPTEFCI</name>
<description>Transmit FIFO empty flag clear interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RNFULLFCI</name>
<description>Receive FIFO nearly full flag clear interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TNEAREFCI</name>
<description>Transmit FIFO nearly empty flag clear interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXFOF</name>
<description>Receive FIFO overflow flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFOF</name>
<description>Transmit FIFO overflow flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFERR</name>
<description>Receive FIFO error flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A receive FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFERR</name>
<description>Transmit FIFO error flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transmit FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>SPI control register 3</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FIFOMODE</name>
<description>FIFO mode enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer mode disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLIEN</name>
<description>Receive FIFO nearly full interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon RNFULLF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon RNFULLF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEARIEN</name>
<description>Transmit FIFO nearly empty interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon TNEAREF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon TNEAREF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTCLR</name>
<description>Interrupt clearing mechanism select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>These interrupts are cleared by writing the corresponding bits in the CI register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF_MARK</name>
<description>Receive FIFO nearly full watermark</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RNFULLF is set when the receive FIFO has 48 bits or more</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RNFULLF is set when the receive FIFO has 32 bits or more</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF_MARK</name>
<description>Transmit FIFO nearly empty watermark</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TNEAREF is set when the transmit FIFO has 16 bits or less</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TNEAREF is set when the transmit FIFO has 32 bits or less</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI1_</prependToName>
<baseAddress>0x40076000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<value>5</value>
</interrupt>
<registers>
<register>
<name>S</name>
<description>SPI Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RFIFOEF</name>
<description>SPI read FIFO empty flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read FIFO is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFULLF</name>
<description>Transmit FIFO full flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has less than 8 bytes</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has 8 bytes of data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF</name>
<description>Transmit FIFO nearly empty flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF</name>
<description>Receive FIFO nearly full flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODF</name>
<description>Master Mode Fault Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No mode fault error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTEF</name>
<description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMF</name>
<description>SPI Match Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Value in the receive data buffer matches the value in the MH:ML registers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPRF</name>
<description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BR</name>
<description>SPI Baud Rate Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPR</name>
<description>SPI Baud Rate Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Baud rate divisor is 2.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Baud rate divisor is 4.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Baud rate divisor is 8.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Baud rate divisor is 16.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Baud rate divisor is 32.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Baud rate divisor is 64.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Baud rate divisor is 128.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Baud rate divisor is 256.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Baud rate divisor is 512.</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPPR</name>
<description>SPI Baud Rate Prescale Divisor</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Baud rate prescaler divisor is 1.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Baud rate prescaler divisor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Baud rate prescaler divisor is 3.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Baud rate prescaler divisor is 4.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Baud rate prescaler divisor is 5.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Baud rate prescaler divisor is 6.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Baud rate prescaler divisor is 7.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Baud rate prescaler divisor is 8.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>SPI Control Register 2</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPC0</name>
<description>SPI Pin Control 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPISWAI</name>
<description>SPI Stop in Wait Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI clocks continue to operate in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI clocks stop when the MCU enters Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDMAE</name>
<description>Receive DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIDIROE</name>
<description>Bidirectional Mode Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI I/O pin enabled as an output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODFEN</name>
<description>Master Mode-Fault Function Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDMAE</name>
<description>Transmit DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIMODE</name>
<description>SPI 8-bit or 16-bit mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>8-bit SPI shift register, match register, and buffers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>16-bit SPI shift register, match register, and buffers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMIE</name>
<description>SPI Match Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPMF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPMF is 1, requests a hardware interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>SPI Control Register 1</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LSBFE</name>
<description>LSB First (shifter direction)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI serial data transfers start with the most significant bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI serial data transfers start with the least significant bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSOE</name>
<description>Slave Select Output Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Active-high SPI clock (idles low)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Active-low SPI clock (idles high)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI module configured as a slave SPI device</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI module configured as a master SPI device</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTIE</name>
<description>SPI Transmit Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPTEF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPTEF is 1, hardware interrupt requested</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPE</name>
<description>SPI System Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI system inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI system enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIE</name>
<description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ML</name>
<description>SPI Match Register low</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MH</name>
<description>SPI match register high</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DL</name>
<description>SPI Data Register low</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DH</name>
<description>SPI data register high</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CI</name>
<description>SPI clear interrupt register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPRFCI</name>
<description>Receive FIFO full flag clear interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SPTEFCI</name>
<description>Transmit FIFO empty flag clear interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RNFULLFCI</name>
<description>Receive FIFO nearly full flag clear interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TNEAREFCI</name>
<description>Transmit FIFO nearly empty flag clear interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXFOF</name>
<description>Receive FIFO overflow flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFOF</name>
<description>Transmit FIFO overflow flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFERR</name>
<description>Receive FIFO error flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A receive FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFERR</name>
<description>Transmit FIFO error flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transmit FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>SPI control register 3</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FIFOMODE</name>
<description>FIFO mode enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer mode disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLIEN</name>
<description>Receive FIFO nearly full interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon RNFULLF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon RNFULLF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEARIEN</name>
<description>Transmit FIFO nearly empty interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon TNEAREF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon TNEAREF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTCLR</name>
<description>Interrupt clearing mechanism select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>These interrupts are cleared by writing the corresponding bits in the CI register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF_MARK</name>
<description>Receive FIFO nearly full watermark</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RNFULLF is set when the receive FIFO has 48 bits or more</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RNFULLF is set when the receive FIFO has 32 bits or more</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF_MARK</name>
<description>Transmit FIFO nearly empty watermark</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TNEAREF is set when the transmit FIFO has 16 bits or less</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TNEAREF is set when the transmit FIFO has 32 bits or less</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCM</name>
<description>Reset Control Module</description>
<prependToName>RCM_</prependToName>
<baseAddress>0x4007B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SRS0</name>
<description>System Reset Status Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x82</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WAKEUP</name>
<description>Low Leakage Wakeup Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVD</name>
<description>Low-Voltage Detect Reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LVD trip or POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LVD trip or POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOC</name>
<description>Loss-of-Clock Reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of external clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of external clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOL</name>
<description>Loss-of-Lock Reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of lock in the PLL</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of lock in the PLL</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDOG</name>
<description>Watchdog</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by watchdog timeout</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by watchdog timeout</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIN</name>
<description>External Reset Pin</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by external reset pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by external reset pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POR</name>
<description>Power-On Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRS1</name>
<description>System Reset Status Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCKUP</name>
<description>Core Lockup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by core LOCKUP event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by core LOCKUP event</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SW</name>
<description>Software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by software setting of SYSRESETREQ bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDM_AP</name>
<description>MDM-AP System Reset Request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by host debugger system setting of the System Reset Request bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SACKERR</name>
<description>Stop Mode Acknowledge Error Reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFC</name>
<description>Reset Pin Filter Control register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSRW</name>
<description>Reset Pin Filter Select in Run and Wait Modes</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>All filtering disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bus clock filter enabled for normal operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>LPO clock filter enabled for normal operation</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTFLTSS</name>
<description>Reset Pin Filter Select in Stop Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All filtering disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPO clock filter enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFW</name>
<description>Reset Pin Filter Width register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSEL</name>
<description>Reset Pin Filter Bus Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>Bus clock filter count is 1</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>Bus clock filter count is 2</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>Bus clock filter count is 3</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>Bus clock filter count is 4</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>Bus clock filter count is 5</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>Bus clock filter count is 6</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>Bus clock filter count is 7</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>Bus clock filter count is 8</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>Bus clock filter count is 9</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>Bus clock filter count is 10</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>Bus clock filter count is 11</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>Bus clock filter count is 12</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>Bus clock filter count is 13</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>Bus clock filter count is 14</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>Bus clock filter count is 15</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>Bus clock filter count is 16</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>Bus clock filter count is 17</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>Bus clock filter count is 18</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>Bus clock filter count is 19</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>Bus clock filter count is 20</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>Bus clock filter count is 21</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>Bus clock filter count is 22</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>Bus clock filter count is 23</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>Bus clock filter count is 24</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11000</name>
<description>Bus clock filter count is 25</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>11001</name>
<description>Bus clock filter count is 26</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>Bus clock filter count is 27</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>Bus clock filter count is 28</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11100</name>
<description>Bus clock filter count is 29</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>Bus clock filter count is 30</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>Bus clock filter count is 31</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Bus clock filter count is 32</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LLWU</name>
<description>Low leakage wakeup unit</description>
<prependToName>LLWU_</prependToName>
<baseAddress>0x4007C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LLWU</name>
<value>12</value>
</interrupt>
<registers>
<register>
<name>PE1</name>
<description>LLWU Pin Enable 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE0</name>
<description>Wakeup Pin Enable For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE1</name>
<description>Wakeup Pin Enable For LLWU_P1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE2</name>
<description>Wakeup Pin Enable For LLWU_P2</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE3</name>
<description>Wakeup Pin Enable For LLWU_P3</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE2</name>
<description>LLWU Pin Enable 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE4</name>
<description>Wakeup Pin Enable For LLWU_P4</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE5</name>
<description>Wakeup Pin Enable For LLWU_P5</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE6</name>
<description>Wakeup Pin Enable For LLWU_P6</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE7</name>
<description>Wakeup Pin Enable For LLWU_P7</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE3</name>
<description>LLWU Pin Enable 3 register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE8</name>
<description>Wakeup Pin Enable For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE9</name>
<description>Wakeup Pin Enable For LLWU_P9</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE10</name>
<description>Wakeup Pin Enable For LLWU_P10</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE11</name>
<description>Wakeup Pin Enable For LLWU_P11</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE4</name>
<description>LLWU Pin Enable 4 register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE12</name>
<description>Wakeup Pin Enable For LLWU_P12</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE13</name>
<description>Wakeup Pin Enable For LLWU_P13</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE14</name>
<description>Wakeup Pin Enable For LLWU_P14</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE15</name>
<description>Wakeup Pin Enable For LLWU_P15</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ME</name>
<description>LLWU Module Enable register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUME0</name>
<description>Wakeup Module Enable For Module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME1</name>
<description>Wakeup Module Enable for Module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME2</name>
<description>Wakeup Module Enable For Module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME3</name>
<description>Wakeup Module Enable For Module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME4</name>
<description>Wakeup Module Enable For Module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME5</name>
<description>Wakeup Module Enable For Module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME6</name>
<description>Wakeup Module Enable For Module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME7</name>
<description>Wakeup Module Enable For Module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F1</name>
<description>LLWU Flag 1 register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF0</name>
<description>Wakeup Flag For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF1</name>
<description>Wakeup Flag For LLWU_P1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF2</name>
<description>Wakeup Flag For LLWU_P2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF3</name>
<description>Wakeup Flag For LLWU_P3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P3 input was not a wake-up source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P3 input was a wake-up source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF4</name>
<description>Wakeup Flag For LLWU_P4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF5</name>
<description>Wakeup Flag For LLWU_P5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF6</name>
<description>Wakeup Flag For LLWU_P6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF7</name>
<description>Wakeup Flag For LLWU_P7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F2</name>
<description>LLWU Flag 2 register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF8</name>
<description>Wakeup Flag For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P8 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P8 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF9</name>
<description>Wakeup Flag For LLWU_P9</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P9 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P9 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF10</name>
<description>Wakeup Flag For LLWU_P10</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P10 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P10 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF11</name>
<description>Wakeup Flag For LLWU_P11</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P11 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P11 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF12</name>
<description>Wakeup Flag For LLWU_P12</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P12 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P12 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF13</name>
<description>Wakeup Flag For LLWU_P13</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P13 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P13 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF14</name>
<description>Wakeup Flag For LLWU_P14</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P14 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P14 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF15</name>
<description>Wakeup Flag For LLWU_P15</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P15 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P15 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F3</name>
<description>LLWU Flag 3 register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MWUF0</name>
<description>Wakeup flag For module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF1</name>
<description>Wakeup flag For module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF2</name>
<description>Wakeup flag For module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF3</name>
<description>Wakeup flag For module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 3 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 3 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF4</name>
<description>Wakeup flag For module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF5</name>
<description>Wakeup flag For module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF6</name>
<description>Wakeup flag For module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF7</name>
<description>Wakeup flag For module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT1</name>
<description>LLWU Pin Filter 1 register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 1 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 1 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT2</name>
<description>LLWU Pin Filter 2 register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 2 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 2 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMC</name>
<description>Power Management Controller</description>
<prependToName>PMC_</prependToName>
<baseAddress>0x4007D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PMC</name>
<value>6</value>
</interrupt>
<registers>
<register>
<name>LVDSC1</name>
<description>Low Voltage Detect Status And Control 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVDV</name>
<description>Low-Voltage Detect Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (V LVD = V LVDL )</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>High trip point selected (V LVD = V LVDH )</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDRE</name>
<description>Low-Voltage Detect Reset Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LVDF does not generate hardware resets</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force an MCU reset when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDIE</name>
<description>Low-Voltage Detect Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDACK</name>
<description>Low-Voltage Detect Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVDF</name>
<description>Low-Voltage Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LVDSC2</name>
<description>Low Voltage Detect Status And Control 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVWV</name>
<description>Low-Voltage Warning Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (VLVW = VLVW1)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mid 1 trip point selected (VLVW = VLVW2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mid 2 trip point selected (VLVW = VLVW3)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>High trip point selected (VLVW = VLVW4)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWIE</name>
<description>Low-Voltage Warning Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVWF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWACK</name>
<description>Low-Voltage Warning Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVWF</name>
<description>Low-Voltage Warning Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage warning event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage warning event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>REGSC</name>
<description>Regulator Status And Control register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BGBE</name>
<description>Bandgap Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap buffer not enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap buffer enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BGBDS</name>
<description>Bandgap Buffer Drive Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGONS</name>
<description>Regulator In Run Regulation Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Regulator is in stop regulation or in transition to/from it</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Regulator is in run regulation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKISO</name>
<description>Acknowledge Isolation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripherals and I/O pads are in normal run state.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Certain peripherals and I/O pads are in an isolated and latched state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BGEN</name>
<description>Bandgap Enable In VLPx Operation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap voltage reference is disabled in VLPx , and VLLSx modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap voltage reference is enabled in VLPx , and VLLSx modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SMC</name>
<description>System Mode Controller</description>
<prependToName>SMC_</prependToName>
<baseAddress>0x4007E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PMPROT</name>
<description>Power Mode Protection register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVLLS</name>
<description>Allow Very-Low-Leakage Stop Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Any VLLSx mode is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Any VLLSx mode is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVLP</name>
<description>Allow Very-Low-Power Modes</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>VLPR, VLPW, and VLPS are not allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>VLPR, VLPW, and VLPS are allowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Power Mode Control register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>STOPM</name>
<description>Stop Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Normal Stop (STOP)</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Very-Low-Power Stop (VLPS)</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Very-Low-Leakage Stop (VLLSx)</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Reseved</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPA</name>
<description>Stop Aborted</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The previous stop mode entry was successsful.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The previous stop mode entry was aborted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUNM</name>
<description>Run Mode Control</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Normal Run mode (RUN)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Very-Low-Power Run mode (VLPR)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STOPCTRL</name>
<description>Stop Control Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VLLSM</name>
<description>VLLS Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>VLLS0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>VLLS1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>VLLS2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>VLLS3</description>
<value>#011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORPO</name>
<description>POR Power Option</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>POR detect circuit is enabled in VLLS0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>POR detect circuit is disabled in VLLS0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSTOPO</name>
<description>Partial Stop Option</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>STOP - Normal Stop mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMSTAT</name>
<description>Power Mode Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PMSTAT</name>
<description>Power Mode Status</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOA_</prependToName>
<baseAddress>0x400FF000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOB_</prependToName>
<baseAddress>0x400FF001</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOC</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOC_</prependToName>
<baseAddress>0x400FF002</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOD</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOD_</prependToName>
<baseAddress>0x400FF003</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOE</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOE_</prependToName>
<baseAddress>0x400FF040</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOF</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOF_</prependToName>
<baseAddress>0x400FF041</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOG</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOG_</prependToName>
<baseAddress>0x400FF042</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOH</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOH_</prependToName>
<baseAddress>0x400FF043</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOI</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOI_</prependToName>
<baseAddress>0x400FF080</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PTx</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GACR</name>
<description>GPIO Attribute Checker Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACB</name>
<description>Attribute Check Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read + Write</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: Read</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>User nonsecure: None; User Secure: None; Privileged Secure: None</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROB</name>
<description>Read-Only Byte</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ACB are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ACB are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MTB</name>
<description>Micro Trace Buffer</description>
<prependToName>MTB_</prependToName>
<baseAddress>0xF0000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>POSITION</name>
<description>MTB Position Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>WRAP</name>
<description>WRAP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POINTER</name>
<description>Trace Packet Address Pointer[28:0]</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASTER</name>
<description>MTB Master Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFE0</resetMask>
<fields>
<field>
<name>MASK</name>
<description>Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSTARTEN</name>
<description>Trace Start Input Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSTOPEN</name>
<description>Trace Stop Input Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SFRWPRIV</name>
<description>Special Function Register Write Privilege</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RAMPRIV</name>
<description>RAM Privilege</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HALTREQ</name>
<description>Halt Request</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EN</name>
<description>Main Trace Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLOW</name>
<description>MTB Flow Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x4</resetMask>
<fields>
<field>
<name>AUTOSTOP</name>
<description>AUTOSTOP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AUTOHALT</name>
<description>AUTOHALT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WATERMARK</name>
<description>WATERMARK[28:0]</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BASE</name>
<description>MTB Base Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>BASEADDR</name>
<description>BASEADDR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MODECTRL</name>
<description>Integration Mode Control Register</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODECTRL</name>
<description>MODECTRL</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TAGSET</name>
<description>Claim TAG Set Register</description>
<addressOffset>0xFA0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TAGSET</name>
<description>TAGSET</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TAGCLEAR</name>
<description>Claim TAG Clear Register</description>
<addressOffset>0xFA4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TAGCLEAR</name>
<description>TAGCLEAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LOCKACCESS</name>
<description>Lock Access Register</description>
<addressOffset>0xFB0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCKACCESS</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LOCKSTAT</name>
<description>Lock Status Register</description>
<addressOffset>0xFB4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCKSTAT</name>
<description>LOCKSTAT</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>AUTHSTAT</name>
<description>Authentication Status Register</description>
<addressOffset>0xFB8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BIT0</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT1</name>
<description>BIT1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT2</name>
<description>BIT2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT3</name>
<description>BIT3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICEARCH</name>
<description>Device Architecture Register</description>
<addressOffset>0xFBC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x47700A31</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICEARCH</name>
<description>DEVICEARCH</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICECFG</name>
<description>Device Configuration Register</description>
<addressOffset>0xFC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICECFG</name>
<description>DEVICECFG</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICETYPID</name>
<description>Device Type Identifier Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x31</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICETYPID</name>
<description>DEVICETYPID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>PERIPHID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MTBDWT</name>
<description>MTB data watchpoint and trace</description>
<prependToName>MTBDWT_</prependToName>
<baseAddress>0xF0001000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>MTB DWT Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x2F000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DWTCFGCTRL</name>
<description>DWT configuration controls</description>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUMCMP</name>
<description>Number of comparators</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>COMP%s</name>
<description>MTB_DWT Comparator Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMP</name>
<description>Reference value for comparison</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>MASK%s</name>
<description>MTB_DWT Comparator Mask Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASK</name>
<description>MASK</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FCT0</name>
<description>MTB_DWT Comparator Function Register 0</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNCTION</name>
<description>Function</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Instruction fetch.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Data operand read.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Data operand write.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Data operand (read + write).</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVMATCH</name>
<description>Data Value Match</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Perform address comparison.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Perform data value comparison.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVSIZE</name>
<description>Data Value Size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Byte.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halfword.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Word.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVADDR0</name>
<description>Data Value Address 0</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MATCHED</name>
<description>Comparator match</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No match.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Match occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCT1</name>
<description>MTB_DWT Comparator Function Register 1</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNCTION</name>
<description>Function</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Instruction fetch.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Data operand read.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Data operand write.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Data operand (read + write).</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATCHED</name>
<description>Comparator match</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No match.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Match occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TBCTRL</name>
<description>MTB_DWT Trace Buffer Control Register</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ACOMP0</name>
<description>Action based on Comparator 0 match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACOMP1</name>
<description>Action based on Comparator 1 match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NUMCOMP</name>
<description>Number of Comparators</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICECFG</name>
<description>Device Configuration Register</description>
<addressOffset>0xFC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICECFG</name>
<description>DEVICECFG</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICETYPID</name>
<description>Device Type Identifier Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICETYPID</name>
<description>DEVICETYPID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>PERIPHID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ROM</name>
<description>System ROM</description>
<prependToName>ROM_</prependToName>
<baseAddress>0xF0002000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2</dimIndex>
<name>ENTRY%s</name>
<description>Entry</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>ENTRY</name>
<description>ENTRY</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TABLEMARK</name>
<description>End of Table Marker Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MARK</name>
<description>MARK</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SYSACCESS</name>
<description>System Access Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSACCESS</name>
<description>SYSACCESS</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>PERIPHID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCM</name>
<description>Core Platform Miscellaneous Control Module</description>
<prependToName>MCM_</prependToName>
<baseAddress>0xF0003000</baseAddress>
<addressBlock>
<offset>0x8</offset>
<size>0x7C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PLASC</name>
<description>Crossbar Switch (AXBS) Slave Configuration</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0x7</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ASC</name>
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch&apos;s slave input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus slave connection to AXBS input port n is absent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus slave connection to AXBS input port n is present.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLAMC</name>
<description>Crossbar Switch (AXBS) Master Configuration</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>AMC</name>
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus master connection to AXBS input port n is absent</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus master connection to AXBS input port n is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLACR</name>
<description>Platform Control Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x50</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ARB</name>
<description>Arbitration select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fixed-priority arbitration for the crossbar masters</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Round-robin arbitration for the crossbar masters</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFCC</name>
<description>Clear Flash Controller Cache</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DFCDA</name>
<description>Disable Flash Controller Data Caching</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller data caching</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller data caching.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCIC</name>
<description>Disable Flash Controller Instruction Caching</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller instruction caching.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller instruction caching.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCC</name>
<description>Disable Flash Controller Cache</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller cache.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller cache.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EFDS</name>
<description>Enable Flash Data Speculation</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable flash data speculation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable flash data speculation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCS</name>
<description>Disable Flash Controller Speculation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller speculation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller speculation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ESFC</name>
<description>Enable Stalling Flash Controller</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable stalling flash controller when flash is busy.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable stalling flash controller when flash is busy.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PID</name>
<description>Process ID register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PID</name>
<description>M0_PID For MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reserved for privileged secure tasks</description>
<value>#0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CPO</name>
<description>Compute Operation Control Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPOREQ</name>
<description>Compute Operation Request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Request is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request Compute Operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOACK</name>
<description>Compute Operation Acknowledge</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compute operation entry has not completed or compute operation exit has completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compute operation entry has completed or compute operation exit has not completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOWOI</name>
<description>Compute Operation Wake-up on Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MATCR</name>
<description>Master Attribute Configuration Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ATC0</name>
<description>Attribute Configuration Master n</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00x</name>
<description>Master attributes are statically forced to {privileged, secure}.</description>
<value>#00x</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Master attributes are statically forced to {user, secure}.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Master attributes are statically forced to {user, nonsecure}.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Enable master attribute {privileged or user} and statically force {secure}.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Enable master attribute {privileged or user} and statically force {nonsecure}.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>11x</name>
<description>Enable master attribute {privileged or user, secure or nonsecure}</description>
<value>#11x</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RO0</name>
<description>Read-Only Master n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ATCn are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ATCn are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATC2</name>
<description>Attribute Configuration Master n</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00x</name>
<description>Master attributes are statically forced to {privileged, secure}.</description>
<value>#00x</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Master attributes are statically forced to {user, secure}.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Master attributes are statically forced to {user, nonsecure}.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Enable master attribute {privileged or user} and statically force {secure}.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Enable master attribute {privileged or user} and statically force {nonsecure}.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>11x</name>
<description>Enable master attribute {privileged or user, secure or nonsecure}</description>
<value>#11x</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RO2</name>
<description>Read-Only Master n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the ATCn are allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the ATCn are ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>