12128 lines
467 KiB
XML
12128 lines
467 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>Freescale Semiconductor, Inc.</vendor>
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<vendorID>Freescale</vendorID>
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<series>Kinetis_L</series>
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<name>MKL02Z4</name>
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<version>1.6</version>
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<description>MKL02Z4 Freescale Microcontroller</description>
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<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
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<cpu>
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<name>CM0PLUS</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<mpuPresent>false</mpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>2</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>FTFA_FlashConfig</name>
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<description>Flash configuration field</description>
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<prependToName>NV_</prependToName>
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<baseAddress>0x400</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0xE</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>BACKKEY3</name>
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<description>Backdoor Comparison Key 3.</description>
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<addressOffset>0</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY2</name>
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<description>Backdoor Comparison Key 2.</description>
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<addressOffset>0x1</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY1</name>
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<description>Backdoor Comparison Key 1.</description>
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<addressOffset>0x2</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY0</name>
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<description>Backdoor Comparison Key 0.</description>
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<addressOffset>0x3</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY7</name>
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<description>Backdoor Comparison Key 7.</description>
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<addressOffset>0x4</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY6</name>
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<description>Backdoor Comparison Key 6.</description>
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<addressOffset>0x5</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY5</name>
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<description>Backdoor Comparison Key 5.</description>
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<addressOffset>0x6</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY4</name>
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<description>Backdoor Comparison Key 4.</description>
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<addressOffset>0x7</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT3</name>
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<description>Non-volatile P-Flash Protection 1 - Low Register</description>
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<addressOffset>0x8</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT2</name>
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<description>Non-volatile P-Flash Protection 1 - High Register</description>
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<addressOffset>0x9</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT1</name>
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<description>Non-volatile P-Flash Protection 0 - Low Register</description>
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<addressOffset>0xA</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT0</name>
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<description>Non-volatile P-Flash Protection 0 - High Register</description>
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<addressOffset>0xB</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FSEC</name>
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<description>Non-volatile Flash Security Register</description>
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<addressOffset>0xC</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>SEC</name>
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<description>Flash Security</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>MCU security status is unsecure</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>MCU security status is secure</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FSLACC</name>
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<description>Freescale Failure Analysis Access Code</description>
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<bitOffset>2</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>Freescale factory access denied</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>Freescale factory access granted</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MEEN</name>
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<description>no description available</description>
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<bitOffset>4</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>Mass erase is disabled</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>Mass erase is enabled</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>KEYEN</name>
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<description>Backdoor Key Security Enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>Backdoor key access enabled</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>Backdoor key access disabled</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>FOPT</name>
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<description>Non-volatile Flash Option Register</description>
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<addressOffset>0xD</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>LPBOOT0</name>
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<description>no description available</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>00</name>
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<description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.</description>
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<value>#0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>01</name>
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<description>Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.</description>
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>NMI_DIS</name>
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<description>no description available</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>00</name>
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<description>NMI interrupts are always blocked</description>
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<value>#0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>01</name>
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<description>NMI_b pin/interrupts reset default to enabled</description>
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>RESET_PIN_CFG</name>
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<description>no description available</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>00</name>
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<description>RESET pin is disabled following a POR and cannot be enabled as reset function</description>
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<value>#0</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>01</name>
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|
<description>RESET_b pin is dedicated</description>
|
|
<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>LPBOOT1</name>
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|
<description>no description available</description>
|
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<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAST_INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Slower initialization</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fast Initialization</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTFA</name>
|
|
<description>Flash Memory Interface</description>
|
|
<prependToName>FTFA_</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTFA</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FSTAT</name>
|
|
<description>Flash Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MGSTAT0</name>
|
|
<description>Memory Controller Command Completion Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVIOL</name>
|
|
<description>Flash Protection Violation Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No protection violation detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection violation detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCERR</name>
|
|
<description>Flash Access Error Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No access error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLERR</name>
|
|
<description>Flash Read Collision Error Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No collision error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Collision error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIF</name>
|
|
<description>Command Complete Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash command in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash command has completed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCNFG</name>
|
|
<description>Flash Configuration Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERSSUSP</name>
|
|
<description>Erase Suspend</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No suspend requested</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Suspend the current Erase Flash Sector command execution.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERSAREQ</name>
|
|
<description>Erase All Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No request or request complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLLIE</name>
|
|
<description>Read Collision Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read collision error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Command Complete Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command complete interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSEC</name>
|
|
<description>Flash Security Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Flash Security</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLACC</name>
|
|
<description>Freescale Failure Analysis Access Code</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEEN</name>
|
|
<description>Mass Erase Enable Bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mass erase is disabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYEN</name>
|
|
<description>Backdoor Key Security Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Backdoor key access enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOPT</name>
|
|
<description>Flash Option Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPT</name>
|
|
<description>Nonvolatile Option</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
|
|
<name>FCCOB%s</name>
|
|
<description>Flash Common Command Object Registers</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOBn</name>
|
|
<description>The FCCOB register provides a command code and relevant parameters to the memory controller</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0</dimIndex>
|
|
<name>FPROT%s</name>
|
|
<description>Program Flash Protection Registers</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT</name>
|
|
<description>Program Flash Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Program flash region is protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Program flash region is not protected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TPM0</name>
|
|
<description>Timer/PWM Module</description>
|
|
<groupName>TPM</groupName>
|
|
<prependToName>TPM0_</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TPM0</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>Clock Mode Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>LPTPM counter is disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>LPTPM counter increments on every LPTPM counter clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter operates in up counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter operates in up-down counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling or DMA request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status and Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture and Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal LPTPM counter continues in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>LPTPM counter continues in debug mode.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global time base enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All channels use the internally generated LPTPM counter as their timebase</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All channels use an externally generated global timebase as their timebase</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSOT</name>
|
|
<description>Counter Start on Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter starts to increment immediately, once it is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSOO</name>
|
|
<description>Counter Stop On Overflow</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter continues incrementing or decrementing after overflow</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter stops incrementing or decrementing after overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CROT</name>
|
|
<description>Counter Reload On Trigger</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TPM1</name>
|
|
<description>Timer/PWM Module</description>
|
|
<groupName>TPM</groupName>
|
|
<prependToName>TPM1_</prependToName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TPM1</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>Clock Mode Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>LPTPM counter is disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>LPTPM counter increments on every LPTPM counter clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter operates in up counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter operates in up-down counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling or DMA request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status and Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture and Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal LPTPM counter continues in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>LPTPM counter continues in debug mode.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global time base enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All channels use the internally generated LPTPM counter as their timebase</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All channels use an externally generated global timebase as their timebase</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSOT</name>
|
|
<description>Counter Start on Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter starts to increment immediately, once it is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSOO</name>
|
|
<description>Counter Stop On Overflow</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTPM counter continues incrementing or decrementing after overflow</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTPM counter stops incrementing or decrementing after overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CROT</name>
|
|
<description>Counter Reload On Trigger</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<prependToName>ADC0_</prependToName>
|
|
<baseAddress>0x4003B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x50</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>SC1%s</name>
|
|
<description>ADC Status and Control Registers 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>AD0 is selected as input.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>AD1 is selected as input.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>AD2 is selected as input.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>AD3 is selected as input.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>AD4 is selected as input.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>AD5 is selected as input.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>AD6 is selected as input.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>AD7 is selected as input.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>AD8 is selected as input.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>AD9 is selected as input.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>AD10 is selected as input.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>AD11 is selected as input.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>AD12 is selected as input.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>AD13 is selected as input.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>AD14 is selected as input.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>AD15 is selected as input.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>AD16 is selected as input.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>AD17 is selected as input.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>AD18 is selected as input.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>AD19 is selected as input.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>AD20 is selected as input.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>AD21 is selected as input.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>AD22 is selected as input.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>AD23 is selected as input.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Temp Sensor (single-ended) is selected as input.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Bandgap (single-ended) is selected as input.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module is disabled.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion is not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion is completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<description>ADC Configuration Register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>(Bus clock)/2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock (ALTCLK)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Asynchronous clock (ADACK)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion mode selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>It is single-ended 8-bit conversion.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>It is single-ended 12-bit conversion .</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>It is single-ended 10-bit conversion .</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Reserved. Do not set the bitfield to this value.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLSMP</name>
|
|
<description>Sample time configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Short sample time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Long sample time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock Divide Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The divide ratio is 1 and the clock rate is input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLPC</name>
|
|
<description>Low-Power Configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal power configuration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<description>ADC Configuration Register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADLSTS</name>
|
|
<description>Long Sample Time Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADHSC</name>
|
|
<description>High-Speed Configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal conversion sequence selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACKEN</name>
|
|
<description>Asynchronous Clock Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXSEL</name>
|
|
<description>ADC Mux Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADxxa channels are selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADxxb channels are selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>R%s</name>
|
|
<description>ADC Data Result Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Data result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>CV%s</name>
|
|
<description>Compare Value Registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Compare Value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and Control Register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare Function Range Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range function disabled. Only CV1 is compared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare Function Greater Than Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare Function Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion Trigger Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and Control Register 3</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware Average Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>4 samples averaged.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8 samples averaged.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16 samples averaged.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32 samples averaged.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware Average Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware average function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware average function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous Conversion Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALF</name>
|
|
<description>Calibration Failed Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Calibration completed normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>ADC Offset Correction Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PG</name>
|
|
<description>ADC Plus-Side Gain Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>Plus-Side Gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPD</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPD</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP4</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP4</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTMR0</name>
|
|
<description>Low Power Timer</description>
|
|
<prependToName>LPTMR0_</prependToName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPTMR0</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Low Power Timer Control Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTMR is disabled and internal logic is reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTMR is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMS</name>
|
|
<description>Timer Mode Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time Counter mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFC</name>
|
|
<description>Timer Free-Running Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNR is reset whenever TCF is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNR is reset on overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPP</name>
|
|
<description>Timer Pin Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Timer Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Pulse counter input 0 is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Pulse counter input 1 is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Pulse counter input 2 is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Pulse counter input 3 is selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Timer Compare Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The value of CNR is not equal to CMR and increments.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The value of CNR is equal to CMR and increments.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>Low Power Timer Prescale Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Prescaler Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prescaler/glitch filter clock 0 selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Prescaler/glitch filter clock 1 selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Prescaler/glitch filter clock 2 selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Prescaler/glitch filter clock 3 selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBYP</name>
|
|
<description>Prescaler Bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler/glitch filter is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler/glitch filter is bypassed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescale Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR</name>
|
|
<description>Low Power Timer Compare Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPARE</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNR</name>
|
|
<description>Low Power Timer Counter Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SIM</name>
|
|
<description>System Integration Module</description>
|
|
<prependToName>SIM_</prependToName>
|
|
<baseAddress>0x40047000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x1004</offset>
|
|
<size>0x104</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SOPT2</name>
|
|
<description>System Options Register 2</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPMSRC</name>
|
|
<description>TPM clock source select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Clock disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGFLLCLK clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>MCGIRCLK clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0SRC</name>
|
|
<description>UART0 clock source select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Clock disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGFLLCLK clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>MCGIRCLK clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT4</name>
|
|
<description>System Options Register 4</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPM1CH0SRC</name>
|
|
<description>TPM1 channel 0 input capture source select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM1_CH0 signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP0 output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM0CLKSEL</name>
|
|
<description>TPM0 External Clock Pin Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM0 external clock driven by TPM_CLKIN0 pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TPM0 external clock driven by TPM_CLKIN1 pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM1CLKSEL</name>
|
|
<description>TPM1 External Clock Pin Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM1 external clock driven by TPM_CLKIN0 pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TPM1 external clock driven by TPM_CLKIN1 pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT5</name>
|
|
<description>System Options Register 5</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART0TXSRC</name>
|
|
<description>UART0 transmit data source select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART0_TX pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART0_TX pin modulated with TPM1 channel 0 output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0RXSRC</name>
|
|
<description>UART0 receive data source select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART0_RX pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP0 output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0ODE</name>
|
|
<description>UART0 Open Drain Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain is disabled on UART0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain is enabled on UART0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT7</name>
|
|
<description>System Options Register 7</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0TRGSEL</name>
|
|
<description>ADC0 trigger select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>External trigger pin input (EXTRG_IN)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>CMP0 output</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>TPM0 overflow</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>TPM1 overflow</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>LPTMR0 trigger</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0PRETRGSEL</name>
|
|
<description>ADC0 pretrigger select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pre-trigger A</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pre-trigger B</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0ALTTRGEN</name>
|
|
<description>ADC0 alternate trigger enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternate trigger selected for ADC0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDID</name>
|
|
<description>System Device Identification Register</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x100600</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINID</name>
|
|
<description>Pincount identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>16-pin</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>24-pin</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>32-pin</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>48-pin</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>64-pin</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>80-pin</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>100-pin</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIEID</name>
|
|
<description>Device die number</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REVID</name>
|
|
<description>Device revision number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRAMSIZE</name>
|
|
<description>System SRAM Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0.5 KB</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1 KB</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2 KB</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>4 KB</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>8 KB</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>16 KB</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>32 KB</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>64 KB</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SERIESID</name>
|
|
<description>Kinetis Series ID</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>KL family</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUBFAMID</name>
|
|
<description>Kinetis Sub-Family ID</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>KLx2 Subfamily (low end)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>KLx4 Subfamily (basic analog)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>KLx5 Subfamily (advanced analog)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>KLx6 Subfamily (advanced analog with I2S)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAMID</name>
|
|
<description>Kinetis family ID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>KL0x Family (low end)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>KL1x Family (basic)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>KL2x Family (USB)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>KL3x Family (Segment LCD)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>KL4x Family (USB and Segment LCD)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC4</name>
|
|
<description>System Clock Gating Control Register 4</description>
|
|
<addressOffset>0x1034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xE0000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>I2C0 Clock Gate Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>I2C1 Clock Gate Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0</name>
|
|
<description>UART0 Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Comparator Clock Gate Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>SPI0 Clock Gate Control</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC5</name>
|
|
<description>System Clock Gating Control Register 5</description>
|
|
<addressOffset>0x1038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x180</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPTMR</name>
|
|
<description>Low Power Timer Access Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Access disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTA</name>
|
|
<description>Port A Clock Gate Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTB</name>
|
|
<description>Port B Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC6</name>
|
|
<description>System Clock Gating Control Register 6</description>
|
|
<addressOffset>0x103C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTF</name>
|
|
<description>Flash Memory Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM0</name>
|
|
<description>TPM0 Clock Gate Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM1</name>
|
|
<description>TPM1 Clock Gate Control</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0</name>
|
|
<description>ADC0 Clock Gate Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV1</name>
|
|
<description>System Clock Divider Register 1</description>
|
|
<addressOffset>0x1044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUTDIV4</name>
|
|
<description>Clock 4 output divider value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV1</name>
|
|
<description>Clock 1 output divider value</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG1</name>
|
|
<description>Flash Configuration Register 1</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLASHDIS</name>
|
|
<description>Flash Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash is enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHDOZE</name>
|
|
<description>Flash Doze</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash remains enabled during Doze mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash is disabled for the duration of Doze mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSIZE</name>
|
|
<description>Program flash size</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>8 KB of program flash memory, 0.25 KB protection region</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>16 KB of program flash memory, 0.5 KB protection region</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>32 KB of program flash memory, 1 KB protection region</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>64 KB of program flash memory, 2 KB protection region</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 KB of program flash memory, 4 KB protection region</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>256 KB of program flash memory, 8 KB protection region</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>32 KB of program flash memory, 1 KB protection region</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG2</name>
|
|
<description>Flash Configuration Register 2</description>
|
|
<addressOffset>0x1050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x7F800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXADDR0</name>
|
|
<description>Max address block</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDMH</name>
|
|
<description>Unique Identification Register Mid-High</description>
|
|
<addressOffset>0x1058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDML</name>
|
|
<description>Unique Identification Register Mid Low</description>
|
|
<addressOffset>0x105C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDL</name>
|
|
<description>Unique Identification Register Low</description>
|
|
<addressOffset>0x1060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COPC</name>
|
|
<description>COP Control Register</description>
|
|
<addressOffset>0x1100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COPW</name>
|
|
<description>COP windowed mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowed mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COPCLKS</name>
|
|
<description>COP Clock Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal 1 kHz clock is source to COP</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock is source to COP</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COPT</name>
|
|
<description>COP Watchdog Timeout</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>COP disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>COP timeout after 25 LPO cycles or 213 bus clock cycles</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>COP timeout after 28 LPO cycles or 216 bus clock cycles</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>COP timeout after 210 LPO cycles or 218 bus clock cycles</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRVCOP</name>
|
|
<description>Service COP Register</description>
|
|
<addressOffset>0x1104</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRVCOP</name>
|
|
<description>Sevice COP Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTA</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTA_</prependToName>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTA</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>PCR%s</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x302</resetValue>
|
|
<resetMask>0xFFFFFFFA</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. The flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. The flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTB</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTB_</prependToName>
|
|
<baseAddress>0x4004A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTB</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
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|
<name>PCR%s</name>
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|
<description>Pin Control Register n</description>
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|
<addressOffset>0</addressOffset>
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|
<size>32</size>
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|
<access>read-write</access>
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|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFA</resetMask>
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|
<fields>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
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|
<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
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|
<bitOffset>4</bitOffset>
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|
<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
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|
<bitOffset>6</bitOffset>
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|
<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
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|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
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<bitOffset>8</bitOffset>
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|
<bitWidth>3</bitWidth>
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<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (analog).</description>
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|
<value>#000</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
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|
<value>#001</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
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|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. The flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. The flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCG</name>
|
|
<description>Multipurpose Clock Generator module</description>
|
|
<prependToName>MCG_</prependToName>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MCG</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>MCG Control 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREFSTEN</name>
|
|
<description>Internal Reference Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal reference clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRCLKEN</name>
|
|
<description>Internal Reference Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGIRCLK inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGIRCLK active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFS</name>
|
|
<description>Internal Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The slow internal reference clock is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDIV</name>
|
|
<description>FLL External Reference Divider</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 .</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>If RANGE 0 = 0 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 .</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Output of FLL is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - External reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Encoding 3 - Reserved.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>MCG Control 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCS</name>
|
|
<description>Internal Reference Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow internal reference clock selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast internal reference clock selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LP</name>
|
|
<description>Low Power Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL is not disabled in bypass modes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL is disabled in bypass modes (lower power)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EREFS0</name>
|
|
<description>External Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HGO0</name>
|
|
<description>High Gain Oscillator Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configure crystal oscillator for low-power operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configure crystal oscillator for high-gain operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RANGE0</name>
|
|
<description>Frequency Range Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Low frequency range selected for the crystal oscillator .</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - High frequency range selected for the crystal oscillator .</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCFTRIM</name>
|
|
<description>Fast Internal Reference Clock Fine Trim</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCRE0</name>
|
|
<description>Loss of Clock Reset Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt request is generated on a loss of OSC0 external reference clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate a reset request on a loss of OSC0 external reference clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>MCG Control 3 Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCTRIM</name>
|
|
<description>Slow Internal Reference Clock Trim Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>MCG Control 4 Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xE0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCFTRIM</name>
|
|
<description>Slow Internal Reference Clock Fine Trim</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FCTRIM</name>
|
|
<description>Fast Internal Reference Clock Trim Setting</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRST_DRS</name>
|
|
<description>DCO Range Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Low range (reset default).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Mid range.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - Mid-high range.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Encoding 3 - High range.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMX32</name>
|
|
<description>DCO Maximum Frequency with 32.768 kHz Reference</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DCO has a default range of 25%.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DCO is fine-tuned for maximum frequency with 32.768 kHz reference.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C6</name>
|
|
<description>MCG Control 6 Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CME</name>
|
|
<description>Clock Monitor Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External clock monitor is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate a reset request on loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>MCG Status Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCST</name>
|
|
<description>Internal Reference Clock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of internal reference clock is the slow clock (32 kHz IRC).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of internal reference clock is the fast clock (4 MHz IRC).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCINIT0</name>
|
|
<description>OSC Initialization</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKST</name>
|
|
<description>Clock Mode Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Output of the FLL is selected (reset default).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - External reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFST</name>
|
|
<description>Internal Reference Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of FLL reference clock is the external reference clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of FLL reference clock is the internal reference clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>MCG Status and Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCS0</name>
|
|
<description>OSC0 Loss of Clock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loss of OSC0 has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of OSC0 has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCRDIV</name>
|
|
<description>Fast Clock Internal Reference Divider</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide Factor is 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide Factor is 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide Factor is 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide Factor is 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide Factor is 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide Factor is 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide Factor is 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide Factor is 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTPRSRV</name>
|
|
<description>FLL Filter Preserve Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL filter and FLL frequency will reset on changes to currect clock mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fll filter and FLL frequency retain their previous values during new clock mode change.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATMF</name>
|
|
<description>Automatic Trim Machine Fail Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic Trim Machine completed normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic Trim Machine failed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATMS</name>
|
|
<description>Automatic Trim Machine Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>32 kHz Internal Reference Clock selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>4 MHz Internal Reference Clock selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATME</name>
|
|
<description>Automatic Trim Machine Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto Trim Machine disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto Trim Machine enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCVH</name>
|
|
<description>MCG Auto Trim Compare Value High Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATCVH</name>
|
|
<description>ATM Compare Value High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCVL</name>
|
|
<description>MCG Auto Trim Compare Value Low Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATCVL</name>
|
|
<description>ATM Compare Value Low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC0</name>
|
|
<description>Oscillator</description>
|
|
<prependToName>OSC0_</prependToName>
|
|
<baseAddress>0x40065000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>OSC Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SC16P</name>
|
|
<description>Oscillator 16 pF Capacitor Load Configure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 16 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC8P</name>
|
|
<description>Oscillator 8 pF Capacitor Load Configure</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 8 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC4P</name>
|
|
<description>Oscillator 4 pF Capacitor Load Configure</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 4 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC2P</name>
|
|
<description>Oscillator 2 pF Capacitor Load Configure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 2 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EREFSTEN</name>
|
|
<description>External Reference Stop Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERCLKEN</name>
|
|
<description>External Reference Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External reference clock is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C0_</prependToName>
|
|
<baseAddress>0x40066000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>ClockRate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>The MULT bits define the multiplier factor mul</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit Acknowledge Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following receiving byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following receiving data byte.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>I2C Status register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range Address Match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed As A Slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range Address Matching Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave Baud Rate Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HDRS</name>
|
|
<description>High Drive Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal drive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address Extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Filter Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>I2C Bus Start Detect Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No start happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>I2C Bus Stop or Start Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop or start detection interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop or start detection interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>I2C Bus Stop Detect Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No stop happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHEN</name>
|
|
<description>Stop Hold Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop holdoff is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range Slave Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C1_</prependToName>
|
|
<baseAddress>0x40067000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>ClockRate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>The MULT bits define the multiplier factor mul</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit Acknowledge Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following receiving byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following receiving data byte.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>I2C Status register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range Address Match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed As A Slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range Address Matching Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave Baud Rate Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HDRS</name>
|
|
<description>High Drive Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal drive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address Extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Filter Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>I2C Bus Start Detect Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No start happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>I2C Bus Stop or Start Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop or start detection interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop or start detection interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>I2C Bus Stop Detect Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No stop happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHEN</name>
|
|
<description>Stop Hold Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop holdoff is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range Slave Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter</description>
|
|
<prependToName>UART0_</prependToName>
|
|
<baseAddress>0x4006A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Register High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RX Input Active Edge Interrupt Enable (for RXEDGIF)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART _S2[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART _S2[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Register Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART is enabled in Wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART is disabled in Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - UART _RX and UART _TX use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART .</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal UART receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver in standby waiting for wakeup condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable for IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from IDLE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when IDLE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable for RDRF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RDRF disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when RDRF flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable for TDRE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in UART _D.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new UART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data buffer empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data buffer full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data buffer full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data buffer empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active ( UART _RXD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>UART _RX Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>UART _TX Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART _TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART _TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R9T8</name>
|
|
<description>Receive Bit 9 / Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T9</name>
|
|
<description>Receive Bit 8 / Transmit Bit 9</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>Read receive data buffer 0 or write transmit data buffer 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>Read receive data buffer 1 or write transmit data buffer 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>Read receive data buffer 2 or write transmit data buffer 2.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>Read receive data buffer 3 or write transmit data buffer 3.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>Read receive data buffer 4 or write transmit data buffer 4.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>Read receive data buffer 5 or write transmit data buffer 5.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>Read receive data buffer 6 or write transmit data buffer 6.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>Read receive data buffer 7 or write transmit data buffer 7.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Over Sampling Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit or 9-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 10-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESYNCDIS</name>
|
|
<description>Resynchronization Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resynchronization during received data word is supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resynchronization during received data word is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOTHEDGE</name>
|
|
<description>Both Edge Sampling</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP0</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<prependToName>CMP0_</prependToName>
|
|
<baseAddress>0x40073000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Level 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Level 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Level 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Level 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>One sample must agree. The comparator output is simply sampled.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Comparator INVERT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGM</name>
|
|
<description>Trigger Mode Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPR</name>
|
|
<description>CMP Filter Period Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT_PER</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>CMP Status and Control Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling-edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Falling-edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rising-edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising-edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACCR</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>V is selected as resistor ladder network supply reference V. in1 in</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>V is selected as resistor ladder network supply reference V. in2 in</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUXCR</name>
|
|
<description>MUX Control Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input Mux Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input Mux Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>Serial Peripheral Interface</description>
|
|
<prependToName>SPI0_</prependToName>
|
|
<baseAddress>0x40076000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>SPI control register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LSB first (shifter direction)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI serial data transfers start with most significant bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI serial data transfers start with least significant bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>Slave select output enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active-high SPI clock (idles low)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active-low SPI clock (idles high)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/slave mode select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI module configured as a slave SPI device</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI module configured as a master SPI device</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTIE</name>
|
|
<description>SPI transmit interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPTEF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPTEF is 1, hardware interrupt requested</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI system enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI system inactive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI system enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>SPI interrupt enable: for SPRF and MODF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPRF and MODF are inhibited-use polling</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when SPRF or MODF is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>SPI control register 2</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPC0</name>
|
|
<description>SPI pin control 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPISWAI</name>
|
|
<description>SPI stop in wait mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI clocks continue to operate in wait mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI clocks stop when the MCU enters wait mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIDIROE</name>
|
|
<description>Bidirectional mode output enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI I/O pin enabled as an output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODFEN</name>
|
|
<description>Master mode-fault function enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMIE</name>
|
|
<description>SPI match interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPMF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPMF is 1, requests a hardware interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BR</name>
|
|
<description>SPI baud rate register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPR</name>
|
|
<description>SPI baud rate divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Baud rate divisor is 2</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Baud rate divisor is 4</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Baud rate divisor is 8</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Baud rate divisor is 16</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Baud rate divisor is 32</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Baud rate divisor is 64</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Baud rate divisor is 128</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Baud rate divisor is 256</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Baud rate divisor is 512</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPPR</name>
|
|
<description>SPI baud rate prescale divisor</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Baud rate prescaler divisor is 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Baud rate prescaler divisor is 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Baud rate prescaler divisor is 3</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Baud rate prescaler divisor is 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Baud rate prescaler divisor is 5</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Baud rate prescaler divisor is 6</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Baud rate prescaler divisor is 7</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Baud rate prescaler divisor is 8</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>SPI status register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Master mode fault flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mode fault error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTEF</name>
|
|
<description>SPI transmit buffer empty flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI transmit buffer not empty</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI transmit buffer empty</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMF</name>
|
|
<description>SPI match flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Value in the receive data buffer does not match the value in the M register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Value in the receive data buffer matches the value in the M register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPRF</name>
|
|
<description>SPI read buffer full flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data available in the receive data buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data available in the receive data buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>SPI data register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Data (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M</name>
|
|
<description>SPI match register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Hardware compare value (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<description>Power Management Controller</description>
|
|
<prependToName>PMC_</prependToName>
|
|
<baseAddress>0x4007D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LVD_LVW</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>LVDSC1</name>
|
|
<description>Low Voltage Detect Status And Control 1 register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDV</name>
|
|
<description>Low-Voltage Detect Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low trip point selected (V LVD = V LVDL )</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>High trip point selected (V LVD = V LVDH )</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDRE</name>
|
|
<description>Low-Voltage Detect Reset Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LVDF does not generate hardware resets</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force an MCU reset when LVDF = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDIE</name>
|
|
<description>Low-Voltage Detect Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVDF = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDACK</name>
|
|
<description>Low-Voltage Detect Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDF</name>
|
|
<description>Low-Voltage Detect Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LVDSC2</name>
|
|
<description>Low Voltage Detect Status And Control 2 register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVWV</name>
|
|
<description>Low-Voltage Warning Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low trip point selected (VLVW = VLVW1)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mid 1 trip point selected (VLVW = VLVW2)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mid 2 trip point selected (VLVW = VLVW3)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High trip point selected (VLVW = VLVW4)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWIE</name>
|
|
<description>Low-Voltage Warning Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVWF = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWACK</name>
|
|
<description>Low-Voltage Warning Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVWF</name>
|
|
<description>Low-Voltage Warning Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage warning event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage warning event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGSC</name>
|
|
<description>Regulator Status And Control register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BGBE</name>
|
|
<description>Bandgap Buffer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bandgap buffer not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bandgap buffer enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGONS</name>
|
|
<description>Regulator In Run Regulation Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Regulator is in stop regulation or in transition to/from it</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Regulator is in run regulation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKISO</name>
|
|
<description>Acknowledge Isolation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripherals and I/O pads are in normal run state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Certain peripherals and I/O pads are in an isolated and latched state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGEN</name>
|
|
<description>Bandgap Enable In VLPx Operation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bandgap voltage reference is disabled in VLPx , and VLLSx modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bandgap voltage reference is enabled in VLPx , and VLLSx modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SMC</name>
|
|
<description>System Mode Controller</description>
|
|
<prependToName>SMC_</prependToName>
|
|
<baseAddress>0x4007E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PMPROT</name>
|
|
<description>Power Mode Protection register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVLLS</name>
|
|
<description>Allow Very-Low-Leakage Stop Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Any VLLSx mode is not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Any VLLSx mode is allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVLP</name>
|
|
<description>Allow Very-Low-Power Modes</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLPR, VLPW and VLPS are not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLPR, VLPW and VLPS are allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMCTRL</name>
|
|
<description>Power Mode Control register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPM</name>
|
|
<description>Stop Mode Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Normal Stop (STOP)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Very-Low-Power Stop (VLPS)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Very-Low-Leakage Stop (VLLSx)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Reseved</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPA</name>
|
|
<description>Stop Aborted</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The previous stop mode entry was successsful.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The previous stop mode entry was aborted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNM</name>
|
|
<description>Run Mode Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal Run mode (RUN)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Very-Low-Power Run mode (VLPR)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STOPCTRL</name>
|
|
<description>Stop Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VLLSM</name>
|
|
<description>VLLS Mode Control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>VLLS0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>VLLS1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>VLLS3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORPO</name>
|
|
<description>POR Power Option</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>POR detect circuit is enabled in VLLS0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>POR detect circuit is disabled in VLLS0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSTOPO</name>
|
|
<description>Partial Stop Option</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>STOP - Normal Stop mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMSTAT</name>
|
|
<description>Power Mode Status register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMSTAT</name>
|
|
<description>When debug is enabled, the PMSTAT will not update to STOP or VLPS When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCM</name>
|
|
<description>Reset Control Module</description>
|
|
<prependToName>RCM_</prependToName>
|
|
<baseAddress>0x4007F000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SRS0</name>
|
|
<description>System Reset Status Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x82</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Low Leakage Wakeup Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD</name>
|
|
<description>Low-Voltage Detect Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by LVD trip or POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by LVD trip or POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Loss-of-Clock Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of external clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOG</name>
|
|
<description>Watchdog</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by watchdog timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by watchdog timeout</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>External Reset Pin</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by external reset pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by external reset pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power-On Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRS1</name>
|
|
<description>System Reset Status Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>Core Lockup</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by core LOCKUP event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by core LOCKUP event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>Software</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDM_AP</name>
|
|
<description>MDM-AP System Reset Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKERR</name>
|
|
<description>Stop Mode Acknowledge Error Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPFC</name>
|
|
<description>Reset Pin Filter Control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTFLTSRW</name>
|
|
<description>Reset Pin Filter Select in Run and Wait Modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>All filtering disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bus clock filter enabled for normal operation</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>LPO clock filter enabled for normal operation</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTFLTSS</name>
|
|
<description>Reset Pin Filter Select in Stop Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All filtering disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPO clock filter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPFW</name>
|
|
<description>Reset Pin Filter Width register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTFLTSEL</name>
|
|
<description>Reset Pin Filter Bus Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Bus clock filter count is 1</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>Bus clock filter count is 2</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>Bus clock filter count is 3</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>Bus clock filter count is 4</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>Bus clock filter count is 5</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>Bus clock filter count is 6</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>Bus clock filter count is 7</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>Bus clock filter count is 8</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>Bus clock filter count is 9</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>Bus clock filter count is 10</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>Bus clock filter count is 11</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>Bus clock filter count is 12</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>Bus clock filter count is 13</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>Bus clock filter count is 14</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>Bus clock filter count is 15</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>Bus clock filter count is 16</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Bus clock filter count is 17</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Bus clock filter count is 18</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Bus clock filter count is 19</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>Bus clock filter count is 20</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>Bus clock filter count is 21</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>Bus clock filter count is 22</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Bus clock filter count is 23</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Bus clock filter count is 24</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>Bus clock filter count is 25</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>Bus clock filter count is 26</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Bus clock filter count is 27</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Bus clock filter count is 28</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>Bus clock filter count is 29</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>Bus clock filter count is 30</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>Bus clock filter count is 31</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Bus clock filter count is 32</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOA_</prependToName>
|
|
<baseAddress>0x400FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTA</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOB_</prependToName>
|
|
<baseAddress>0x400FF040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTB</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MTB</name>
|
|
<description>Micro Trace Buffer</description>
|
|
<prependToName>MTB_</prependToName>
|
|
<baseAddress>0xF0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>POSITION</name>
|
|
<description>MTB Position Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRAP</name>
|
|
<description>This bit is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER[MASK] bit in the MASTER Trace Control Register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POINTER</name>
|
|
<description>Trace Packet Address Pointer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASTER</name>
|
|
<description>MTB Master Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTARTEN</name>
|
|
<description>Trace start input enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTOPEN</name>
|
|
<description>Trace stop input enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFRWPRIV</name>
|
|
<description>Special Function Register Write Privilege bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMPRIV</name>
|
|
<description>RAM privilege bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALTREQ</name>
|
|
<description>Halt request bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Main trace enable bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOW</name>
|
|
<description>MTB Flow Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x4</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOSTOP</name>
|
|
<description>If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[EN] bit is automatically set to 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOHALT</name>
|
|
<description>If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[HALTREQ] bit is automatically set to 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WATERMARK</name>
|
|
<description>WATERMARK value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE</name>
|
|
<description>MTB Base Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASEADDR</name>
|
|
<description>This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODECTRL</name>
|
|
<description>Integration Mode Control Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODECTRL</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAGSET</name>
|
|
<description>Claim TAG Set Register</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAGSET</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAGCLEAR</name>
|
|
<description>Claim TAG Clear Register</description>
|
|
<addressOffset>0xFA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAGCLEAR</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKACCESS</name>
|
|
<description>Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKACCESS</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKSTAT</name>
|
|
<description>Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKSTAT</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTHSTAT</name>
|
|
<description>Authentication Status Register</description>
|
|
<addressOffset>0xFB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIT0</name>
|
|
<description>Connected to DBGEN.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT1</name>
|
|
<description>Hardwired to 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT2</name>
|
|
<description>Connected to NIDEN or DBGEN signal.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT3</name>
|
|
<description>Hardwired to 1.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEARCH</name>
|
|
<description>Device Architecture Register</description>
|
|
<addressOffset>0xFBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x47700A31</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEARCH</name>
|
|
<description>Hardwired to 0x4770_0A31.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICECFG</name>
|
|
<description>Device Configuration Register</description>
|
|
<addressOffset>0xFC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICECFG</name>
|
|
<description>Hardwired to 0x0000_0000.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICETYPID</name>
|
|
<description>Device Type Identifier Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x31</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICETYPID</name>
|
|
<description>Hardwired to 0x0000_0031.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MTBDWT</name>
|
|
<description>MTB data watchpoint and trace</description>
|
|
<prependToName>MTBDWT_</prependToName>
|
|
<baseAddress>0xF0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>MTB DWT Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2F000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DWTCFGCTRL</name>
|
|
<description>DWT configuration controls</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUMCMP</name>
|
|
<description>Number of comparators</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>COMP%s</name>
|
|
<description>MTB_DWT Comparator Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Reference value for comparison</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>MTB_DWT Comparator Mask Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>MASK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCT0</name>
|
|
<description>MTB_DWT Comparator Function Register 0</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Instruction fetch.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Data operand read.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Data operand write.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Data operand (read + write).</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>Data Value Match</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Perform address comparison.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Perform data value comparison.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Data Value Size</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Byte.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Halfword.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Word.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Data Value Address 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>Comparator match</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCT1</name>
|
|
<description>MTB_DWT Comparator Function Register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Instruction fetch.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Data operand read.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Data operand write.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Data operand (read + write).</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>Comparator match</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBCTRL</name>
|
|
<description>MTB_DWT Trace Buffer Control Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACOMP0</name>
|
|
<description>Action based on Comparator 0 match</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACOMP1</name>
|
|
<description>Action based on Comparator 1 match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUMCOMP</name>
|
|
<description>Number of Comparators</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICECFG</name>
|
|
<description>Device Configuration Register</description>
|
|
<addressOffset>0xFC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICECFG</name>
|
|
<description>Hardwired to 0x0000_0000.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICETYPID</name>
|
|
<description>Device Type Identifier Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICETYPID</name>
|
|
<description>Hardwired to 0x0000_0004.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ROM</name>
|
|
<description>System ROM</description>
|
|
<prependToName>ROM_</prependToName>
|
|
<baseAddress>0xF0002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2</dimIndex>
|
|
<name>ENTRY%s</name>
|
|
<description>Entry</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENTRY</name>
|
|
<description>ENTRY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TABLEMARK</name>
|
|
<description>End of Table Marker Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MARK</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSACCESS</name>
|
|
<description>System Access Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYSACCESS</name>
|
|
<description>Hardwired to 0x0000_0001</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCM</name>
|
|
<description>Core Platform Miscellaneous Control Module</description>
|
|
<prependToName>MCM_</prependToName>
|
|
<baseAddress>0xF0003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x3C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PLASC</name>
|
|
<description>Crossbar Switch (AXBS) Slave Configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus slave connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus slave connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLAMC</name>
|
|
<description>Crossbar Switch (AXBS) Master Configuration</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMC</name>
|
|
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus master connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus master connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLACR</name>
|
|
<description>Platform Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Arbitration select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fixed-priority arbitration for the crossbar masters</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round-robin arbitration for the crossbar masters</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFCC</name>
|
|
<description>Clear Flash Controller Cache</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DFCDA</name>
|
|
<description>Disable Flash Controller Data Caching</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller data caching</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller data caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCIC</name>
|
|
<description>Disable Flash Controller Instruction Caching</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller instruction caching.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller instruction caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCC</name>
|
|
<description>Disable Flash Controller Cache</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller cache.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller cache.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EFDS</name>
|
|
<description>Enable Flash Data Speculation</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable flash data speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable flash data speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCS</name>
|
|
<description>Disable Flash Controller Speculation</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESFC</name>
|
|
<description>Enable Stalling Flash Controller</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable stalling flash controller when flash is busy.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable stalling flash controller when flash is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPO</name>
|
|
<description>Compute Operation Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPOREQ</name>
|
|
<description>Compute Operation request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Request is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request Compute Operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOACK</name>
|
|
<description>Compute Operation acknowledge</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compute operation entry has not completed or compute operation exit has completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compute operation entry has completed or compute operation exit has not completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOWOI</name>
|
|
<description>Compute Operation wakeup on interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FGPIOA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>FGPIO</groupName>
|
|
<prependToName>FGPIOA_</prependToName>
|
|
<baseAddress>0xF80FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FGPIOB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>FGPIO</groupName>
|
|
<prependToName>FGPIOB_</prependToName>
|
|
<baseAddress>0xF80FF040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|