87314 lines
3.4 MiB
Executable File
87314 lines
3.4 MiB
Executable File
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>Freescale Semiconductor, Inc.</vendor>
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<vendorID>Freescale</vendorID>
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<series>Kinetis_K</series>
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<name>MK52DZ10</name>
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<version>1.6</version>
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<description>MK52DZ10 Freescale Microcontroller</description>
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<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<mpuPresent>false</mpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>FTFL_FlashConfig</name>
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<description>Flash configuration field</description>
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<prependToName>NV_</prependToName>
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<baseAddress>0x400</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0xE</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>BACKKEY3</name>
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<description>Backdoor Comparison Key 3.</description>
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<addressOffset>0</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY2</name>
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<description>Backdoor Comparison Key 2.</description>
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<addressOffset>0x1</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY1</name>
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<description>Backdoor Comparison Key 1.</description>
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<addressOffset>0x2</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY0</name>
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<description>Backdoor Comparison Key 0.</description>
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<addressOffset>0x3</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY7</name>
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<description>Backdoor Comparison Key 7.</description>
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<addressOffset>0x4</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY6</name>
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<description>Backdoor Comparison Key 6.</description>
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<addressOffset>0x5</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY5</name>
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<description>Backdoor Comparison Key 5.</description>
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<addressOffset>0x6</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY4</name>
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<description>Backdoor Comparison Key 4.</description>
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<addressOffset>0x7</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT3</name>
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<description>Non-volatile P-Flash Protection 1 - Low Register</description>
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<addressOffset>0x8</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT2</name>
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<description>Non-volatile P-Flash Protection 1 - High Register</description>
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<addressOffset>0x9</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT1</name>
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<description>Non-volatile P-Flash Protection 0 - Low Register</description>
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<addressOffset>0xA</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT0</name>
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<description>Non-volatile P-Flash Protection 0 - High Register</description>
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<addressOffset>0xB</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FSEC</name>
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<description>Non-volatile Flash Security Register</description>
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<addressOffset>0xC</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>SEC</name>
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<description>Flash Security</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>MCU security status is unsecure</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>11</name>
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<description>MCU security status is secure</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FSLACC</name>
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<description>Freescale Failure Analysis Access Code</description>
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<bitOffset>2</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>10</name>
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<description>Freescale factory access denied</description>
|
|
<value>#10</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Freescale factory access granted</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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|
<name>MEEN</name>
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<description>no description available</description>
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<bitOffset>4</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mass erase is disabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#11</value>
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</enumeratedValue>
|
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</enumeratedValues>
|
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</field>
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|
<field>
|
|
<name>KEYEN</name>
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<description>Backdoor Key Security Enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Backdoor key access enabled</description>
|
|
<value>#10</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
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<description>Backdoor key access disabled</description>
|
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>FOPT</name>
|
|
<description>Non-volatile Flash Option Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
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<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
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|
<field>
|
|
<name>LPBOOT</name>
|
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<description>no description available</description>
|
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<bitOffset>0</bitOffset>
|
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<bitWidth>1</bitWidth>
|
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<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low-power boot</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Normal boot</description>
|
|
<value>#01</value>
|
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</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZPORT_DIS</name>
|
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<description>no description available</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
|
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<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>EzPort operation is disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>EzPort operation is enabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AIPS0</name>
|
|
<description>AIPS-Lite Bridge</description>
|
|
<groupName>AIPS</groupName>
|
|
<prependToName>AIPS0_</prependToName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MPRA</name>
|
|
<description>Master Privilege Register A</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x77700000</resetValue>
|
|
<resetMask>0x77777700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPL5</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW5</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR5</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL4</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW4</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR4</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL3</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW3</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR3</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL2</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW2</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR2</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL1</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW1</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR1</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL0</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW0</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR0</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRA</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRB</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRC</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRD</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRE</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRF</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRG</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRH</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRI</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRJ</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRK</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRL</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRM</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRN</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRO</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRP</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AIPS1</name>
|
|
<description>AIPS-Lite Bridge</description>
|
|
<groupName>AIPS</groupName>
|
|
<prependToName>AIPS1_</prependToName>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MPRA</name>
|
|
<description>Master Privilege Register A</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x77700000</resetValue>
|
|
<resetMask>0x77777700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPL5</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW5</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR5</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL4</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW4</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR4</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL3</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW3</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR3</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL2</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW2</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR2</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL1</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW1</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR1</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL0</name>
|
|
<description>Master privilege level</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW0</name>
|
|
<description>Master trusted for writes</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR0</name>
|
|
<description>Master trusted for read</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRA</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRB</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRC</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRD</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRE</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRF</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRG</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRH</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRI</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRJ</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRK</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRL</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRM</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRN</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRO</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRP</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AXBS</name>
|
|
<description>Crossbar switch</description>
|
|
<prependToName>AXBS_</prependToName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xD04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x100</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>PRS%s</name>
|
|
<description>Priority Registers Slave</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x76543210</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>Master 0 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>Master 1 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M2</name>
|
|
<description>Master 2 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M3</name>
|
|
<description>Master 3 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4</name>
|
|
<description>Master 4 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5</name>
|
|
<description>Master 5 priority. Sets the arbitration priority for this port on the associated slave port.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>This master has level 1, or highest, priority when accessing the slave port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>This master has level 2 priority when accessing the slave port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>This master has level 3 priority when accessing the slave port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>This master has level 4 priority when accessing the slave port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>This master has level 5 priority when accessing the slave port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>This master has level 6 priority when accessing the slave port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>This master has level 7 priority when accessing the slave port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>This master has level 8, or lowest, priority when accessing the slave port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x100</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>CRS%s</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARK</name>
|
|
<description>Park</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Park on master port M0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Park on master port M1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Park on master port M2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Park on master port M3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Park on master port M4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Park on master port M5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCTL</name>
|
|
<description>Parking control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Arbitration mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Round-robin, or rotating, priority</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HLP</name>
|
|
<description>Halt low priority</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The low power mode request has the highest priority for arbitration on this slave port</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The low power mode request has the lowest initial priority for arbitration on this slave port</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RO</name>
|
|
<description>Read only</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave port's registers are writeable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x100</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>MGPCR%s</name>
|
|
<description>Master General Purpose Control Register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AULB</name>
|
|
<description>Arbitrates on undefined length bursts</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No arbitration is allowed during an undefined length burst</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Arbitration is allowed at any time during an undefined length burst</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Arbitration is allowed after four beats of an undefined length burst</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Arbitration is allowed after eight beats of an undefined length burst</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Arbitration is allowed after 16 beats of an undefined length burst</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>Enhanced direct memory access controller</description>
|
|
<prependToName>DMA_</prependToName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA8</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA9</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA10</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA11</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA12</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA13</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA14</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA15</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_Error</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDBG</name>
|
|
<description>Enable Debug</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When in debug mode, the DMA continues to operate.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERCA</name>
|
|
<description>Enable Round Robin Channel Arbitration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fixed priority arbitration is used for channel selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round robin arbitration is used for channel selection.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOE</name>
|
|
<description>Halt On Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt DMA Operations</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLM</name>
|
|
<description>Continuous Link Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A minor loop channel link made to itself goes through channel arbitration before being activated again.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMLM</name>
|
|
<description>Enable Minor Loop Mapping</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Error Cancel Transfer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX</name>
|
|
<description>Cancel Transfer</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ES</name>
|
|
<description>Error Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBE</name>
|
|
<description>Destination Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a bus error on a destination write</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Source Bus Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a bus error on a source read</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SGE</name>
|
|
<description>Scatter/Gather Configuration Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No scatter/gather configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCE</name>
|
|
<description>NBYTES/CITER Configuration Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No NBYTES/CITER configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOE</name>
|
|
<description>Destination Offset Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination offset configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAE</name>
|
|
<description>Destination Address Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination address configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Source Offset Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source offset configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAE</name>
|
|
<description>Source Address Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source address configuration error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRCHN</name>
|
|
<description>Error Channel Number or Cancelled Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPE</name>
|
|
<description>Channel Priority Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel priority error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Transfer Cancelled</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No cancelled transfers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded entry was a cancelled transfer by the error cancel transfer input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No ERR bits are set</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one ERR bit is set indicating a valid error exists that has not been cleared</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERQ</name>
|
|
<description>Enable Request Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERQ0</name>
|
|
<description>Enable DMA Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ1</name>
|
|
<description>Enable DMA Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ2</name>
|
|
<description>Enable DMA Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ3</name>
|
|
<description>Enable DMA Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ4</name>
|
|
<description>Enable DMA Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ5</name>
|
|
<description>Enable DMA Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ6</name>
|
|
<description>Enable DMA Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ7</name>
|
|
<description>Enable DMA Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ8</name>
|
|
<description>Enable DMA Request 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ9</name>
|
|
<description>Enable DMA Request 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ10</name>
|
|
<description>Enable DMA Request 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ11</name>
|
|
<description>Enable DMA Request 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ12</name>
|
|
<description>Enable DMA Request 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ13</name>
|
|
<description>Enable DMA Request 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ14</name>
|
|
<description>Enable DMA Request 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ15</name>
|
|
<description>Enable DMA Request 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEI</name>
|
|
<description>Enable Error Interrupt Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEI0</name>
|
|
<description>Enable Error Interrupt 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI1</name>
|
|
<description>Enable Error Interrupt 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI2</name>
|
|
<description>Enable Error Interrupt 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI3</name>
|
|
<description>Enable Error Interrupt 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI4</name>
|
|
<description>Enable Error Interrupt 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI5</name>
|
|
<description>Enable Error Interrupt 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI6</name>
|
|
<description>Enable Error Interrupt 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI7</name>
|
|
<description>Enable Error Interrupt 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI8</name>
|
|
<description>Enable Error Interrupt 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI9</name>
|
|
<description>Enable Error Interrupt 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI10</name>
|
|
<description>Enable Error Interrupt 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI11</name>
|
|
<description>Enable Error Interrupt 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI12</name>
|
|
<description>Enable Error Interrupt 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI13</name>
|
|
<description>Enable Error Interrupt 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI14</name>
|
|
<description>Enable Error Interrupt 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI15</name>
|
|
<description>Enable Error Interrupt 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEE</name>
|
|
<description>Clear All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the EEI bit specified in the CEEI field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in EEI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAEE</name>
|
|
<description>Sets All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the EEI bit specified in the SEEI field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sets all bits in EEI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAER</name>
|
|
<description>Clear All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the ERQ bit specified in the CERQ field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in ERQ</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERQ</name>
|
|
<description>Set Enable Request Register</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERQ</name>
|
|
<description>Set enable request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAER</name>
|
|
<description>Set All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the ERQ bit specified in the SERQ field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set all bits in ERQ</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Status Bit Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CADN</name>
|
|
<description>Clears All DONE Bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clears only the TCDn_CSR[DONE] bit specified in the CDNE field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears all bits in TCDn_CSR[DONE]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit Register</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAST</name>
|
|
<description>Set All START Bits (activates all channels)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the TCDn_CSR[START] bit specified in the SSRT field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set all bits in TCDn_CSR[START]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERR</name>
|
|
<description>Clear Error Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERR</name>
|
|
<description>Clear Error Indicator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEI</name>
|
|
<description>Clear All Error Indicators</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the ERR bit specified in the CERR field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in ERR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request Register</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAIR</name>
|
|
<description>Clear All Interrupt Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the INT bit specified in the CINT field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in INT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Interrupt Request Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT0</name>
|
|
<description>Interrupt Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1</name>
|
|
<description>Interrupt Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT2</name>
|
|
<description>Interrupt Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT3</name>
|
|
<description>Interrupt Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT4</name>
|
|
<description>Interrupt Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT5</name>
|
|
<description>Interrupt Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT6</name>
|
|
<description>Interrupt Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT7</name>
|
|
<description>Interrupt Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT8</name>
|
|
<description>Interrupt Request 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT9</name>
|
|
<description>Interrupt Request 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT10</name>
|
|
<description>Interrupt Request 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT11</name>
|
|
<description>Interrupt Request 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT12</name>
|
|
<description>Interrupt Request 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT13</name>
|
|
<description>Interrupt Request 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT14</name>
|
|
<description>Interrupt Request 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT15</name>
|
|
<description>Interrupt Request 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR</name>
|
|
<description>Error Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR0</name>
|
|
<description>Error In Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR1</name>
|
|
<description>Error In Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR2</name>
|
|
<description>Error In Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR3</name>
|
|
<description>Error In Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR4</name>
|
|
<description>Error In Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR5</name>
|
|
<description>Error In Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR6</name>
|
|
<description>Error In Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR7</name>
|
|
<description>Error In Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR8</name>
|
|
<description>Error In Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR9</name>
|
|
<description>Error In Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR10</name>
|
|
<description>Error In Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR11</name>
|
|
<description>Error In Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR12</name>
|
|
<description>Error In Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR13</name>
|
|
<description>Error In Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR14</name>
|
|
<description>Error In Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR15</name>
|
|
<description>Error In Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in the corresponding channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in the corresponding channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRS</name>
|
|
<description>Hardware Request Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRS0</name>
|
|
<description>Hardware Request Status Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS1</name>
|
|
<description>Hardware Request Status Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS2</name>
|
|
<description>Hardware Request Status Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS3</name>
|
|
<description>Hardware Request Status Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS4</name>
|
|
<description>Hardware Request Status Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS5</name>
|
|
<description>Hardware Request Status Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS6</name>
|
|
<description>Hardware Request Status Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS7</name>
|
|
<description>Hardware Request Status Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS8</name>
|
|
<description>Hardware Request Status Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS9</name>
|
|
<description>Hardware Request Status Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS10</name>
|
|
<description>Hardware Request Status Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS11</name>
|
|
<description>Hardware Request Status Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS12</name>
|
|
<description>Hardware Request Status Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS13</name>
|
|
<description>Hardware Request Status Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS14</name>
|
|
<description>Hardware Request Status Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS15</name>
|
|
<description>Hardware Request Status Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for the corresponding channel is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for the corresponding channel is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12</dimIndex>
|
|
<name>DCHPRI%s</name>
|
|
<description>Channel n Priority Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel n can suspend a lower priority channel</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination Data Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>8-bit</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>16-bit</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>32-bit</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16-byte</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel is not explicitly started</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel is explicitly started via a software initiated service request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The end-of-major loop interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The end-of-major loop interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The half-point interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The half-point interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel's ERQ bit is not affected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No eDMA engine stalls</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>eDMA engine stalls for 4 cycles after each r/w</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>eDMA engine stalls for 8 cycles after each r/w</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>TCD%s_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FB</name>
|
|
<description>FlexBus external bus interface</description>
|
|
<prependToName>FB_</prependToName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x64</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0xC</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>CSAR%s</name>
|
|
<description>Chip select address register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BA</name>
|
|
<description>Base address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0xC</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>CSMR%s</name>
|
|
<description>Chip select mask register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>V</name>
|
|
<description>Valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Chip select invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Chip select valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read and write accesses are allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Only read accesses are allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BAM</name>
|
|
<description>Base address mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding address bit is used in chip-select decode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding address bit is a don't care in chip-select decode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0xC</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>CSCR%s</name>
|
|
<description>Chip select control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3FFC00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTW</name>
|
|
<description>Burst-write enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSTR</name>
|
|
<description>Burst-read enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEM</name>
|
|
<description>Byte-enable mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The FB_BE n signals are asserted for read and write accesses</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Port size</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>32-bit port size. Valid data sampled and driven on FB_D[31:0]</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AA</name>
|
|
<description>Auto-acknowledge enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No internal FB_TA is asserted. Cycle is terminated externally</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal transfer acknowledge is asserted as specified by WS</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLS</name>
|
|
<description>Byte-lane shift</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not shifted. Data is left-justfied on FB_AD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifted. Data is right justified on FB_AD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WS</name>
|
|
<description>Wait states</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRAH</name>
|
|
<description>Write address hold or deselect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Hold address and attributes two cycles after FB_CSn negates on writes.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Hold address and attributes three cycles after FB_CSn negates on writes.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDAH</name>
|
|
<description>Read address hold or deselect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>If AA is cleared, 1 cycle. If AA is set, 0 cycles.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>If AA is cleared, 2 cycles. If AA is set, 1 cycle.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>If AA is cleared, 3 cycles. If AA is set, 2 cycles.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>If AA is cleared, 4 cycles. If AA is set, 3 cycles.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASET</name>
|
|
<description>Address setup</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Assert FB_CSn on second rising clock edge after address is asserted.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Assert FB_CSn on third rising clock edge after address is asserted.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FB_TS /FB_ALE asserts for one bus clock cycle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSEN</name>
|
|
<description>Secondary wait state enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWS</name>
|
|
<description>Secondary wait states</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSPMCR</name>
|
|
<description>Chip select port multiplexing control register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GROUP5</name>
|
|
<description>FlexBus signal group 5 multiplex control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>FB_TA</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>FB_CS3. You must also set CSCRn[AA].</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>FB_BE_7_0. You must also set CSCRn[AA].</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GROUP4</name>
|
|
<description>FlexBus signal group 4 multiplex control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>FB_TBST</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>FB_CS2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>FB_BE_15_8</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GROUP3</name>
|
|
<description>FlexBus signal group 3 multiplex control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>FB_CS5</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>FB_TSIZ1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>FB_BE_23_16</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GROUP2</name>
|
|
<description>FlexBus signal group 2 multiplex control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>FB_CS4</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>FB_TSIZ0</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>FB_BE_31_24</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GROUP1</name>
|
|
<description>FlexBus signal group 1 multiplex control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>FB_ALE</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>FB_CS1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>FB_TS</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MPU</name>
|
|
<description>Memory protection unit</description>
|
|
<prependToName>MPU_</prependToName>
|
|
<baseAddress>0x4000D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x830</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CESR</name>
|
|
<description>Control/Error Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x815101</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>Valid (global enable/disable for the MPU)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU is disabled. All accesses from all bus masters are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRGD</name>
|
|
<description>Number of region descriptors</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>8 region descriptors</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>12 region descriptors</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>16 region descriptors</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSP</name>
|
|
<description>Number of slave ports</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HRL</name>
|
|
<description>Hardware revision level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SPERR</name>
|
|
<description>Slave port n error</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error has occurred for slave port n.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occurred for slave port n.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>EAR%s</name>
|
|
<description>Error Address Register, Slave Port n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EADDR</name>
|
|
<description>Error address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4</dimIndex>
|
|
<name>EDR%s</name>
|
|
<description>Error Detail Register, Slave Port n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERW</name>
|
|
<description>Error read/write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EATTR</name>
|
|
<description>Error attributes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>User mode, instruction access</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>User mode, data access</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Supervisor mode, instruction access</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Supervisor mode, data access</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMN</name>
|
|
<description>Error master number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EACD</name>
|
|
<description>Error access control detail</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11</dimIndex>
|
|
<name>RGD%s_WORD0</name>
|
|
<description>Region Descriptor n, Word 0</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTADDR</name>
|
|
<description>Start address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11</dimIndex>
|
|
<name>RGD%s_WORD1</name>
|
|
<description>Region Descriptor n, Word 1</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENDADDR</name>
|
|
<description>End address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11</dimIndex>
|
|
<name>RGD%s_WORD2</name>
|
|
<description>Region Descriptor n, Word 2</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x61F7DF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0UM</name>
|
|
<description>Bus master 0 user mode access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M0SM</name>
|
|
<description>Bus master 0 supervisor mode access control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1UM</name>
|
|
<description>Bus master 1 user mode access control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1SM</name>
|
|
<description>Bus master 1 supervisor mode access control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2UM</name>
|
|
<description>Bus master 2 user mode access control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2SM</name>
|
|
<description>Bus master 2 supervisor mode access control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3UM</name>
|
|
<description>Bus master 3 user mode access control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allows the given access type to occur</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M3SM</name>
|
|
<description>Bus master 3 supervisor mode access control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>r/w/x; read, write and execute allowed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>r/x; read and execute allowed, but no write</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>r/w; read and write allowed, but no execute</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Same as user mode defined in M3UM</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4WE</name>
|
|
<description>Bus master 4 write enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 4 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 4 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4RE</name>
|
|
<description>Bus master 4 read enable.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 4 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 4 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5WE</name>
|
|
<description>Bus master 5 write enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 5 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 5 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5RE</name>
|
|
<description>Bus master 5 read enable.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 5 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 5 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6WE</name>
|
|
<description>Bus master 6 write enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 6 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 6 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6RE</name>
|
|
<description>Bus master 6 read enable.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 6 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 6 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7WE</name>
|
|
<description>Bus master 7 write enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 7 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 7 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7RE</name>
|
|
<description>Bus master 7 read enable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 7 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 7 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11</dimIndex>
|
|
<name>RGD%s_WORD3</name>
|
|
<description>Region Descriptor n, Word 3</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>Valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Region descriptor is invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Region descriptor is valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11</dimIndex>
|
|
<name>RGDAAC%s</name>
|
|
<description>Region Descriptor Alternate Access Control n</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x61F7DF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0UM</name>
|
|
<description>Bus master 0 user mode access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M0SM</name>
|
|
<description>Bus master 0 supervisor mode access control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1UM</name>
|
|
<description>Bus master 1 user mode access control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1SM</name>
|
|
<description>Bus master 1 supervisor mode access control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2UM</name>
|
|
<description>Bus master 2 user mode access control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M2SM</name>
|
|
<description>Bus master 2 supervisor mode access control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M3UM</name>
|
|
<description>Bus master 3 user mode access control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allows the given access type to occur</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M3SM</name>
|
|
<description>Bus master 3 supervisor mode access control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>r/w/x; read, write and execute allowed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>r/x; read and execute allowed, but no write</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>r/w; read and write allowed, but no execute</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Same as user mode defined in M3UM</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4WE</name>
|
|
<description>Bus master 4 write enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 4 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 4 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4RE</name>
|
|
<description>Bus master 4 read enable.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 4 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 4 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5WE</name>
|
|
<description>Bus master 5 write enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 5 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 5 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5RE</name>
|
|
<description>Bus master 5 read enable.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 5 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 5 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6WE</name>
|
|
<description>Bus master 6 write enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 6 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 6 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6RE</name>
|
|
<description>Bus master 6 read enable.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 6 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 6 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7WE</name>
|
|
<description>Bus master 7 write enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 7 writes terminate with an access error and the write is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 7 writes allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7RE</name>
|
|
<description>Bus master 7 read enable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus master 7 reads terminate with an access error and the read is not performed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus master 7 reads allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FMC</name>
|
|
<description>Flash Memory Controller</description>
|
|
<prependToName>FMC_</prependToName>
|
|
<baseAddress>0x4001F000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PFAPR</name>
|
|
<description>Flash Access Protection Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF8003F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0AP</name>
|
|
<description>Master 0 Access Protection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M1AP</name>
|
|
<description>Master 1 Access Protection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M2AP</name>
|
|
<description>Master 2 Access Protection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M3AP</name>
|
|
<description>Master 3 Access Protection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4AP</name>
|
|
<description>Master 4 Access Protection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5AP</name>
|
|
<description>Master 5 Access Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6AP</name>
|
|
<description>Master 6 Access Protection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7AP</name>
|
|
<description>Master 7 Access Protection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No access may be performed by this master.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Only read accesses may be performed by this master.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Only write accesses may be performed by this master.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both read and write accesses may be performed by this master.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M0PFD</name>
|
|
<description>Master 0 Prefetch Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M1PFD</name>
|
|
<description>Master 1 Prefetch Disable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M2PFD</name>
|
|
<description>Master 2 Prefetch Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M3PFD</name>
|
|
<description>Master 3 Prefetch Disable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4PFD</name>
|
|
<description>Master 4 Prefetch Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M5PFD</name>
|
|
<description>Master 5 Prefetch Disable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M6PFD</name>
|
|
<description>Master 6 Prefetch Disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7PFD</name>
|
|
<description>Master 7 Prefetch Disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prefetching for this master is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prefetching for this master is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFB0CR</name>
|
|
<description>Flash Bank 0 Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3002001F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B0SEBE</name>
|
|
<description>Bank 0 Single Entry Buffer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single entry buffer is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single entry buffer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0IPE</name>
|
|
<description>Bank 0 Instruction Prefetch Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not prefetch in response to instruction fetches.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable prefetches in response to instruction fetches.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0DPE</name>
|
|
<description>Bank 0 Data Prefetch Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not prefetch in response to data references.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable prefetches in response to data references.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0ICE</name>
|
|
<description>Bank 0 Instruction Cache Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not cache instruction fetches.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cache instruction fetches.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0DCE</name>
|
|
<description>Bank 0 Data Cache Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not cache data references.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cache data references.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>Cache Replacement Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>LRU replacement algorithm per set across all four ways</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Independent LRU with ways [0-1] for ifetches, [2-3] for data</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Independent LRU with ways [0-2] for ifetches, [3] for data</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0MW</name>
|
|
<description>Bank 0 Memory Width</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>32 bits</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>64 bits</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_B_INV</name>
|
|
<description>Invalidate Prefetch Speculation Buffer</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Speculation buffer and single entry buffer are not affected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invalidate (clear) speculation buffer and single entry buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINV_WAY</name>
|
|
<description>Cache Invalidate Way x</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No cache way invalidation for the corresponding cache</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLCK_WAY</name>
|
|
<description>Cache Lock Way x</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cache way is unlocked and may be displaced</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cache way is locked and its contents are not displaced</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B0RWSC</name>
|
|
<description>Bank 0 Read Wait State Control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFB1CR</name>
|
|
<description>Flash Bank 1 Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3002001F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B1SEBE</name>
|
|
<description>Bank 1 Single Entry Buffer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single entry buffer is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single entry buffer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1IPE</name>
|
|
<description>Bank 1 Instruction Prefetch Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not prefetch in response to instruction fetches.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable prefetches in response to instruction fetches.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1DPE</name>
|
|
<description>Bank 1 Data Prefetch Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not prefetch in response to data references.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable prefetches in response to data references.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1ICE</name>
|
|
<description>Bank 1 Instruction Cache Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not cache instruction fetches.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cache instruction fetches.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1DCE</name>
|
|
<description>Bank 1 Data Cache Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not cache data references.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cache data references.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1MW</name>
|
|
<description>Bank 1 Memory Width</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>32 bits</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>64 bits</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>B1RWSC</name>
|
|
<description>Bank 1 Read Wait State Control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TAGVDW0S%s</name>
|
|
<description>Cache Tag Storage</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>valid</name>
|
|
<description>1-bit valid for cache entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>tag</name>
|
|
<description>13-bit tag for cache entry</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TAGVDW1S%s</name>
|
|
<description>Cache Tag Storage</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>valid</name>
|
|
<description>1-bit valid for cache entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>tag</name>
|
|
<description>13-bit tag for cache entry</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TAGVDW2S%s</name>
|
|
<description>Cache Tag Storage</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>valid</name>
|
|
<description>1-bit valid for cache entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>tag</name>
|
|
<description>13-bit tag for cache entry</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TAGVDW3S%s</name>
|
|
<description>Cache Tag Storage</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>valid</name>
|
|
<description>1-bit valid for cache entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>tag</name>
|
|
<description>13-bit tag for cache entry</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW0S%sU</name>
|
|
<description>Cache Data Storage (upper word)</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [63:32] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW0S%sL</name>
|
|
<description>Cache Data Storage (lower word)</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [31:0] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW1S%sU</name>
|
|
<description>Cache Data Storage (upper word)</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [63:32] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW1S%sL</name>
|
|
<description>Cache Data Storage (lower word)</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [31:0] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW2S%sU</name>
|
|
<description>Cache Data Storage (upper word)</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [63:32] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW2S%sL</name>
|
|
<description>Cache Data Storage (lower word)</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [31:0] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW3S%sU</name>
|
|
<description>Cache Data Storage (upper word)</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [63:32] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>DATAW3S%sL</name>
|
|
<description>Cache Data Storage (lower word)</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<description>Bits [31:0] of data entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTFL</name>
|
|
<description>Flash Memory Interface</description>
|
|
<prependToName>FTFL_</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTFL</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>Read_Collision</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FSTAT</name>
|
|
<description>Flash Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MGSTAT0</name>
|
|
<description>Memory Controller Command Completion Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVIOL</name>
|
|
<description>Flash Protection Violation Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No protection violation detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection violation detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCERR</name>
|
|
<description>Flash Access Error Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No access error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLERR</name>
|
|
<description>FTFL Read Collision Error Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No collision error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Collision error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIF</name>
|
|
<description>Command Complete Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTFL command in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTFL command has completed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCNFG</name>
|
|
<description>Flash Configuration Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEERDY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMRDY</name>
|
|
<description>RAM Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Programming acceleration RAM is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Programming acceleration RAM is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFLSH</name>
|
|
<description>FTFL configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTFL configured for program flash only, without support for data flash and/or EEPROM</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Physical program flash 0 is located at relative address 0x0000</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH flag is not set, physical program flash 0 is located at relative address 0x0000</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERSSUSP</name>
|
|
<description>Erase Suspend</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No suspend requested</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Suspend the current Erase Flash Sector command execution.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERSAREQ</name>
|
|
<description>Erase All Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No request or request complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLLIE</name>
|
|
<description>Read Collision Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read collision error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read collision error interrupt enabled. An interrupt request is generated whenever an FTFL read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Command Complete Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command complete interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSEC</name>
|
|
<description>Flash Security Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Flash Security</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>MCU security status is unsecure (The standard shipping condition of the FTFL is unsecure.)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLACC</name>
|
|
<description>Freescale Failure Analysis Access Code</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEEN</name>
|
|
<description>Mass Erase Enable Bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mass erase is disabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYEN</name>
|
|
<description>Backdoor Key Security Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Backdoor key access enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOPT</name>
|
|
<description>Flash Option Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPT</name>
|
|
<description>Nonvolatile Option</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
|
|
<name>FCCOB%s</name>
|
|
<description>Flash Common Command Object Registers</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOBn</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0</dimIndex>
|
|
<name>FPROT%s</name>
|
|
<description>Program Flash Protection Registers</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT</name>
|
|
<description>Program Flash Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Program flash region is protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Program flash region is not protected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAMUX</name>
|
|
<description>DMA channel multiplexor</description>
|
|
<prependToName>DMAMUX_</prependToName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>CHCFG%s</name>
|
|
<description>Channel Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOURCE</name>
|
|
<description>DMA Channel Source (slot)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>DMA Channel Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENBL</name>
|
|
<description>DMA Channel Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>Deserial Serial Peripheral Interface</description>
|
|
<groupName>SPI</groupName>
|
|
<prependToName>SPI0_</prependToName>
|
|
<baseAddress>0x4002C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>DSPI Module Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMPL_PT</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>0 system clocks between SCK edge and SIN sample</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1 system clock between SCK edge and SIN sample</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 system clocks between SCK edge and SIN sample</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_RXF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Rx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Rx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_TXF</name>
|
|
<description>Clear TX FIFO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Tx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Tx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_RXF</name>
|
|
<description>Disable Receive FIFO</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_TXF</name>
|
|
<description>Disable Transmit FIFO</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable DSPI clocks.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allow external logic to disable DSPI clocks.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZE</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Doze mode has no effect on DSPI.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Doze mode disables DSPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSIS</name>
|
|
<description>Peripheral Chip Select x Inactive State</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state of PCSx is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state of PCSx is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROOE</name>
|
|
<description>Receive FIFO Overflow Overwrite Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Incoming data is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Incoming data is shifted into the shift register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSE</name>
|
|
<description>Peripheral Chip Select Strobe Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCS[5]/PCSS is used as an active-low PCS Strobe signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTFE</name>
|
|
<description>Modified Timing Format Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modified SPI transfer format disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modified SPI transfer format enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not halt serial transfers in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Halt serial transfers in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCONF</name>
|
|
<description>DSPI Configuration</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SPI</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT_SCKE</name>
|
|
<description>Continuous SCK Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous SCK disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous SCK enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DSPI is in slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DSPI is in master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>DSPI Transfer Count Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_TCNT</name>
|
|
<description>SPI Transfer Counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CTAR%s</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Master Mode)</description>
|
|
<alternateGroup>SPI0</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>Baud Rate Scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Delay After Transfer Scaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>After SCK Delay Scaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSSCK</name>
|
|
<description>PCS to SCK Delay Scaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PBR</name>
|
|
<description>Baud Rate Prescaler</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Baud Rate Prescaler value is 2.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Baud Rate Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Baud Rate Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Baud Rate Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDT</name>
|
|
<description>Delay after Transfer Prescaler</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PASC</name>
|
|
<description>After SCK Delay Prescaler</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS to SCK Delay Prescaler</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCS to SCK Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCS to SCK Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCS to SCK Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCS to SCK Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LBS First</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is transferred MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is transferred LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBR</name>
|
|
<description>Double Baud Rate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The baud rate is computed normally with a 50/50 duty cycle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTAR_SLAVE</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Slave Mode)</description>
|
|
<alternateGroup>SPI0</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>DSPI Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POPNXTPTR</name>
|
|
<description>Pop Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>RX FIFO Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXNXTPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>TX FIFO Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFDF</name>
|
|
<description>Receive FIFO Drain Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is not empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF</name>
|
|
<description>Receive FIFO Overflow Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Rx FIFO overflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF</name>
|
|
<description>Transmit FIFO Fill Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is not full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF</name>
|
|
<description>Transmit FIFO Underflow Flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Tx FIFO underflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF</name>
|
|
<description>End of Queue Flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQ is not set in the executing command.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQ is set in the executing SPI command.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRXS</name>
|
|
<description>TX and RX Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit and receive operations are disabled (DSPI is in stopped state).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit and receive operations are enabled (DSPI is in running state).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSER</name>
|
|
<description>DSPI DMA/Interrupt Request Select and Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFDF_DIRS</name>
|
|
<description>Receive FIFO Drain DMA or Interrupt Request Select.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDF_RE</name>
|
|
<description>Receive FIFO Drain Request Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFDF interrupt or DMA requests are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFDF interrupt or DMA requests are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF_RE</name>
|
|
<description>Receive FIFO Overflow Request Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFOF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFOF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_DIRS</name>
|
|
<description>Transmit FIFO Fill DMA or Interrupt Request Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF flag generates interrupt requests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF flag generates DMA requests.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_RE</name>
|
|
<description>Transmit FIFO Fill Request Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF interrupts or DMA requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF interrupts or DMA requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF_RE</name>
|
|
<description>Transmit FIFO Underflow Request Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFUF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFUF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF_RE</name>
|
|
<description>DSPI Finished Request Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF_RE</name>
|
|
<description>Transmission Complete Request Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TCF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TCF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR</name>
|
|
<description>DSPI PUSH TX FIFO Register In Master Mode</description>
|
|
<alternateGroup>SPI0</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Negate the PCS[x] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Assert the PCS[x] signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTCNT</name>
|
|
<description>Clear Transfer Counter.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQ</name>
|
|
<description>End Of Queue</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SPI data is not the last data to transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SPI data is the last data to transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTAS</name>
|
|
<description>Clock and Transfer Attributes Select.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>CTAR0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>CTAR1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Peripheral Chip Select Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Return PCSn signals to their inactive state between transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keep PCSn signals asserted between transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR_SLAVE</name>
|
|
<description>DSPI PUSH TX FIFO Register In Slave Mode</description>
|
|
<alternateGroup>SPI0</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POPR</name>
|
|
<description>DSPI POP RX FIFO Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Received Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TXFR%s</name>
|
|
<description>DSPI Transmit FIFO Registers</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCMD_TXDATA</name>
|
|
<description>Transmit Command or Transmit Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>RXFR%s</name>
|
|
<description>DSPI Receive FIFO Registers</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI1</name>
|
|
<description>Deserial Serial Peripheral Interface</description>
|
|
<groupName>SPI</groupName>
|
|
<prependToName>SPI1_</prependToName>
|
|
<baseAddress>0x4002D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>DSPI Module Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMPL_PT</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>0 system clocks between SCK edge and SIN sample</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1 system clock between SCK edge and SIN sample</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 system clocks between SCK edge and SIN sample</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_RXF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Rx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Rx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_TXF</name>
|
|
<description>Clear TX FIFO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Tx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Tx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_RXF</name>
|
|
<description>Disable Receive FIFO</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_TXF</name>
|
|
<description>Disable Transmit FIFO</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable DSPI clocks.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allow external logic to disable DSPI clocks.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZE</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Doze mode has no effect on DSPI.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Doze mode disables DSPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSIS</name>
|
|
<description>Peripheral Chip Select x Inactive State</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state of PCSx is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state of PCSx is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROOE</name>
|
|
<description>Receive FIFO Overflow Overwrite Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Incoming data is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Incoming data is shifted into the shift register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSE</name>
|
|
<description>Peripheral Chip Select Strobe Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCS[5]/PCSS is used as an active-low PCS Strobe signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTFE</name>
|
|
<description>Modified Timing Format Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modified SPI transfer format disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modified SPI transfer format enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not halt serial transfers in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Halt serial transfers in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCONF</name>
|
|
<description>DSPI Configuration</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SPI</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT_SCKE</name>
|
|
<description>Continuous SCK Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous SCK disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous SCK enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DSPI is in slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DSPI is in master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>DSPI Transfer Count Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_TCNT</name>
|
|
<description>SPI Transfer Counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CTAR%s</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Master Mode)</description>
|
|
<alternateGroup>SPI1</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>Baud Rate Scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Delay After Transfer Scaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>After SCK Delay Scaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSSCK</name>
|
|
<description>PCS to SCK Delay Scaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PBR</name>
|
|
<description>Baud Rate Prescaler</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Baud Rate Prescaler value is 2.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Baud Rate Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Baud Rate Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Baud Rate Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDT</name>
|
|
<description>Delay after Transfer Prescaler</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PASC</name>
|
|
<description>After SCK Delay Prescaler</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS to SCK Delay Prescaler</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCS to SCK Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCS to SCK Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCS to SCK Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCS to SCK Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LBS First</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is transferred MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is transferred LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBR</name>
|
|
<description>Double Baud Rate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The baud rate is computed normally with a 50/50 duty cycle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTAR_SLAVE</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Slave Mode)</description>
|
|
<alternateGroup>SPI1</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>DSPI Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POPNXTPTR</name>
|
|
<description>Pop Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>RX FIFO Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXNXTPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>TX FIFO Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFDF</name>
|
|
<description>Receive FIFO Drain Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is not empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF</name>
|
|
<description>Receive FIFO Overflow Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Rx FIFO overflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF</name>
|
|
<description>Transmit FIFO Fill Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is not full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF</name>
|
|
<description>Transmit FIFO Underflow Flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Tx FIFO underflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF</name>
|
|
<description>End of Queue Flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQ is not set in the executing command.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQ is set in the executing SPI command.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRXS</name>
|
|
<description>TX and RX Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit and receive operations are disabled (DSPI is in stopped state).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit and receive operations are enabled (DSPI is in running state).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSER</name>
|
|
<description>DSPI DMA/Interrupt Request Select and Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFDF_DIRS</name>
|
|
<description>Receive FIFO Drain DMA or Interrupt Request Select.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDF_RE</name>
|
|
<description>Receive FIFO Drain Request Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFDF interrupt or DMA requests are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFDF interrupt or DMA requests are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF_RE</name>
|
|
<description>Receive FIFO Overflow Request Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFOF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFOF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_DIRS</name>
|
|
<description>Transmit FIFO Fill DMA or Interrupt Request Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF flag generates interrupt requests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF flag generates DMA requests.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_RE</name>
|
|
<description>Transmit FIFO Fill Request Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF interrupts or DMA requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF interrupts or DMA requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF_RE</name>
|
|
<description>Transmit FIFO Underflow Request Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFUF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFUF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF_RE</name>
|
|
<description>DSPI Finished Request Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF_RE</name>
|
|
<description>Transmission Complete Request Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TCF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TCF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR</name>
|
|
<description>DSPI PUSH TX FIFO Register In Master Mode</description>
|
|
<alternateGroup>SPI1</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Negate the PCS[x] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Assert the PCS[x] signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTCNT</name>
|
|
<description>Clear Transfer Counter.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQ</name>
|
|
<description>End Of Queue</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SPI data is not the last data to transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SPI data is the last data to transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTAS</name>
|
|
<description>Clock and Transfer Attributes Select.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>CTAR0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>CTAR1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Peripheral Chip Select Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Return PCSn signals to their inactive state between transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keep PCSn signals asserted between transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR_SLAVE</name>
|
|
<description>DSPI PUSH TX FIFO Register In Slave Mode</description>
|
|
<alternateGroup>SPI1</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POPR</name>
|
|
<description>DSPI POP RX FIFO Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Received Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TXFR%s</name>
|
|
<description>DSPI Transmit FIFO Registers</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCMD_TXDATA</name>
|
|
<description>Transmit Command or Transmit Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>RXFR%s</name>
|
|
<description>DSPI Receive FIFO Registers</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI2</name>
|
|
<description>Deserial Serial Peripheral Interface</description>
|
|
<groupName>SPI</groupName>
|
|
<prependToName>SPI2_</prependToName>
|
|
<baseAddress>0x400AC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI2</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>DSPI Module Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMPL_PT</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>0 system clocks between SCK edge and SIN sample</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1 system clock between SCK edge and SIN sample</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 system clocks between SCK edge and SIN sample</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_RXF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Rx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Rx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_TXF</name>
|
|
<description>Clear TX FIFO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the Tx FIFO counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the Tx FIFO counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_RXF</name>
|
|
<description>Disable Receive FIFO</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_TXF</name>
|
|
<description>Disable Transmit FIFO</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable DSPI clocks.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allow external logic to disable DSPI clocks.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZE</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Doze mode has no effect on DSPI.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Doze mode disables DSPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSIS</name>
|
|
<description>Peripheral Chip Select x Inactive State</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state of PCSx is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state of PCSx is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROOE</name>
|
|
<description>Receive FIFO Overflow Overwrite Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Incoming data is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Incoming data is shifted into the shift register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSE</name>
|
|
<description>Peripheral Chip Select Strobe Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCS[5]/PCSS is used as an active-low PCS Strobe signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTFE</name>
|
|
<description>Modified Timing Format Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modified SPI transfer format disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modified SPI transfer format enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not halt serial transfers in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Halt serial transfers in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCONF</name>
|
|
<description>DSPI Configuration</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SPI</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT_SCKE</name>
|
|
<description>Continuous SCK Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous SCK disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous SCK enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DSPI is in slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DSPI is in master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>DSPI Transfer Count Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_TCNT</name>
|
|
<description>SPI Transfer Counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CTAR%s</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Master Mode)</description>
|
|
<alternateGroup>SPI2</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>Baud Rate Scaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Delay After Transfer Scaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>After SCK Delay Scaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSSCK</name>
|
|
<description>PCS to SCK Delay Scaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PBR</name>
|
|
<description>Baud Rate Prescaler</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Baud Rate Prescaler value is 2.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Baud Rate Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Baud Rate Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Baud Rate Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDT</name>
|
|
<description>Delay after Transfer Prescaler</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PASC</name>
|
|
<description>After SCK Delay Prescaler</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Delay after Transfer Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Delay after Transfer Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Delay after Transfer Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Delay after Transfer Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS to SCK Delay Prescaler</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCS to SCK Prescaler value is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCS to SCK Prescaler value is 3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCS to SCK Prescaler value is 5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCS to SCK Prescaler value is 7.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LBS First</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is transferred MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is transferred LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBR</name>
|
|
<description>Double Baud Rate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The baud rate is computed normally with a 50/50 duty cycle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTAR_SLAVE</name>
|
|
<description>DSPI Clock and Transfer Attributes Register (In Slave Mode)</description>
|
|
<alternateGroup>SPI2</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x78000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>DSPI Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POPNXTPTR</name>
|
|
<description>Pop Next Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCTR</name>
|
|
<description>RX FIFO Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXNXTPTR</name>
|
|
<description>Transmit Next Pointer</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCTR</name>
|
|
<description>TX FIFO Counter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFDF</name>
|
|
<description>Receive FIFO Drain Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rx FIFO is empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO is not empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF</name>
|
|
<description>Receive FIFO Overflow Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Rx FIFO overflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rx FIFO overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF</name>
|
|
<description>Transmit FIFO Fill Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tx FIFO is full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO is not full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF</name>
|
|
<description>Transmit FIFO Underflow Flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Tx FIFO underflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tx FIFO underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF</name>
|
|
<description>End of Queue Flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQ is not set in the executing command.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQ is set in the executing SPI command.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRXS</name>
|
|
<description>TX and RX Status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit and receive operations are disabled (DSPI is in stopped state).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit and receive operations are enabled (DSPI is in running state).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSER</name>
|
|
<description>DSPI DMA/Interrupt Request Select and Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFDF_DIRS</name>
|
|
<description>Receive FIFO Drain DMA or Interrupt Request Select.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDF_RE</name>
|
|
<description>Receive FIFO Drain Request Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFDF interrupt or DMA requests are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFDF interrupt or DMA requests are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF_RE</name>
|
|
<description>Receive FIFO Overflow Request Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFOF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFOF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_DIRS</name>
|
|
<description>Transmit FIFO Fill DMA or Interrupt Request Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF flag generates interrupt requests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF flag generates DMA requests.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFF_RE</name>
|
|
<description>Transmit FIFO Fill Request Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFFF interrupts or DMA requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFFF interrupts or DMA requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF_RE</name>
|
|
<description>Transmit FIFO Underflow Request Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TFUF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TFUF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQF_RE</name>
|
|
<description>DSPI Finished Request Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOQF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOQF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF_RE</name>
|
|
<description>Transmission Complete Request Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TCF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TCF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR</name>
|
|
<description>DSPI PUSH TX FIFO Register In Master Mode</description>
|
|
<alternateGroup>SPI2</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Negate the PCS[x] signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Assert the PCS[x] signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTCNT</name>
|
|
<description>Clear Transfer Counter.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the TCR[SPI_TCNT] field.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOQ</name>
|
|
<description>End Of Queue</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SPI data is not the last data to transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SPI data is the last data to transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTAS</name>
|
|
<description>Clock and Transfer Attributes Select.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>CTAR0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>CTAR1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Peripheral Chip Select Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Return PCSn signals to their inactive state between transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keep PCSn signals asserted between transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUSHR_SLAVE</name>
|
|
<description>DSPI PUSH TX FIFO Register In Slave Mode</description>
|
|
<alternateGroup>SPI2</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POPR</name>
|
|
<description>DSPI POP RX FIFO Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Received Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TXFR%s</name>
|
|
<description>DSPI Transmit FIFO Registers</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCMD_TXDATA</name>
|
|
<description>Transmit Command or Transmit Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>RXFR%s</name>
|
|
<description>DSPI Receive FIFO Registers</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2S0</name>
|
|
<description>Synchronous Serial Interface</description>
|
|
<prependToName>I2S0_</prependToName>
|
|
<baseAddress>0x4002F000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2S0</name>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TX0</name>
|
|
<description>I2S Transmit Data Registers 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX0</name>
|
|
<description>I2S transmit data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX1</name>
|
|
<description>I2S Transmit Data Registers 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX1</name>
|
|
<description>I2S transmit data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX0</name>
|
|
<description>I2S Receive Data Registers 0</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX0</name>
|
|
<description>I2S Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX1</name>
|
|
<description>I2S Receive Data Registers 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX1</name>
|
|
<description>I2S Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>I2S Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2SEN</name>
|
|
<description>I2S Enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2S is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmit Enable.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit section disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit section enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receive Enable.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive section disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive section enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NET</name>
|
|
<description>Network Mode.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Network mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Network mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYN</name>
|
|
<description>Synchronous Mode.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous mode selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Synchronous mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2SMODE</name>
|
|
<description>I2S Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>I2S master mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>I2S slave mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Normal mode</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCLKEN</name>
|
|
<description>System Clock (Oversampling Clock) Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Network clock not output on SRCK port.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Network clock output on SRCK port.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCHEN</name>
|
|
<description>Two-Channel Operation Enable.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Two-channel mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two-channel mode enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKIST</name>
|
|
<description>Clock Idle State.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock idle state is `0'.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock idle state is `1'.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRCLKDIS</name>
|
|
<description>Transmit Frame Clock Disable.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may be required when frame-sync and clocks are required from I2S, even when no data is to be received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFRCLKDIS</name>
|
|
<description>Receive Frame Clock Disable.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may be required when Frame-sync and Clocks are required from I2S, even when no data is to be received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCTXFS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CR[TE] not latched with FS occurrence and used directly for transmitter enable/disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CR[TE] latched with FS occurrence and latched-TE used for transmitter enable/disable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>I2S Interrupt Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE0</name>
|
|
<description>Transmit FIFO Empty 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO0 has data for transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO0 is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFE1</name>
|
|
<description>Transmit FIFO Empty 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO1 has data for transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO1 is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFF0</name>
|
|
<description>Receive FIFO Full 0.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Space available in receive FIFO0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO0 is full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFF1</name>
|
|
<description>Receive FIFO Full 1.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Space available in receive FIFO1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO1 is full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RLS</name>
|
|
<description>Receive Last Time Slot.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Current time slot is not last time slot of frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Current time slot is the last receive time slot of frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TLS</name>
|
|
<description>Transmit Last Time Slot.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Current time slot is not last time slot of frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Current time slot is the last transmit time slot of frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFS</name>
|
|
<description>Receive Frame Sync.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No occurrence of receive frame sync.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame sync occurred during reception of next word in RX registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFS</name>
|
|
<description>Transmit Frame Sync.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No occurrence of transmit frame sync.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit frame sync occurred during transmission of last word written to TX registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUE0</name>
|
|
<description>Transmitter Underrun Error 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underrun detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter underrun error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUE1</name>
|
|
<description>Transmitter Underrun Error 1.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underrun detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter underrun error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROE0</name>
|
|
<description>Receiver Overrun Error 0.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver overrun error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROE1</name>
|
|
<description>Receiver Overrun Error 1.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver overrun error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE0</name>
|
|
<description>Transmit Data Register Empty 0.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data available for transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data needs to be written by the core for transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE1</name>
|
|
<description>Transmit Data Register Empty 1.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data available for transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data needs to be written by the core for transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDR0</name>
|
|
<description>Receive Data Ready 0.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No new data for core to read.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>New data for core to read.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDR1</name>
|
|
<description>Receive Data Ready 1.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No new data for core to read.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>New data for core to read.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>Receive Tag Updated.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No change in ATAG register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ATAG register updated with different value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDDU</name>
|
|
<description>Command Data Register Updated.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No change in ACDAT register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACDAT register updated with different value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDAU</name>
|
|
<description>Command Address Register Updated.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No change in ACADD register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACADD register updated with different value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transmit Frame Complete.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>End of frame not reached.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End of frame reached after disabling CR[TE] or disabling CR[TFRCLKDIS], when transmitter is already disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFRC</name>
|
|
<description>Receive Frame Complete.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>End of frame not reached.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End of frame reached after disabling CR[RE] or disabling CR[RFRCLKDIS], when receiver is already disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>I2S Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFE1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFF0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFF1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RLSEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TLSEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFSEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFSEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUE0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUE1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROE0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROE1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDR0EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDR1EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDDUEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDAUEN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2S transmitter interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S transmitter interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAE</name>
|
|
<description>Transmit DMA Enable.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2S transmitter DMA requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S transmitter DMA requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Interrupt Enable.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2S receiver interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S receiver interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAE</name>
|
|
<description>Receive DMA Enable.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2S receiver DMA requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S receiver DMA requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRC_EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFRC_EN</name>
|
|
<description>Enable Bit.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding status bit cannot issue interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding status bit can issue interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>I2S Transmit Configuration Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEFS</name>
|
|
<description>Transmit Early Frame Sync.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit frame sync initiated as the first bit of data is transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit frame sync is initiated one bit before the data is transmitted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFSL</name>
|
|
<description>Transmit Frame Sync Length.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit frame sync is one-word long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit frame sync is one-clock-bit long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFSI</name>
|
|
<description>Transmit Frame Sync Invert.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit frame sync is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit frame sync is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCKP</name>
|
|
<description>Transmit Clock Polarity.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data clocked out on rising edge of bit clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data clocked out on falling edge of bit clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSHFD</name>
|
|
<description>Transmit Shift Direction.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmitted MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data transmitted LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmit clock direction</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit clock is external.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit clock generated internally</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFDIR</name>
|
|
<description>Transmit Frame Direction.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame sync is external.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame sync generated internally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFEN0</name>
|
|
<description>Transmit FIFO Enable 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO 0 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO 0 enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFEN1</name>
|
|
<description>Transmit FIFO Enable 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO 1 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO 1 enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXBIT0</name>
|
|
<description>Transmit Bit 0.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifting with respect to bit 0 of transmit shift register (LSB aligned).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>I2S Receive Configuration Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFS</name>
|
|
<description>Receive Early Frame Sync.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive frame sync initiated as the first bit of data is received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame sync is initiated one bit before the data is received.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFSL</name>
|
|
<description>Receive Frame Sync Length.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive frame sync is one-word long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame sync is one-clock-bit long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFSI</name>
|
|
<description>Receive Frame Sync Invert.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive frame sync is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame sync is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCKP</name>
|
|
<description>Receive Clock Polarity.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data latched on falling edge of bit clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data latched on rising edge of bit clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSHFD</name>
|
|
<description>Receive Shift Direction.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data received MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data received LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIR</name>
|
|
<description>Receive Clock Direction.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Clock is external.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive Clock generated internally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDIR</name>
|
|
<description>Receive Frame Direction.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame Sync is external.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame Sync generated internally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFEN0</name>
|
|
<description>Receive FIFO Enable 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO 0 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO 0 enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFEN1</name>
|
|
<description>Receive FIFO Enable 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO 1 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO 1 enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXBIT0</name>
|
|
<description>Receive Bit 0.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifting with respect to bit 0 of receive shift register (LSB aligned).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEXT</name>
|
|
<description>Receive Data Extension.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sign extension turned off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sign extension turned on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCCR</name>
|
|
<description>I2S Transmit Clock Control Registers</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Prescaler Modulus Select.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Frame Rate Divider Control.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WL</name>
|
|
<description>Word Length Control.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>8</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>10</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>12</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>16</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>18</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>20</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>22</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>24</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Reserved. Do not program this value.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSR</name>
|
|
<description>Prescaler Range.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler bypassed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler used to divide clock by 8.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV2</name>
|
|
<description>Divide By 2.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divider bypassed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divider used to divide clock by 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCCR</name>
|
|
<description>I2S Receive Clock Control Registers</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Prescaler Modulus Select.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Frame Rate Divider Control.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WL</name>
|
|
<description>Word Length Control.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Number of Bits/Word: 2; Supported in Implementation: No.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Number of Bits/Word: 4; Supported in Implementation: No.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Number of Bits/Word: 6; Supported in Implementation: No.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Number of Bits/Word: 8; Supported in Implementation: Yes.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Number of Bits/Word: 10; Supported in Implementation: Yes.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Number of Bits/Word: 12; Supported in Implementation: Yes.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Number of Bits/Word: 14; Supported in Implementation: No.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Number of Bits/Word: 16; Supported in Implementation: Yes.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Number of Bits/Word: 18; Supported in Implementation: Yes.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Number of Bits/Word: 20; Supported in Implementation: Yes.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Number of Bits/Word: 22; Supported in Implementation: Yes.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Number of Bits/Word: 24; Supported in Implementation: Yes.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Number of Bits/Word: 26; Supported in Implementation: No.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Number of Bits/Word: 28; Supported in Implementation: No.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Number of Bits/Word: 30; Supported in Implementation: No.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Number of Bits/Word: 32; Supported in Implementation: No.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSR</name>
|
|
<description>Prescaler Range.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler bypassed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler used to divide clock by 8.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV2</name>
|
|
<description>Divide By 2.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divider bypassed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divider used to divide clock by 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCSR</name>
|
|
<description>I2S FIFO Control/Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x810081</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFWM0</name>
|
|
<description>Transmit FIFO Empty WaterMark 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFWM0</name>
|
|
<description>Receive FIFO Full WaterMark 0.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFCNT0</name>
|
|
<description>Transmit FIFO Counter 0.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 data word in transmit FIFO.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1 data word in transmit FIFO.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2 data word in transmit FIFO.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3 data word in transmit FIFO.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4 data word in transmit FIFO.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5 data word in transmit FIFO.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6 data word in transmit FIFO.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7 data word in transmit FIFO.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8 data word in transmit FIFO.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>9 data word in transmit FIFO.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>10 data word in transmit FIFO.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>11 data word in transmit FIFO.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>12 data word in transmit FIFO.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>13 data word in transmit FIFO.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>14 data word in transmit FIFO.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>15 data word in transmit FIFO.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT0</name>
|
|
<description>Receive FIFO Counter 0.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 data word in receive FIFO.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1 data word in receive FIFO.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2 data word in receive FIFO.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3 data word in receive FIFO.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4 data word in receive FIFO.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5 data word in receive FIFO.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6 data word in receive FIFO.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7 data word in receive FIFO.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8 data word in receive FIFO.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>9 data word in receive FIFO.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>10 data word in receive FIFO.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>11 data word in receive FIFO.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>12 data word in receive FIFO.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>13 data word in receive FIFO.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>14 data word in receive FIFO.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>15 data word in receive FIFO.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFWM1</name>
|
|
<description>Transmit FIFO Empty WaterMark 1.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFWM1</name>
|
|
<description>Receive FIFO Full WaterMark 1.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFCNT1</name>
|
|
<description>Transmit FIFO Counter1.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 data word in transmit FIFO.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1 data word in transmit FIFO.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2 data word in transmit FIFO.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3 data word in transmit FIFO.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4 data word in transmit FIFO.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5 data word in transmit FIFO.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6 data word in transmit FIFO.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7 data word in transmit FIFO.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8 data word in transmit FIFO.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>9 data word in transmit FIFO.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>10 data word in transmit FIFO.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>11 data word in transmit FIFO.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>12 data word in transmit FIFO.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>13 data word in transmit FIFO.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>14 data word in transmit FIFO.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>15 data word in transmit FIFO.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT1</name>
|
|
<description>Receive FIFO Counter1.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 data word in receive FIFO.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1 data word in receive FIFO.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2 data word in receive FIFO.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3 data word in receive FIFO.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4 data word in receive FIFO.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5 data word in receive FIFO.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6 data word in receive FIFO.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7 data word in receive FIFO.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8 data word in receive FIFO.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>9 data word in receive FIFO.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>10 data word in receive FIFO.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>11 data word in receive FIFO.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>12 data word in receive FIFO.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>13 data word in receive FIFO.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>14 data word in receive FIFO.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>15 data word in receive FIFO.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACNT</name>
|
|
<description>I2S AC97 Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC97EN</name>
|
|
<description>AC97 Mode Enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AC97 mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2S in AC97 mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FV</name>
|
|
<description>Fixed/Variable Operation.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AC97 Fixed Mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AC97 Variable Mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Tag in FIFO.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Tag info stored in ATAG register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Tag info stored in ATAG register and Rx FIFO 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Read Command.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Next frame will not have a Read Command.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next frame will have a Read Command.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR</name>
|
|
<description>Write Command.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Next frame will not have a Write Command.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next frame will have a Write Command.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDIV</name>
|
|
<description>Frame Rate Divider.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACADD</name>
|
|
<description>I2S AC97 Command Address Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACADD</name>
|
|
<description>AC97 Command Address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACDAT</name>
|
|
<description>I2S AC97 Command Data Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACDAT</name>
|
|
<description>AC97 Command Data.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATAG</name>
|
|
<description>I2S AC97 Tag Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATAG</name>
|
|
<description>AC97 Tag Value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMSK</name>
|
|
<description>I2S Transmit Time Slot Mask Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMSK</name>
|
|
<description>Transmit Mask.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Valid Time Slot.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time Slot masked (no data transmitted in this time slot).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMSK</name>
|
|
<description>I2S Receive Time Slot Mask Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMSK</name>
|
|
<description>Receive Mask.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Valid Time Slot.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time Slot masked (no data received in this time slot).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCST</name>
|
|
<description>I2S AC97 Channel Status Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACCST</name>
|
|
<description>AC97 Channel Status.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data channel disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data channel enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCEN</name>
|
|
<description>I2S AC97 Channel Enable Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACCEN</name>
|
|
<description>AC97 Channel Enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write has no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write enables the corresponding data channel.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCDIS</name>
|
|
<description>I2S AC97 Channel Disable Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACCDIS</name>
|
|
<description>AC97 Channel Disable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write has no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write disables the corresponding data channel.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Cyclic Redundancy Check</description>
|
|
<prependToName>CRC_</prependToName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CRC</name>
|
|
<description>CRC Data Register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LL</name>
|
|
<description>CRC Low Lower Byte</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LU</name>
|
|
<description>CRC Low Upper Byte</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HL</name>
|
|
<description>CRC High Lower Byte</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>CRC High Upper Byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCL</name>
|
|
<description>CRC_CRCL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCL</name>
|
|
<description>CRCL stores the lower 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCLL</name>
|
|
<description>CRC_CRCLL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCLL</name>
|
|
<description>CRCLL stores the first 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCLU</name>
|
|
<description>CRC_CRCLU register.</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCLU</name>
|
|
<description>CRCLL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCH</name>
|
|
<description>CRC_CRCH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCH</name>
|
|
<description>CRCH stores the high 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCHL</name>
|
|
<description>CRC_CRCHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCHL</name>
|
|
<description>CRCHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCHU</name>
|
|
<description>CRC_CRCHU register.</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCHU</name>
|
|
<description>CRCHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLY</name>
|
|
<description>CRC Polynomial Register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1021</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW</name>
|
|
<description>Low polynominal half-word</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIGH</name>
|
|
<description>High polynominal half-word</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYL</name>
|
|
<description>CRC_GPOLYL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYL</name>
|
|
<description>POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLL</name>
|
|
<description>CRC_GPOLYLL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLL</name>
|
|
<description>POLYLL stores the first 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLU</name>
|
|
<description>CRC_GPOLYLU register.</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLU</name>
|
|
<description>POLYLL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYH</name>
|
|
<description>CRC_GPOLYH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYH</name>
|
|
<description>POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHL</name>
|
|
<description>CRC_GPOLYHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHL</name>
|
|
<description>POLYHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHU</name>
|
|
<description>CRC_GPOLYHU register.</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHU</name>
|
|
<description>POLYHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>CRC Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>Write CRC data register as seed</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the CRC data register are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>Complement Read of CRC data register</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of the CRC data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>Type of Transpose for Read</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>Type of Transpose for Writes</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLHU</name>
|
|
<description>CRC_CTRLHU register.</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to CRC data reguster are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of CRC data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBDCD</name>
|
|
<description>USB Device Charger Detection module</description>
|
|
<prependToName>USBDCD_</prependToName>
|
|
<baseAddress>0x40035000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USBDCD</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IACK</name>
|
|
<description>Interrupt Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear the interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the IF bit (interrupt flag).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt is pending.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable interrupts to the system.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable interrupts to the system.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Change Detection Sequence</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not start the sequence. Writes of this value have no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not perform a software reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Perform a software reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK</name>
|
|
<description>Clock Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLOCK_UNIT</name>
|
|
<description>Unit of measurement encoding for Clock Speed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>kHz Speed (between 1 kHz and 1023 kHz)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MHz Speed (between 1 MHz and 1023 MHz)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLOCK_SPEED</name>
|
|
<description>Numerical Value of Clock Speed in Binary</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEQ_RES</name>
|
|
<description>Charger Detection Sequence Results</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No results to report.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Attached to a standard host. Must comply with USB Spec 2.0 by drawing only 2.5mA (max) until connected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a charging host or a dedicated charger (The charger type detection has not completed.) 1: Attached to a charging host (The charger type detection has completed.)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Attached to a dedicated charger.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEQ_STAT</name>
|
|
<description>Charger Detection Sequence Status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The module is either not enabled, or the module is enabled but the data pins have not yet been detected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Data pin contact detection is complete.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Charger detection is complete.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Charger type detection is complete.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No sequence errors.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>Timeout Flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The detection sequence has not been running for over 1 s.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>It has been over 1 s since the data pin contact was detected and debounced.{</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Active Status Indicator</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The sequence is not running.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The sequence is running.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMER0</name>
|
|
<description>TIMER0 Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TUNITCON</name>
|
|
<description>Unit Connection Timer Elapse (in ms)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEQ_INIT</name>
|
|
<description>Sequence Initiation Time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMER1</name>
|
|
<description>no description available</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA0028</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TVDPSRC_ON</name>
|
|
<description>Time Period Comparator Enabled</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDCD_DBNC</name>
|
|
<description>Time Period to Debounce D+ Signal</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMER2</name>
|
|
<description>no description available</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x280001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHECK_DM</name>
|
|
<description>Time Before Check of D- Line</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TVDPSRC_CON</name>
|
|
<description>Time Period Before Enabling D+ Pullup</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PDB0</name>
|
|
<description>Programmable Delay Block</description>
|
|
<prependToName>PDB0_</prependToName>
|
|
<baseAddress>0x40036000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x198</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PDB0</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Mode Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB operation in One-Shot mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB operation in Continuous mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>Multiplication Factor Select for Prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Multiplication factor is 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Multiplication factor is 10</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Multiplication factor is 20</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Multiplication factor is 40</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDBIE</name>
|
|
<description>PDB Interrupt Enable.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDBIF</name>
|
|
<description>PDB Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PDBEN</name>
|
|
<description>PDB Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB disabled. Counter is off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Input Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Trigger-In 0 is selected</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Trigger-In 1 is selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Trigger-In 2 is selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Trigger-In 3 is selected</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Trigger-In 4 is selected</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Trigger-In 5 is selected</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Trigger-In 6 is selected</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Trigger-In 7 is selected</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Trigger-In 8 is selected</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Trigger-In 9 is selected</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Trigger-In 10 is selected</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Trigger-In 11 is selected</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Trigger-In 12 is selected</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Trigger-In 13 is selected</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Trigger-In 14 is selected</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Software trigger is selected</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler Divider Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Counting uses the peripheral clock divided by multiplication factor selected by MULT.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PDBEIE</name>
|
|
<description>PDB Sequence Error Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB sequence error interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB sequence error interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulus Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>PDB Modulus.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>PDB Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDLY</name>
|
|
<description>Interrupt Delay Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDLY</name>
|
|
<description>PDB Interrupt Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sC1</name>
|
|
<description>Channel n Control Register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>PDB Channel Pre-Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOS</name>
|
|
<description>PDB Channel Pre-Trigger Output Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BB</name>
|
|
<description>PDB Channel Pre-Trigger Back-to-Back Operation Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger back-to-back operation disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger back-to-back operation enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sS</name>
|
|
<description>Channel n Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>PDB Channel Sequence Error Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sequence error not detected on PDB channel's corresponding pre-trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CF</name>
|
|
<description>PDB Channel Flags</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sDLY0</name>
|
|
<description>Channel n Delay 0 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>PDB Channel Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sDLY1</name>
|
|
<description>Channel n Delay 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>PDB Channel Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>DACINTC%s</name>
|
|
<description>DAC Interval Trigger n Control Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOE</name>
|
|
<description>DAC Interval Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC interval trigger disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC interval trigger enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>DAC External Trigger Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>DACINT%s</name>
|
|
<description>DAC Interval n Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>DAC Interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POEN</name>
|
|
<description>Pulse-Out n Enable Register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POEN</name>
|
|
<description>PDB Pulse-Out Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB Pulse-Out disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB Pulse-Out enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PODLY</name>
|
|
<description>Pulse-Out n Delay Register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY2</name>
|
|
<description>PDB Pulse-Out Delay 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLY1</name>
|
|
<description>PDB Pulse-Out Delay 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PIT</name>
|
|
<description>Periodic Interrupt Timer</description>
|
|
<prependToName>PIT_</prependToName>
|
|
<baseAddress>0x40037000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x140</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIT0</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIT1</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIT2</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIT3</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>PIT Module Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timers continue to run in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timers are stopped in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock for PIT Timers is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock for PIT Timers is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>LDVAL%s</name>
|
|
<description>Timer Load Value Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSV</name>
|
|
<description>Timer Start Value Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>CVAL%s</name>
|
|
<description>Current Timer Value Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TVL</name>
|
|
<description>Current Timer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TCTRL%s</name>
|
|
<description>Timer Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable Bit.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer n is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer n is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable Bit.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt requests from Timer n are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt will be requested whenever TIF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TFLG%s</name>
|
|
<description>Timer Flag Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Timer Interrupt Flag.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time-out has not yet occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time-out has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM0</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM0_</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x9C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM0</name>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected (This in effect disables the FTM counter.)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in up counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in up-down counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status and Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture and Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize the Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum loading point enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum loading point enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State for Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function for Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels for n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement of Channel (n) for n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable for n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable for n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable for n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels for n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement of Channel (n) for n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable for n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable for n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable for n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels for n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement of Channel (n) for n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable for n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable for n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable for n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels for n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable for n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable for n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable for n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control and Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUMTOF</name>
|
|
<description>TOF Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>BDM Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global time base enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global time base output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN register synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL register synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL register synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM1</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM1_</prependToName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x9C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM1</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected (This in effect disables the FTM counter.)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in up counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in up-down counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status and Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture and Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize the Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum loading point enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum loading point enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State for Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function for Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels for n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement of Channel (n) for n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable for n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable for n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable for n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels for n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement of Channel (n) for n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable for n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable for n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable for n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels for n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement of Channel (n) for n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable for n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable for n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable for n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels for n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable for n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable for n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable for n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control and Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUMTOF</name>
|
|
<description>TOF Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>BDM Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global time base enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global time base output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN register synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL register synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL register synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM2</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM2_</prependToName>
|
|
<baseAddress>0x400B8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x9C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM2</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected (This in effect disables the FTM counter.)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in up counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in up-down counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status and Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture and Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize the Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum loading point enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum loading point enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State for Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function for Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels for n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement of Channel (n) for n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable for n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable for n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable for n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels for n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement of Channel (n) for n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable for n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable for n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable for n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels for n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement of Channel (n) for n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable for n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable for n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable for n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels for n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable for n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures for n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable for n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable for n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable for n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control and Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction in Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUMTOF</name>
|
|
<description>TOF Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>BDM Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global time base enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global time base output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A one at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A zero at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN register synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL register synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL register synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC0_</prependToName>
|
|
<baseAddress>0x4003B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>SC1%s</name>
|
|
<description>ADC status and control registers 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module disabled.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Differential mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single-ended conversions and input channels are selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential conversions and input channels are selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion complete flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<description>ADC configuration register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input clock select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bus clock divided by 2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock (ALTCLK).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Asynchronous clock (ADACK).</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion mode selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output .</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLSMP</name>
|
|
<description>Sample time configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Short sample time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Long sample time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock divide select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The divide ratio is 1 and the clock rate is input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLPC</name>
|
|
<description>Low-power configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal power configuration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low power configuration. The power is reduced at the expense of maximum clock speed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<description>Configuration register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADLSTS</name>
|
|
<description>Long sample time select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADHSC</name>
|
|
<description>High speed configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal conversion sequence selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACKEN</name>
|
|
<description>Asynchronous clock output enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Asynchronous clock and clock output enabled regardless of the state of the ADC.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXSEL</name>
|
|
<description>ADC Mux select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADxxa channels are selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADxxb channels are selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>R%s</name>
|
|
<description>ADC data result register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Data result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>CV%s</name>
|
|
<description>Compare value registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage reference selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair (external pins VREFH and VREFL)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare function range enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range function disabled. Only the compare value 1 register (CV1) is compared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range function enabled. Both compare value registers (CV1 and CV2) are compared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare function greater than enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare function enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion trigger select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and control register 3</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware average select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>4 samples averaged.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8 samples averaged.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16 samples averaged.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32 samples averaged.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware average enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware average function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware average function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous conversion enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALF</name>
|
|
<description>Calibration failed flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Calibration completed normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>ADC offset correction register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset error correction value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PG</name>
|
|
<description>ADC plus-side gain register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>Plus-side gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MG</name>
|
|
<description>ADC minus-side gain register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MG</name>
|
|
<description>Minus-side gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPD</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP4</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PGA</name>
|
|
<description>ADC PGA register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PGAG</name>
|
|
<description>PGA gain setting</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>4</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>8</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>16</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>32</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>64</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGALPb</name>
|
|
<description>PGA low-power mode control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PGA runs in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PGA runs in normal power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGAEN</name>
|
|
<description>PGA enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PGA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PGA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLMD</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLMD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLMS</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLMS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM4</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM3</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM2</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM1</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM0</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC1</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC1_</prependToName>
|
|
<baseAddress>0x400BB000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>SC1%s</name>
|
|
<description>ADC status and control registers 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module disabled.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Differential mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single-ended conversions and input channels are selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential conversions and input channels are selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion complete flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<description>ADC configuration register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input clock select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bus clock divided by 2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock (ALTCLK).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Asynchronous clock (ADACK).</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion mode selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output .</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLSMP</name>
|
|
<description>Sample time configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Short sample time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Long sample time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock divide select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The divide ratio is 1 and the clock rate is input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLPC</name>
|
|
<description>Low-power configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal power configuration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low power configuration. The power is reduced at the expense of maximum clock speed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<description>Configuration register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADLSTS</name>
|
|
<description>Long sample time select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADHSC</name>
|
|
<description>High speed configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal conversion sequence selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACKEN</name>
|
|
<description>Asynchronous clock output enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Asynchronous clock and clock output enabled regardless of the state of the ADC.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXSEL</name>
|
|
<description>ADC Mux select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADxxa channels are selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADxxb channels are selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>R%s</name>
|
|
<description>ADC data result register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Data result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>CV%s</name>
|
|
<description>Compare value registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage reference selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair (external pins VREFH and VREFL)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare function range enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range function disabled. Only the compare value 1 register (CV1) is compared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range function enabled. Both compare value registers (CV1 and CV2) are compared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare function greater than enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare function enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion trigger select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and control register 3</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware average select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>4 samples averaged.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8 samples averaged.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16 samples averaged.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32 samples averaged.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware average enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware average function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware average function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous conversion enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALF</name>
|
|
<description>Calibration failed flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Calibration completed normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>ADC offset correction register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset error correction value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PG</name>
|
|
<description>ADC plus-side gain register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>Plus-side gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MG</name>
|
|
<description>ADC minus-side gain register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MG</name>
|
|
<description>Minus-side gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPD</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP4</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0</name>
|
|
<description>ADC plus-side general calibration value register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PGA</name>
|
|
<description>ADC PGA register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PGAG</name>
|
|
<description>PGA gain setting</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>4</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>8</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>16</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>32</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>64</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGALPb</name>
|
|
<description>PGA low-power mode control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PGA runs in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PGA runs in normal power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGAEN</name>
|
|
<description>PGA enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PGA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PGA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLMD</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLMD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLMS</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLMS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM4</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM3</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM2</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM1</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLM0</name>
|
|
<description>ADC minus-side general calibration value register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLM0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Secure Real Time Clock</description>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x4003D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x808</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TSR</name>
|
|
<description>RTC Time Seconds Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSR</name>
|
|
<description>Time Seconds Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>RTC Time Prescaler Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPR</name>
|
|
<description>Time Prescaler Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR</name>
|
|
<description>RTC Time Alarm Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAR</name>
|
|
<description>Time Alarm Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>RTC Time Compensation Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Time Compensation Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10000000</name>
|
|
<description>Time prescaler register overflows every 32896 clock cycles.</description>
|
|
<value>#10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111111</name>
|
|
<description>Time prescaler register overflows every 32769 clock cycles.</description>
|
|
<value>#11111111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time prescaler register overflows every 32768 clock cycles.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time prescaler register overflows every 32767 clock cycles.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111111</name>
|
|
<description>Time prescaler register overflows every 32641 clock cycles.</description>
|
|
<value>#1111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIR</name>
|
|
<description>Compensation Interval Register</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCV</name>
|
|
<description>Time Compensation Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CIC</name>
|
|
<description>Compensation Interval Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>RTC Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers. The SWR bit is cleared after VBAT POR and by software explicitly clearing it.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPE</name>
|
|
<description>Wakeup Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wakeup pin is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts and the chip is powered down.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUP</name>
|
|
<description>Supervisor Access</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-supervisor mode write accesses are not supported and generate a bus error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Non-supervisor mode write accesses are supported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UM</name>
|
|
<description>Update Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Registers cannot be written when locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Registers can be written when locked under limited conditions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>32.768 kHz oscillator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The 32kHz clock is output to other peripherals</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The 32kHz clock is not output to other peripherals</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC16P</name>
|
|
<description>Oscillator 16pF load configure</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the load.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the additional load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC8P</name>
|
|
<description>Oscillator 8pF load configure</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the load.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the additional load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC4P</name>
|
|
<description>Oscillator 4pF load configure</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the load.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the additional load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC2P</name>
|
|
<description>Oscillator 2pF load configure</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the load.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the additional load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>RTC Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Time Invalid Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time is valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time is invalid and time counter is read as zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Time Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time overflow has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time overflow has occurred and time counter is read as zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAF</name>
|
|
<description>Time Alarm Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time alarm has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time alarm has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCE</name>
|
|
<description>Time Counter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time counter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time counter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LR</name>
|
|
<description>RTC Lock Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCL</name>
|
|
<description>Time Compensation Lock</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time compensation register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time compensation register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRL</name>
|
|
<description>Control Register Lock</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRL</name>
|
|
<description>Status Register Lock</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Status register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Status register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRL</name>
|
|
<description>Lock Register Lock</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Lock register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Lock register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>RTC Interrupt Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIIE</name>
|
|
<description>Time Invalid Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time invalid flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time invalid flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Time Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time overflow flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time overflow flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>Time Alarm Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time alarm flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time alarm flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAR</name>
|
|
<description>RTC Write Access Register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSRW</name>
|
|
<description>Time Seconds Register Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the time seconds register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the time seconds register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPRW</name>
|
|
<description>Time Prescaler Register Write</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the time prescaler register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the time prescaler register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TARW</name>
|
|
<description>Time Alarm Register Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the time alarm register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the time alarm register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCRW</name>
|
|
<description>Time Compensation Register Write</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the time compensation register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the time compensation register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRW</name>
|
|
<description>Control Register Write</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the control register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the control register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Status Register Write</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the status register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the status register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRW</name>
|
|
<description>Lock Register Write</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the lock register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the lock register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IERW</name>
|
|
<description>Interrupt Enable Register Write</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the interupt enable register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the interrupt enable register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAR</name>
|
|
<description>RTC Read Access Register</description>
|
|
<addressOffset>0x804</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSRR</name>
|
|
<description>Time Seconds Register Read</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the time seconds register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the time seconds register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPRR</name>
|
|
<description>Time Prescaler Register Read</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the time prescaler register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the time prescaler register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TARR</name>
|
|
<description>Time Alarm Register Read</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the time alarm register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the time alarm register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCRR</name>
|
|
<description>Time Compensation Register Read</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the time compensation register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the time compensation register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRR</name>
|
|
<description>Control Register Read</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the control register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the control register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRR</name>
|
|
<description>Status Register Read</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the status register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the status register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRR</name>
|
|
<description>Lock Register Read</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the lock register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the lock register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IERR</name>
|
|
<description>Interrupt Enable Register Read</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the interrupt enable register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the interrupt enable register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RFVBAT</name>
|
|
<description>VBAT register file</description>
|
|
<prependToName>RFVBAT_</prependToName>
|
|
<baseAddress>0x4003E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>REG%s</name>
|
|
<description>VBAT register file register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTMR0</name>
|
|
<description>Low Power Timer</description>
|
|
<prependToName>LPTMR0_</prependToName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPTimer</name>
|
|
<value>85</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Low Power Timer Control Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTMR is disabled and internal logic is reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTMR is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMS</name>
|
|
<description>Timer Mode Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time Counter mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFC</name>
|
|
<description>Timer Free Running Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTMR Counter Register is reset whenever the Timer Compare Flag is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTMR Counter Register is reset on overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPP</name>
|
|
<description>Timer Pin Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulse Counter input source is active high, and LPTMR Counter Register will increment on the rising edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter input source is active low, and LPTMR Counter Register will increment on the falling edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Timer Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Pulse counter input 0 is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Pulse counter input 1 is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Pulse counter input 2 is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Pulse counter input 3 is selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Interrupt Disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Interrupt Enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Timer Compare Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTMR Counter Register has not equaled the LPTMR Compare Register and incremented</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTMR Counter Register has equaled the LPTMR Compare Register and incremented</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>Low Power Timer Prescale Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Prescaler Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prescaler/glitch filter clock 0 selected</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Prescaler/glitch filter clock 1 selected</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Prescaler/glitch filter clock 2 selected</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Prescaler/glitch filter clock 3 selected</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBYP</name>
|
|
<description>Prescaler Bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler/Glitch Filter is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler/Glitch Filter is bypassed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescale Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2 rising clock edges.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4 rising clock edges.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8 rising clock edges.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16 rising clock edges.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32 rising clock edges.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64 rising clock edges.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128 rising clock edges.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256 rising clock edges.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after 512 rising clock edges.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after 1024 rising clock edges.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after 2048 rising clock edges.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after 4096 rising clock edges.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after 8192 rising clock edges.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after 16384 rising clock edges.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after 32768 rising clock edges.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR</name>
|
|
<description>Low Power Timer Compare Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPARE</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNR</name>
|
|
<description>Low Power Timer Counter Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RFSYS</name>
|
|
<description>System register file</description>
|
|
<prependToName>RFSYS_</prependToName>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>REG%s</name>
|
|
<description>Register file register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TSI0</name>
|
|
<description>Touch Sensing Input</description>
|
|
<prependToName>TSI0_</prependToName>
|
|
<baseAddress>0x40045000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x160</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TSI0</name>
|
|
<value>83</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>GENCS</name>
|
|
<description>General Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TSI when MCU enters low-power modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allow TSI to continue running in all low power modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STM</name>
|
|
<description>Scan trigger mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger scan</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Periodical scan</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESOR</name>
|
|
<description>End-of-scan or out-of-range interrupt select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Out-of-range interrupt selected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End-of-scan interrupt selected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERIE</name>
|
|
<description>TSI error interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIIE</name>
|
|
<description>TSI interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIEN</name>
|
|
<description>TSI module enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TSI disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TSI enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWTS</name>
|
|
<description>Software trigger start</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCNIP</name>
|
|
<description>Scan-in-progress status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRF</name>
|
|
<description>Overrun error flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTERF</name>
|
|
<description>External electrode error occurred</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No short</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Short to VDD or VSS occured on the electrodes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTRGF</name>
|
|
<description>Out of Range Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOSF</name>
|
|
<description>End of scan flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Electrode oscillator prescaler</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Electrode oscillator frequency divided by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Electrode oscillator frequency divided by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Electrode oscillator frequency divided by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Electrode oscillator frequency divided by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Electrode oscillator frequency divided by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Electrode oscillator frequency divided by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Electrode oscillator frequency divided by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Electrode oscillator frequency divided by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSCN</name>
|
|
<description>Number of Consecutive Scans per Electrode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>1 time per electrode</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>2 times per electrode</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>3 times per electrode</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>4 times per electrode</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>5 times per electrode</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>6 times per electrode</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>7 times per electrode</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>8 times per electrode</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>9 times per electrode</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>10 times per electrode</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>11 times per electrode</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>12 times per electrode</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>13 times per electrode</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>14 times per electrode</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>15 times per electrode</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>16 times per electrode</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>17 times per electrode</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>18 times per electrode</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>19 times per electrode</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>20 times per electrode</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>21 times per electrode</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>22 times per electrode</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>23 times per electrode</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>24 times per electrode</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>25 times per electrode</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>26 times per electrode</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>27 times per electrode</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>28 times per electrode</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>29 times per electrode</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>30 times per electrode</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>31 times per electrode</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>32 times per electrode</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSCNITV</name>
|
|
<description>TSI Low Power Mode Scan Interval</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>1 ms scan interval</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>5 ms scan interval</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>10 ms scan interval</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>15 ms scan interval</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>20 ms scan interval</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>30 ms scan interval</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>40 ms scan interval</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>50 ms scan interval</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>75 ms scan interval</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>100 ms scan interval</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>125 ms scan interval</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>150 ms scan interval</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>200 ms scan interval</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>300 ms scan interval</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>400 ms scan interval</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>500 ms scan interval</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPCLKS</name>
|
|
<description>Low Power Mode Clock Source Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPOCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLPOSCCLK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCANC</name>
|
|
<description>SCAN control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMPSC</name>
|
|
<description>Active mode prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Input clock source divided by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Input clock source divided by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Input clock source divided by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Input clock source divided by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Input clock source divided by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Input clock source divided by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Input clock source divided by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Input clock source divided by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AMCLKS</name>
|
|
<description>Active mode clock source</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus Clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGIRCLK</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Not valid</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AMCLKDIV</name>
|
|
<description>Active mode clock divider</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divider set to 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divider set to 2048</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Scan modulo</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000000</name>
|
|
<description>Continuous scan</description>
|
|
<value>#00000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DELVOL</name>
|
|
<description>Delta voltage select applied to analog oscillators</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>100 mV delta voltage is applied</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>150 mV delta voltage is applied</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>200 mV delta voltage is applied</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>250 mV delta voltage is applied</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>300 mV delta voltage is applied</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>400 mV delta voltage is applied</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>500 mV delta voltage is applied</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>600 mV delta voltage is applied</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTCHRG</name>
|
|
<description>External oscillator charge current select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>1 uA charge current</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>2 uA charge current</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>3 uA charge current</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>4 uA charge current</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>5 uA charge current</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>6 uA charge current</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>7 uA charge current</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>8 uA charge current</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>9 uA charge current</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>10 uA charge current</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>11 uA charge current</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>12 uA charge current</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>13 uA charge current</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>14 uA charge current</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>15 uA charge current</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>16 uA charge current</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>17 uA charge current</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>18 uA charge current</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>19 uA charge current</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>20 uA charge current</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>21 uA charge current</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>22 uA charge current</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>23 uA charge current</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>24 uA charge current</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>25 uA charge current</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>26 uA charge current</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>27 uA charge current</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>28 uA charge current</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>29 uA charge current</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>30 uA charge current</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>31 uA charge current</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>32 uA charge current</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTRM</name>
|
|
<description>Internal capacitance trim value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>0.5 pF internal reference capacitance</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>0.6 pF internal reference capacitance</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>0.7 pF internal reference capacitance</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>0.8 pF internal reference capacitance</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>0.9 pF internal reference capacitance</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>1.0 pF internal reference capacitance</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>1.1 pF internal reference capacitance</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>1.2 pF internal reference capacitance</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFCHRG</name>
|
|
<description>Reference oscillator charge current select</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>1 uA charge current</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>2 uA charge current</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>3 uA charge current</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>4 uA charge current</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>5 uA charge current</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>6 uA charge current</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>7 uA charge current</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>8 uA charge current</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>9 uA charge current</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>10 uA charge current</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>11 uA charge current</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>12 uA charge current</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>13 uA charge current</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>14 uA charge current</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>15 uA charge current</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>16 uA charge current</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>17 uA charge current</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>18 uA charge current</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>19 uA charge current</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>20 uA charge current</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>21 uA charge current</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>22 uA charge current</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>23 uA charge current</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>24 uA charge current</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>25 uA charge current</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>26 uA charge current</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>27 uA charge current</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>28 uA charge current</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>29 uA charge current</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>30 uA charge current</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>31 uA charge current</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>32 uA charge current</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEN</name>
|
|
<description>Pin enable register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEN0</name>
|
|
<description>TSI pin 0 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN1</name>
|
|
<description>TSI pin 1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN2</name>
|
|
<description>TSI pin 2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN3</name>
|
|
<description>TSI pin 3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN4</name>
|
|
<description>TSI pin 4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN5</name>
|
|
<description>TSI pin 5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN6</name>
|
|
<description>TSI pin 6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN7</name>
|
|
<description>TSI pin 7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN8</name>
|
|
<description>TSI pin 8 enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN9</name>
|
|
<description>TSI pin 9 enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN10</name>
|
|
<description>TSI pin 10 enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN11</name>
|
|
<description>TSI pin 11 enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN12</name>
|
|
<description>TSI pin 12 enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN13</name>
|
|
<description>TSI pin 13 enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN14</name>
|
|
<description>TSI pin 14 enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN15</name>
|
|
<description>TSI pin 15 enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding pin is not used by TSI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding pin is used by TSI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSP</name>
|
|
<description>Low-power scan pin</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>TSI_IN[0] is active in low power mode</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>TSI_IN[1] is active in low power mode</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>TSI_IN[2] is active in low power mode</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>TSI_IN[3] is active in low power mode</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>TSI_IN[4] is active in low power mode</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>TSI_IN[5] is active in low power mode</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>TSI_IN[6] is active in low power mode</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>TSI_IN[7] is active in low power mode</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>TSI_IN[8] is active in low power mode</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>TSI_IN[9] is active in low power mode</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>TSI_IN[10] is active in low power mode</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>TSI_IN[11] is active in low power mode</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>TSI_IN[12] is active in low power mode</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>TSI_IN[13] is active in low power mode</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>TSI_IN[14] is active in low power mode</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>TSI_IN[15] is active in low power mode</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ORNGF0</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF1</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF2</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF3</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF4</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF5</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF6</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF7</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF8</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF9</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF10</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF11</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF12</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF13</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF14</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ORNGF15</name>
|
|
<description>Touch Sensing Electrode Out-of-Range Flag 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF0</name>
|
|
<description>TouchSensing Error Flag 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF1</name>
|
|
<description>TouchSensing Error Flag 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF2</name>
|
|
<description>TouchSensing Error Flag 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF3</name>
|
|
<description>TouchSensing Error Flag 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF4</name>
|
|
<description>TouchSensing Error Flag 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF5</name>
|
|
<description>TouchSensing Error Flag 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF6</name>
|
|
<description>TouchSensing Error Flag 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF7</name>
|
|
<description>TouchSensing Error Flag 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF8</name>
|
|
<description>TouchSensing Error Flag 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF9</name>
|
|
<description>TouchSensing Error Flag 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF10</name>
|
|
<description>TouchSensing Error Flag 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF11</name>
|
|
<description>TouchSensing Error Flag 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF12</name>
|
|
<description>TouchSensing Error Flag 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF13</name>
|
|
<description>TouchSensing Error Flag 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF14</name>
|
|
<description>TouchSensing Error Flag 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROF15</name>
|
|
<description>TouchSensing Error Flag 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,3,5,7,9,11,13,15</dimIndex>
|
|
<name>CNTR%s</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTN1</name>
|
|
<description>Touch sensing channel n-1 counter value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTN</name>
|
|
<description>Touch sensing channel n counter value.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>THRESHLD%s</name>
|
|
<description>Channel n threshold register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTHH</name>
|
|
<description>High threshold value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LTHH</name>
|
|
<description>Low threshold value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SIM</name>
|
|
<description>System Integration Module</description>
|
|
<prependToName>SIM_</prependToName>
|
|
<baseAddress>0x40047000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1064</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SOPT1</name>
|
|
<description>System Options Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAMSIZE</name>
|
|
<description>RAM size</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Undefined</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Undefined</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Undefined</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Undefined</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Undefined</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>32 KBytes</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Undefined</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>64 KBytes</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>96 KBytes</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>128 KBytes</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Undefined</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Undefined</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Undefined</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Undefined</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Undefined</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Undefined</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KSEL</name>
|
|
<description>32K oscillator clock select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System oscillator (OSC32KCLK)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC oscillator</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>EzPort chip select pin state</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBSTBY</name>
|
|
<description>USB voltage regulator in standby mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB voltage regulator not in standby.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB voltage regulator in standby.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBREGEN</name>
|
|
<description>USB voltage regulator enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB voltage regulator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB voltage regulator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT2</name>
|
|
<description>System Options Register 2</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCGCLKSEL</name>
|
|
<description>MCG clock select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System oscillator (OSCCLK)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32 kHz RTC oscillator</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBSL</name>
|
|
<description>FlexBus security level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>All off-chip accesses (instruction and data) via the FlexBus are disallowed.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>All off-chip accesses (instruction and data) via the FlexBus are disallowed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Off-chip instruction accesses are disallowed. Data accesses are allowed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Off-chip instruction accesses and data accesses are allowed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMTUARTPAD</name>
|
|
<description>CMT/UART pad drive strength</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single-pad drive strength for CMT IRO or UART0_TXD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Dual-pad drive strength for CMT IRO or UART0_TXD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRACECLKSEL</name>
|
|
<description>Debug trace clock select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGOUTCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Core/system clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLFLLSEL</name>
|
|
<description>PLL/FLL clock select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGFLLCLK clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGPLLCLK clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBSRC</name>
|
|
<description>USB clock source select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External bypass clock (USB_CLKIN).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the SIM_CLKDIV2[USBFRAC, USBDIV] descriptions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMESRC</name>
|
|
<description>IEEE 1588 timestamp clock source select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Core/system clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGPLLCLK/MCGFLLCLK clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External bypass clock (ENET_1588_CLKIN).</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2SSRC</name>
|
|
<description>I2S master clock source select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Core/system clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGPLLCLK/MCGFLLCLK clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External bypass clock (I2S0_CLKIN)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDHCSRC</name>
|
|
<description>SDHC clock source select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Core/system clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCGPLLCLK/MCGFLLCLK clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>OSCERCLK clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External bypass clock (SDHC0_CLKIN)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT4</name>
|
|
<description>System Options Register 4</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTM0FLT0</name>
|
|
<description>FTM0 Fault 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM0_FLT0 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP0 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0FLT1</name>
|
|
<description>FTM0 Fault 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM0_FLT1 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP1 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0FLT2</name>
|
|
<description>FTM0 Fault 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM0_FLT2 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP2 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1FLT0</name>
|
|
<description>FTM1 Fault 0 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM1_FLT0 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP0 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2FLT0</name>
|
|
<description>FTM2 Fault 0 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM2_FLT0 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMP0 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1CH0SRC</name>
|
|
<description>FTM1 channel 0 input capture source select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM1_CH0 signal</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CH0SRC</name>
|
|
<description>FTM2 channel 0 input capture source select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2_CH0 signal</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0CLKSEL</name>
|
|
<description>FlexTimer 0 External Clock Pin Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM_CLK0 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM_CLK1 pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1CLKSEL</name>
|
|
<description>FTM1 External Clock Pin Select</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM_CLK0 pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM_CLK1 pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CLKSEL</name>
|
|
<description>FlexTimer 2 External Clock Pin Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM2 external clock driven by FTM_CLK0 pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM2 external clock driven by FTM_CLK1 pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT5</name>
|
|
<description>System Options Register 5</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART0TXSRC</name>
|
|
<description>UART 0 transmit data source select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>UART0_TX pin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>UART0_TX pin modulated with FTM1 channel 0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>UART0_TX pin modulated with FTM2 channel 0 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0RXSRC</name>
|
|
<description>UART 0 receive data source select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>UART0_RX pin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTTXSRC</name>
|
|
<description>UART 1 transmit data source select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>UART1_TX pin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>UART1_TX pin modulated with FTM1 channel 0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>UART1_TX pin modulated with FTM2 channel 0 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1RXSRC</name>
|
|
<description>UART 1 receive data source select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>UART1_RX pin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT6</name>
|
|
<description>System Options Register 6</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTFLTSEL</name>
|
|
<description>Reset pin filter select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTFLTEN</name>
|
|
<description>Reset pin filter enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>All filtering disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Bus clock filter enabled in normal operation. LPO clock filter enabled in stop mode.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LPO clock filter enabled</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Bus clock filter enabled in normal operation. All filtering disabled in stop mode.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LPO clock filter enabled in normal operation. All filtering disabled in stop mode.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Reserved (all filtering disabled)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Reserved (all filtering disabled)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Reserved (all filtering disabled)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT7</name>
|
|
<description>System Options Register 7</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0TRGSEL</name>
|
|
<description>ADC0 trigger select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>PDB external trigger pin input (PDB0_EXTRG)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>High speed comparator 0 output</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>High speed comparator 1 output</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>High speed comparator 2 output</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PIT trigger 0</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>PIT trigger 1</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PIT trigger 2</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PIT trigger 3</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>FTM0 trigger</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>FTM1 trigger</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>FTM2 trigger</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Unused</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>RTC alarm</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>RTC seconds</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Low-power timer trigger</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Unused</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0PRETRGSEL</name>
|
|
<description>ADC0 pretrigger select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pre-trigger A</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pre-trigger B</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0ALTTRGEN</name>
|
|
<description>ADC0 alternate trigger enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB trigger selected for ADC0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternate trigger selected for ADC0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1TRGSEL</name>
|
|
<description>ADC1 trigger select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>PDB external trigger pin input (PDB0_EXTRG)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>High speed comparator 0 output</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>High speed comparator 1 output</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>High speed comparator 2 output</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PIT trigger 0</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>PIT trigger 1</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PIT trigger 2</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PIT trigger 3</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>FTM0 trigger</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>FTM1 trigger</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>FTM2 trigger</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Unused</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>RTC alarm</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>RTC seconds</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Low-power timer trigger</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Unused</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1PRETRGSEL</name>
|
|
<description>ADC1 pre-trigger select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pre-trigger A selected for ADC1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pre-trigger B selected for ADC1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1ALTTRGEN</name>
|
|
<description>ADC1 alternate trigger enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB trigger selected for ADC1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDID</name>
|
|
<description>System Device Identification Register</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINID</name>
|
|
<description>Pincount identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>32-pin</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>48-pin</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>64-pin</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>80-pin</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>81-pin</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>100-pin</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>121-pin</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>144-pin</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>196-pin</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>256-pin</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAMID</name>
|
|
<description>Kinetis family identification</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>K10</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>K20</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>K30</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>K40</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>K60</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>K70</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>K50 and K52</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>K51 and K53</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REVID</name>
|
|
<description>Device revision number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC1</name>
|
|
<description>System Clock Gating Control Register 1</description>
|
|
<addressOffset>0x1028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART4</name>
|
|
<description>UART4 Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART5</name>
|
|
<description>UART5 Clock Gate Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP</name>
|
|
<description>OPAMP Clock Gate Control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIAMP</name>
|
|
<description>TRIAMP Clock Gate Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC2</name>
|
|
<description>System Clock Gating Control Register 2</description>
|
|
<addressOffset>0x102C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENET</name>
|
|
<description>ENET Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC0</name>
|
|
<description>DAC0 Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC1</name>
|
|
<description>DAC1 Clock Gate Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC3</name>
|
|
<description>System Clock Gating Control Register 3</description>
|
|
<addressOffset>0x1030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RNGB</name>
|
|
<description>RNGB Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2</name>
|
|
<description>SPI2 Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDHC</name>
|
|
<description>SDHC Clock Gate Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2</name>
|
|
<description>FTM2 Clock Gate Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1</name>
|
|
<description>ADC1 Clock Gate Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC4</name>
|
|
<description>System Clock Gating Control Register 4</description>
|
|
<addressOffset>0x1034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x60100030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWM</name>
|
|
<description>EWM Clock Gate Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMT</name>
|
|
<description>CMT Clock Gate Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>I2C0 Clock Gate Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>I2C1 Clock Gate Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0</name>
|
|
<description>UART0 Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1</name>
|
|
<description>UART1 Clock Gate Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2</name>
|
|
<description>UART2 Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART3</name>
|
|
<description>UART3 Clock Gate Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBOTG</name>
|
|
<description>USB Clock Gate Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Comparator Clock Gate Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREF</name>
|
|
<description>VREF Clock Gate Control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LLWU</name>
|
|
<description>LLWU Clock Gate Control</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC5</name>
|
|
<description>System Clock Gating Control Register 5</description>
|
|
<addressOffset>0x1038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40180</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIMER</name>
|
|
<description>Low Power Timer Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGFILE</name>
|
|
<description>Register File Clock Gate Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSI</name>
|
|
<description>TSI Clock Gate Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTA</name>
|
|
<description>Port A Clock Gate Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTB</name>
|
|
<description>Port B Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTC</name>
|
|
<description>Port C Clock Gate Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTD</name>
|
|
<description>Port D Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTE</name>
|
|
<description>Port E Clock Gate Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC6</name>
|
|
<description>System Clock Gating Control Register 6</description>
|
|
<addressOffset>0x103C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTFL</name>
|
|
<description>Flash Memory Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUX</name>
|
|
<description>DMA Mux Clock Gate Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>SPI0 Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1</name>
|
|
<description>SPI1 Clock Gate Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S</name>
|
|
<description>I2S Clock Gate Control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>CRC Clock Gate Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBDCD</name>
|
|
<description>USB DCD Clock Gate Control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDB</name>
|
|
<description>PDB Clock Gate Control</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIT</name>
|
|
<description>PIT Clock Gate Control</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0</name>
|
|
<description>FTM0 Clock Gate Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1</name>
|
|
<description>FTM1 Clock Gate Control</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0</name>
|
|
<description>ADC0 Clock Gate Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>RTC Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC7</name>
|
|
<description>System Clock Gating Control Register 7</description>
|
|
<addressOffset>0x1040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXBUS</name>
|
|
<description>FlexBus Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Clock Gate Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPU</name>
|
|
<description>MPU Clock Gate Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV1</name>
|
|
<description>System Clock Divider Register 1</description>
|
|
<addressOffset>0x1044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUTDIV4</name>
|
|
<description>Clock 4 output divider value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV3</name>
|
|
<description>Clock 3 output divider value</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV2</name>
|
|
<description>Clock 2 output divider value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV1</name>
|
|
<description>Clock 1 output divider value</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV2</name>
|
|
<description>System Clock Divider Register 2</description>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBFRAC</name>
|
|
<description>USB clock divider fraction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBDIV</name>
|
|
<description>USB clock divider divisor</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SFRAC</name>
|
|
<description>I2S clock divider fraction</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SDIV</name>
|
|
<description>I2S clock divider value</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG1</name>
|
|
<description>Flash Configuration Register 1</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEPART</name>
|
|
<description>FlexNVM partition</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EESIZE</name>
|
|
<description>EEPROM size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>4 KB</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>2 KB</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>1 KB</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>512 Bytes</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>256 Bytes</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 Bytes</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>64 Bytes</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>32 Bytes</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>0 Bytes</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSIZE</name>
|
|
<description>Program flash size</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 KB of program flash memory, 4 KB protection region</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>256 KB of program flash memory, 8 KB protection region</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>512 KB of program flash memory, 16 KB protection region</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>For devices without FlexNVM (SIM_FCFG2[PFLSH]=1): 512 KB of program flash memory, 16 KB protection region</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVMSIZE</name>
|
|
<description>FlexNVM size</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 KB of FlexNVM</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 KB of FlexNVM, 16 KB protection region</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>256 KB of FlexNVM, 32 KB protection region</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>256 KB of FlexNVM, 32 KB protection region</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG2</name>
|
|
<description>Flash Configuration Register 2</description>
|
|
<addressOffset>0x1050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXADDR1</name>
|
|
<description>Max address block 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFLSH</name>
|
|
<description>Program flash</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Physical flash block 1 is used as program flash</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAXADDR0</name>
|
|
<description>Max address block 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWAPPFLSH</name>
|
|
<description>Swap program flash</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Swap is not active.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Swap is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDH</name>
|
|
<description>Unique Identification Register High</description>
|
|
<addressOffset>0x1054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDMH</name>
|
|
<description>Unique Identification Register Mid-High</description>
|
|
<addressOffset>0x1058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDML</name>
|
|
<description>Unique Identification Register Mid Low</description>
|
|
<addressOffset>0x105C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDL</name>
|
|
<description>Unique Identification Register Low</description>
|
|
<addressOffset>0x1060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTA</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTA_</prependToName>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTA</name>
|
|
<value>87</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>PCR%s</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-up or pull-down resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive Input Filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open Drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin Disabled (Analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip specific / JTAG / NMI).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register bits [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt/DMA Request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>DMA Request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>DMA Request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>DMA Request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filters are clocked by the 1 kHz LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTB</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTB_</prependToName>
|
|
<baseAddress>0x4004A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTB</name>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
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|
<name>PCR%s</name>
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<description>Pin Control Register n</description>
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<addressOffset>0</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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|
<fields>
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|
<field>
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|
<name>PS</name>
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<description>Pull Select</description>
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|
<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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|
<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>0</name>
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<description>Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
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<value>#0</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>1</name>
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|
<description>Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
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<value>#1</value>
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</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
|
|
<name>PE</name>
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|
<description>Pull Enable</description>
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|
<bitOffset>1</bitOffset>
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|
<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
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|
<description>Internal pull-up or pull-down resistor is not enabled on the corresponding pin.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
|
|
<name>SRE</name>
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|
<description>Slew Rate Enable</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>0</name>
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|
<description>Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
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|
<value>#1</value>
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</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
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|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
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<bitOffset>4</bitOffset>
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|
<bitWidth>1</bitWidth>
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<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive Input Filter is disabled on the corresponding pin.</description>
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<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
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|
<name>1</name>
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|
<description>Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.</description>
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<value>#1</value>
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</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
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|
<name>ODE</name>
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|
<description>Open Drain Enable</description>
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|
<bitOffset>5</bitOffset>
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|
<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open Drain output is disabled on the corresponding pin.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
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|
<bitOffset>8</bitOffset>
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|
<bitWidth>3</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin Disabled (Analog).</description>
|
|
<value>#000</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip specific).</description>
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|
<value>#010</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip specific).</description>
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|
<value>#011</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip specific).</description>
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|
<value>#100</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip specific).</description>
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|
<value>#101</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip specific).</description>
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|
<value>#110</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip specific / JTAG / NMI).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
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|
<field>
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|
<name>LK</name>
|
|
<description>Lock Register</description>
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<bitOffset>15</bitOffset>
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<bitWidth>1</bitWidth>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register bits [15:0] are not locked.</description>
|
|
<value>#0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.</description>
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|
<value>#1</value>
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|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt/DMA Request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>DMA Request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>DMA Request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>DMA Request on either edge.</description>
|
|
<value>#0011</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.</description>
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|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filters are clocked by the 1 kHz LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTC</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTC_</prependToName>
|
|
<baseAddress>0x4004B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTC</name>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>PCR%s</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-up or pull-down resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive Input Filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open Drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin Disabled (Analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip specific / JTAG / NMI).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register bits [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt/DMA Request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>DMA Request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>DMA Request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>DMA Request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filters are clocked by the 1 kHz LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTD</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTD_</prependToName>
|
|
<baseAddress>0x4004C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTD</name>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>PCR%s</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-up or pull-down resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive Input Filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open Drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin Disabled (Analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip specific / JTAG / NMI).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register bits [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt/DMA Request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>DMA Request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>DMA Request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>DMA Request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filters are clocked by the 1 kHz LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTE</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTE_</prependToName>
|
|
<baseAddress>0x4004D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTE</name>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>PCR%s</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pull-up or pull-down resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive Input Filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open Drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin Disabled (Analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip specific / JTAG / NMI).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register bits [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt/DMA Request disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>DMA Request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>DMA Request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>DMA Request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Interrupt when logic zero.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Interrupt on rising edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Interrupt on falling edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Interrupt when logic one.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital Filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital Filters are clocked by the 1 kHz LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDOG</name>
|
|
<description>Generation 2008 Watchdog Timer</description>
|
|
<prependToName>WDOG_</prependToName>
|
|
<baseAddress>0x40052000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>Watchdog</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STCTRLH</name>
|
|
<description>Watchdog Status and Control Register High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1D3</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDOGEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Dedicated clock source selected as WDOG clock (LPO Oscillator).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG clock sourced from alternate clock source.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQRSTEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG time-out generates reset only.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG time-out initially generates an interrupt. After WCT time, it generates a reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WINEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALLOWUPDATE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No further updates allowed to WDOG write once registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG write once registers can be unlocked for updating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is disabled in CPU Debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is enabled in CPU Debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is disabled in CPU stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is enabled in CPU stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is disabled in CPU wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is enabled in CPU wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STNDBYEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is disabled in system Standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is enabled in system Standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TESTWDOG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TESTSEL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYTESEL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Byte 0 selected</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Byte 1 selected</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Byte 2 selected</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Byte 3 selected</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISTESTWDOG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG functional test mode is not disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG functional test mode is disabled permanently until reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCTRLL</name>
|
|
<description>Watchdog Status and Control Register Low</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTFLG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVALH</name>
|
|
<description>Watchdog Time-out Value Register High</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4C</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALHIGH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVALL</name>
|
|
<description>Watchdog Time-out Value Register Low</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4B4C</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALLOW</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINH</name>
|
|
<description>Watchdog Window Register High</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINHIGH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINL</name>
|
|
<description>Watchdog Window Register Low</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINLOW</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFRESH</name>
|
|
<description>Watchdog Refresh Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB480</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDOGREFRESH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UNLOCK</name>
|
|
<description>Watchdog Unlock Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xD928</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDOGUNLOCK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMROUTH</name>
|
|
<description>Watchdog Timer Output Register High</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEROUTHIGH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMROUTL</name>
|
|
<description>Watchdog Timer Output Register Low</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEROUTLOW</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCNT</name>
|
|
<description>Watchdog Reset Count Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESC</name>
|
|
<description>Watchdog Prescaler Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCVAL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EWM</name>
|
|
<description>External Watchdog Monitor</description>
|
|
<prependToName>EWM_</prependToName>
|
|
<baseAddress>0x40061000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWMEN</name>
|
|
<description>EWM enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASSIN</name>
|
|
<description>EWM_in's Assertion State Select.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERV</name>
|
|
<description>Service Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERVICE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPL</name>
|
|
<description>Compare Low Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPH</name>
|
|
<description>Compare High Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMT</name>
|
|
<description>Carrier Modulator Transmitter</description>
|
|
<prependToName>CMT_</prependToName>
|
|
<baseAddress>0x40062000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMT</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CGH1</name>
|
|
<description>CMT Carrier Generator High Data Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH</name>
|
|
<description>Primary Carrier High Time Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGL1</name>
|
|
<description>CMT Carrier Generator Low Data Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>Primary Carrier Low Time Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGH2</name>
|
|
<description>CMT Carrier Generator High Data Register 2</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SH</name>
|
|
<description>Secondary Carrier High Time Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGL2</name>
|
|
<description>CMT Carrier Generator Low Data Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SL</name>
|
|
<description>Secondary Carrier Low Time Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OC</name>
|
|
<description>CMT Output Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IROPEN</name>
|
|
<description>IRO Pin Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMT_IRO signal disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMT_IRO signal enabled as output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMTPOL</name>
|
|
<description>CMT Output Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMT_IRO signal is active low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMT_IRO signal is active high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IROL</name>
|
|
<description>IRO Latch Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC</name>
|
|
<description>CMT Modulator Status and Control Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCGEN</name>
|
|
<description>Modulator and Carrier Generator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modulator and carrier generator disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modulator and carrier generator enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOCIE</name>
|
|
<description>End of Cycle Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSK</name>
|
|
<description>FSK Mode Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMT operates in Time or Baseband mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMT operates in FSK mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BASE</name>
|
|
<description>Baseband Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Baseband mode disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Baseband mode enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXSPC</name>
|
|
<description>Extended Space Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Extended space disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended space enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMTDIV</name>
|
|
<description>CMT Clock Divide Prescaler</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>IF * 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>IF * 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>IF * 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>IF * 8</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOCF</name>
|
|
<description>End Of Cycle Status Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No end of modulation cycle occurrence since flag last cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End of modulator cycle has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD1</name>
|
|
<description>CMT Modulator Data Register Mark High</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD2</name>
|
|
<description>CMT Modulator Data Register Mark Low</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD3</name>
|
|
<description>CMT Modulator Data Register Space High</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD4</name>
|
|
<description>CMT Modulator Data Register Space Low</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPS</name>
|
|
<description>CMT Primary Prescaler Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PPSDIV</name>
|
|
<description>Primary Prescaler Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Bus Clock * 1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Bus Clock * 2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Bus Clock * 3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Bus Clock * 4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Bus Clock * 5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Bus Clock * 6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Bus Clock * 7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Bus Clock * 8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Bus Clock * 9</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Bus Clock * 10</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Bus Clock * 11</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Bus Clock * 12</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Bus Clock * 13</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Bus Clock * 14</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Bus Clock * 15</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Bus Clock * 16</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA</name>
|
|
<description>CMT Direct Memory Access</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA transfer request and done are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA transfer request and done are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCG</name>
|
|
<description>Multipurpose Clock Generator module</description>
|
|
<prependToName>MCG_</prependToName>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>MCG Control 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREFSTEN</name>
|
|
<description>Internal Reference Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal reference clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRCLKEN</name>
|
|
<description>Internal Reference Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGIRCLK inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGIRCLK active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFS</name>
|
|
<description>Internal Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The slow internal reference clock is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDIV</name>
|
|
<description>FLL External Reference Divider</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved .</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved .</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - External reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Encoding 3 - Reserved, defaults to 00.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>MCG Control 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCS</name>
|
|
<description>Internal Reference Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow internal reference clock selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast internal reference clock selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LP</name>
|
|
<description>Low Power Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL (or PLL) is not disabled in bypass modes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL (or PLL) is disabled in bypass modes (lower power)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EREFS</name>
|
|
<description>External Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HGO</name>
|
|
<description>High Gain Oscillator Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configure crystal oscillator for low-power operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configure crystal oscillator for high-gain operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>Frequency Range Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Low frequency range selected for the crystal oscillator .</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - High frequency range selected for the crystal oscillator .</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>MCG Control 3 Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCTRIM</name>
|
|
<description>Slow Internal Reference Clock Trim Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>MCG Control 4 Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xE0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCFTRIM</name>
|
|
<description>Slow Internal Reference Clock Fine Trim</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FCTRIM</name>
|
|
<description>Fast Internal Reference Clock Trim Setting</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRST_DRS</name>
|
|
<description>DCO Range Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Low range (reset default).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Mid range.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - Mid-high range.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Encoding 3 - High range.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMX32</name>
|
|
<description>DCO Maximum Frequency with 32.768 kHz Reference</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DCO has a default range of 25%.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DCO is fine-tuned for maximum frequency with 32.768 kHz reference.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>MCG Control 5 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRDIV</name>
|
|
<description>PLL External Reference Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSTEN</name>
|
|
<description>PLL Stop Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGPLLCLK is disabled in any of the Stop modes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGPLLCLK is enabled if system is in Normal Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLCLKEN</name>
|
|
<description>PLL Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCGPLLCLK is inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCGPLLCLK is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C6</name>
|
|
<description>MCG Control 6 Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VDIV</name>
|
|
<description>VCO Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CME</name>
|
|
<description>Clock Monitor Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External clock monitor is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate a reset request on loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLS</name>
|
|
<description>PLL Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz prior to setting the PLLS bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOLIE</name>
|
|
<description>Loss of Lock Interrrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated on loss of lock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate an interrupt request on loss of lock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>MCG Status Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCST</name>
|
|
<description>Internal Reference Clock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of internal reference clock is the slow clock (32 kHz IRC).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of internal reference clock is the fast clock (2 MHz IRC).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCINIT</name>
|
|
<description>OSC Initialization</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKST</name>
|
|
<description>Clock Mode Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Encoding 0 - Output of the FLL is selected (reset default).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Encoding 1 - Internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Encoding 2 - External reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Encoding 3 - Output of the PLL is selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFST</name>
|
|
<description>Internal Reference Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of FLL reference clock is the external reference clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of FLL reference clock is the internal reference clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLST</name>
|
|
<description>PLL Select Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of PLLS clock is FLL clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of PLLS clock is PLL clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PLL is currently unlocked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PLL is currently locked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOLS</name>
|
|
<description>Loss of Lock Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PLL has not lost lock since LOLS was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PLL has lost lock since LOLS was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATC</name>
|
|
<description>MCG Auto Trim Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATMF</name>
|
|
<description>Automatic Trim machine Fail Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic Trim Machine completed normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic Trim Machine failed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATMS</name>
|
|
<description>Automatic Trim Machine Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>32 kHz Internal Reference Clock selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>4 MHz Internal Reference Clock selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATME</name>
|
|
<description>Automatic Trim Machine Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto Trim Machine disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto Trim Machine enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCVH</name>
|
|
<description>MCG Auto Trim Compare Value High Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATCVH</name>
|
|
<description>ATM Compare Value High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCVL</name>
|
|
<description>MCG Auto Trim Compare Value Low Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATCVL</name>
|
|
<description>ATM Compare Value Low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC</name>
|
|
<description>Oscillator</description>
|
|
<prependToName>OSC_</prependToName>
|
|
<baseAddress>0x40065000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>OSC Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SC16P</name>
|
|
<description>Oscillator 16 pF Capacitor Load Configure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 16 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC8P</name>
|
|
<description>Oscillator 8 pF Capacitor Load Configure</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 8 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC4P</name>
|
|
<description>Oscillator 4 pF Capacitor Load Configure</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 4 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SC2P</name>
|
|
<description>Oscillator 2 pF Capacitor Load Configure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the selection.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add 2 pF capacitor to the oscillator load.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EREFSTEN</name>
|
|
<description>External Reference Stop Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERCLKEN</name>
|
|
<description>External Reference Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External reference clock is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C0_</prependToName>
|
|
<baseAddress>0x40066000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>Clock rate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All DMA signalling disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit acknowledge enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit mode select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>I2C Status Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave read/write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range address match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed as a slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer complete flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range address matching enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave baud rate control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HDRS</name>
|
|
<description>High drive select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal drive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General call address enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C programmable filter factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range slave address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMB</name>
|
|
<description>I2C SMBus Control and Status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHTF2IE</name>
|
|
<description>SHTF2 interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SHTF2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SHTF2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF2</name>
|
|
<description>SCL high timeout flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF1</name>
|
|
<description>SCL high timeout flag 1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA high timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA high timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLTF</name>
|
|
<description>SCL low timeout flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCKSEL</name>
|
|
<description>Timeout counter clock select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout counter counts at the frequency of the bus clock / 64</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout counter counts at the frequency of the bus clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIICAEN</name>
|
|
<description>Second I2C address enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C address register 2 matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C address register 2 matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERTEN</name>
|
|
<description>SMBus alert response address enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus alert response address matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus alert response address matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FACK</name>
|
|
<description>Fast NACK/ACK enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An ACK or NACK is sent on the following receiving data byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>A2</name>
|
|
<description>I2C Address Register 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAD</name>
|
|
<description>SMBus address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTH</name>
|
|
<description>I2C SCL Low Timeout Register High</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTL</name>
|
|
<description>I2C SCL Low Timeout Register Low</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C1_</prependToName>
|
|
<baseAddress>0x40067000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>Clock rate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All DMA signalling disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit acknowledge enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit mode select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>I2C Status Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave read/write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range address match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed as a slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer complete flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range address matching enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave baud rate control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HDRS</name>
|
|
<description>High drive select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal drive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General call address enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C programmable filter factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range slave address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMB</name>
|
|
<description>I2C SMBus Control and Status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHTF2IE</name>
|
|
<description>SHTF2 interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SHTF2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SHTF2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF2</name>
|
|
<description>SCL high timeout flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF1</name>
|
|
<description>SCL high timeout flag 1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA high timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA high timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLTF</name>
|
|
<description>SCL low timeout flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCKSEL</name>
|
|
<description>Timeout counter clock select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout counter counts at the frequency of the bus clock / 64</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout counter counts at the frequency of the bus clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIICAEN</name>
|
|
<description>Second I2C address enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C address register 2 matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C address register 2 matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERTEN</name>
|
|
<description>SMBus alert response address enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus alert response address matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus alert response address matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FACK</name>
|
|
<description>Fast NACK/ACK enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An ACK or NACK is sent on the following receiving data byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>A2</name>
|
|
<description>I2C Address Register 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAD</name>
|
|
<description>SMBus address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTH</name>
|
|
<description>I2C SCL Low Timeout Register High</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTL</name>
|
|
<description>I2C SCL Low Timeout Register Low</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART0_</prependToName>
|
|
<baseAddress>0x4006A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0_RX_TX</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART0_ERR</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C7816</name>
|
|
<description>UART 7816 Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISO_7816E</name>
|
|
<description>ISO-7816 Functionality Enabled</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ISO-7816 functionality is turned off / not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ISO-7816 functionality is turned on / enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TTYPE</name>
|
|
<description>Transfer Type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>T = 0 Per the ISO-7816 specification.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>T = 1 Per the ISO-7816 specification.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Detect Initial Character</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operating mode. Receiver does not seek to identify initial character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver searches for initial character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANACK</name>
|
|
<description>Generate NACK on Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No NACK is automatically generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONACK</name>
|
|
<description>Generate NACK on Overflow</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The received data does not generate a NACK when the receipt of the data results in an overflow event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If the receiver buffer overflows, a NACK is automatically sent on a received character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE7816</name>
|
|
<description>UART 7816 Interrupt Enable Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXTE</name>
|
|
<description>Receive Threshold Exceeded Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[RXT] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[RXT] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXTE</name>
|
|
<description>Transmit Threshold Exceeded Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[TXT] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[TXT] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTVE</name>
|
|
<description>Guard Timer Violated Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[GTV] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[GTV] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITDE</name>
|
|
<description>Initial Character Detected Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[INITD] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[INITD] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWTE</name>
|
|
<description>Block Wait Timer Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[BWT] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[BWT] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CWTE</name>
|
|
<description>Character Wait Timer Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[CWT] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[CWT] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTE</name>
|
|
<description>Wait Timer Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The assertion of the IS7816[WT] bit will not result in the generation of an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the IS7816[WT] bit will result in the generation of an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IS7816</name>
|
|
<description>UART 7816 Interrupt Status Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>Receive Threshold Exceeded Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>Transmit Threshold Exceeded Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of retries and corresponding NACKS does not exceed the value in the ET7816[TXTHRESHOLD] field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of retries and corresponding NACKS exceeds the value in the ET7816[TXTHRESHOLD] field.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTV</name>
|
|
<description>Guard Timer Violated Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A guard time (GT, CGT or BGT) has not been violated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A guard time (GT, CGT or BGT) has been violated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITD</name>
|
|
<description>Initial Character Detected Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A valid initial character has not been received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A valid initial character has been received.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWT</name>
|
|
<description>Block Wait Timer Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Block wait time (BWT) has not been violated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Block wait tTime (BWT) has been violated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CWT</name>
|
|
<description>Character Wait Timer Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Character wait time (CWT) has not been violated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Character wait time (CWT) has been violated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WT</name>
|
|
<description>Wait Timer Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wait time (WT) has not been violated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wait time (WT) has been violated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WP7816T0</name>
|
|
<description>UART 7816 Wait Parameter Register</description>
|
|
<alternateGroup>UART0</alternateGroup>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WI</name>
|
|
<description>Wait Timer Interrupt (C7816[TTYPE] = 0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WP7816T1</name>
|
|
<description>UART 7816 Wait Parameter Register</description>
|
|
<alternateGroup>UART0</alternateGroup>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BWI</name>
|
|
<description>Block Wait Time Integer(C7816[TTYPE] = 1)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CWI</name>
|
|
<description>Character Wait Time Integer (C7816[TTYPE] = 1)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WN7816</name>
|
|
<description>UART 7816 Wait N Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTN</name>
|
|
<description>Guard Band N</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WF7816</name>
|
|
<description>UART 7816 Wait FD Register</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTFD</name>
|
|
<description>FD Multiplier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ET7816</name>
|
|
<description>UART 7816 Error Threshold Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXTHRESHOLD</name>
|
|
<description>Receive NACK Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTHRESHOLD</name>
|
|
<description>Transmit NACK Threshold</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TL7816</name>
|
|
<description>UART 7816 Transmit Length Register</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transmit Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART1</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART1_</prependToName>
|
|
<baseAddress>0x4006B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x17</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1_RX_TX</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART1_ERR</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART2</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART2_</prependToName>
|
|
<baseAddress>0x4006C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x17</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART2_RX_TX</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART2_ERR</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART3</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART3_</prependToName>
|
|
<baseAddress>0x4006D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x17</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART3_RX_TX</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART3_ERR</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART4</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART4_</prependToName>
|
|
<baseAddress>0x400EA000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x17</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART4_RX_TX</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART4_ERR</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART5</name>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART5_</prependToName>
|
|
<baseAddress>0x400EB000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x17</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART5_RX_TX</name>
|
|
<value>55</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART5_ERR</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Registers:High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RXEDGIF disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXEDGIF interrupt request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LBKDIF interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LBKDIF interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Registers: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>UART Baud Rate Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-bit or 8-bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects internal loop back mode and receiver input is internally connected to transmitter output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clock continues to run in wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clock freezes while CPU is in wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IDLE interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IDLE interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RDRF interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RDRF interrupt or DMA transfer requests enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TC interrupt requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TC interrupt requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDRE interrupt and DMA transfer requests disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDRE interrupt or DMA transfer requests enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmit Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle/inactive waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Transmit Character Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is 10, 11, or 12 bits long.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is 13 or 14 bits long.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wakeup Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The S1[IDLE] bit is not set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The S1[IDLE] bit is set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FE interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupt requests are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NF interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OR interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Transmit Bit 8</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Received Bit 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA1</name>
|
|
<description>UART Match Address Registers 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MA2</name>
|
|
<description>UART Match Address Registers 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Match Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>UART Control Register 4</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRFA</name>
|
|
<description>Baud Rate Fine Adjust</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The parity bit is the ninth bit in the serial transmission.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is the tenth bit in the serial transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5</name>
|
|
<description>UART Control Register 5</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDMAS</name>
|
|
<description>Receiver Full DMA Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAS</name>
|
|
<description>Transmitter DMA Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ED</name>
|
|
<description>UART Extended Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEM</name>
|
|
<description>UART Modem Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>UART Infrared Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>3/16.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/16.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFIFO</name>
|
|
<description>UART FIFO Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer Depth = 1 Dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer Depth = 4 Datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer Depth = 8 Datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer Depth = 16 Datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer Depth = 32 Datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer Depth = 64 Datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer Depth = 128 Datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>UART FIFO Control Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFIFO</name>
|
|
<description>UART FIFO Status Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TWFIFO</name>
|
|
<description>UART FIFO Transmit Watermark</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCFIFO</name>
|
|
<description>UART FIFO Transmit Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWFIFO</name>
|
|
<description>UART FIFO Receive Watermark</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCFIFO</name>
|
|
<description>UART FIFO Receive Count</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB0</name>
|
|
<description>Universal Serial Bus, OTG Capable Controller</description>
|
|
<prependToName>USB0_</prependToName>
|
|
<baseAddress>0x40072000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10D</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB0</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Peripheral identification bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDCOMP</name>
|
|
<description>Peripheral ID Complement Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFB</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REV</name>
|
|
<description>Peripheral Revision Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x33</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REV</name>
|
|
<description>Revision</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDINFO</name>
|
|
<description>Peripheral Additional Info Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IEHOST</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQNUM</name>
|
|
<description>Assigned Interrupt Request Number</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGISTAT</name>
|
|
<description>OTG Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVBUSCHG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B_SESS_CHG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESSVLDCHG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINE_STATE_CHG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ONEMSEC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDCHG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGICR</name>
|
|
<description>OTG Interrupt Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVBUSEN</name>
|
|
<description>A VBUS Valid interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The AVBUSCHG interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The AVBUSCHG interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSESSEN</name>
|
|
<description>B Session END interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The B_SESS_CHG interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The B_SESS_CHG interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SESSVLDEN</name>
|
|
<description>Session valid interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SESSVLDCHG interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SESSVLDCHG interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LINESTATEEN</name>
|
|
<description>Line State change interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The LINE_STAT_CHG interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The LINE_STAT_CHG interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONEMSECEN</name>
|
|
<description>1 millisecond interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The 1msec timer interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The 1msec timer interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDEN</name>
|
|
<description>ID interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ID interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ID interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGSTAT</name>
|
|
<description>OTG Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVBUSVLD</name>
|
|
<description>A VBUS Valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The VBUS voltage is below the A VBUS Valid threshold.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The VBUS voltage is above the A VBUS Valid threshold.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSESSEND</name>
|
|
<description>B Session END</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The VBUS voltage is above the B session End threshold.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The VBUS voltage is below the B session End threshold.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SESS_VLD</name>
|
|
<description>Session valid</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The VBUS voltage is below the B session Valid threshold</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The VBUS voltage is above the B session Valid threshold.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LINESTATESTABLE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The LINE_STAT_CHG bit is not yet stable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The LINE_STAT_CHG bit has been debounced and is stable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONEMSECEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates a Type A cable has been plugged into the USB connector</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates no cable is attached or a Type B cable has been plugged into the USB connector</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGCTL</name>
|
|
<description>OTG Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OTGEN</name>
|
|
<description>On-The-Go pullup/pulldown resistor enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>If USB_EN is set and HOST_MODE is clear in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is set the D+ and D- Data Line pull-down resistors are engaged.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The pull-up and pull-down controls in this register are used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMLOW</name>
|
|
<description>D- Data Line pull-down resistor enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D- pulldown resistor is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D- pulldown resistor is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPLOW</name>
|
|
<description>D+ Data Line pull-down resistor enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D+ pulldown resistor is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D+ pulldown resistor is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPHIGH</name>
|
|
<description>D+ Data Line pullup resistor enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D+ pullup resistor is not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D+ pullup resistor is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISTAT</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBRST</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFTOK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOKDNE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ATTACH</name>
|
|
<description>Attach Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBRSTEN</name>
|
|
<description>USBRST Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The USBRST interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The USBRST interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERROREN</name>
|
|
<description>ERROR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ERROR interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ERROR interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFTOKEN</name>
|
|
<description>SOFTOK Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SOFTOK interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SOFTOK interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOKDNEEN</name>
|
|
<description>TOKDNE Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The TOKDNE interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The TOKDNE interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPEN</name>
|
|
<description>SLEEP Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SLEEP interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SLEEP interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEEN</name>
|
|
<description>RESUME Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RESUME interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RESUME interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATTACHEN</name>
|
|
<description>ATTACH Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ATTACH interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ATTACH interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALLEN</name>
|
|
<description>STALL Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The STALL interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The STALL interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRSTAT</name>
|
|
<description>Error Interrupt Status Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIDERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRC5EOF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRC16</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DFN8</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTOERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTSERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERREN</name>
|
|
<description>Error Interrupt Enable Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIDERREN</name>
|
|
<description>PIDERR Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PIDERR interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PIDERR interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC5EOFEN</name>
|
|
<description>CRC5/EOF Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The CRC5/EOF interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CRC5/EOF interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC16EN</name>
|
|
<description>CRC16 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The CRC16 interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CRC16 interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFN8EN</name>
|
|
<description>DFN8 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DFN8 interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DFN8 interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BTOERREN</name>
|
|
<description>BTOERR Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The BTOERR interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The BTOERR interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAERREN</name>
|
|
<description>DMAERR Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMAERR interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMAERR interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BTSERREN</name>
|
|
<description>BTSERR Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The BTSERR interrupt is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The BTSERR interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ODD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Indicator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The most recent transaction was a Receive operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The most recent transaction was a Transmit operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBENSOFEN</name>
|
|
<description>USB Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The USB Module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The USB Module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODDRST</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTMODEEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSUSPENDTOKENBUSY</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SE0</name>
|
|
<description>Live USB Single Ended Zero signal</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JSTATE</name>
|
|
<description>Live USB differential receiver JSTATE signal</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>USB address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSEN</name>
|
|
<description>Low Speed Enable bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTPAGE1</name>
|
|
<description>BDT Page Register 1</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BDTBA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRMNUML</name>
|
|
<description>Frame Number Register Low</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRMNUMH</name>
|
|
<description>Frame Number Register High</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOKEN</name>
|
|
<description>Token Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOKENENDPT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOKENPID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>OUT Token. USB Module performs an OUT (TX) transaction.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>IN Token. USB Module performs an In (RX) transaction.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>SETUP Token. USB Module performs a SETUP (TX) transaction</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTHLD</name>
|
|
<description>SOF Threshold Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTPAGE2</name>
|
|
<description>BDT Page Register 2</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BDTBA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTPAGE3</name>
|
|
<description>BDT Page Register 3</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BDTBA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>ENDPT%s</name>
|
|
<description>Endpoint Control Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPHSHK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPSTALL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPRXEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPCTLDIS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RETRYDIS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTWOHUB</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCTRL</name>
|
|
<description>USB Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Weak pulldowns are disabled on D+ and D-</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Weak pulldowns are enabled on D+ and D-.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB transceiver is not in suspend state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB transceiver is in suspend state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OBSERVE</name>
|
|
<description>USB OTG Observe Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x50</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMPD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D- pulldown disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D- pulldown enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPPD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D+ pulldown disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D+ pulldown enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPPU</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D+ pullup disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D+ pullup enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>USB OTG Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPPULLUPNONOTG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DP Pull up in non-OTG device mode is not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DP Pull up in non-OTG device mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBTRC0</name>
|
|
<description>USB Transceiver Control Register 0</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RESUME_INT</name>
|
|
<description>USB Asynchronous Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt was generated because of the USB asynchronous interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_DET</name>
|
|
<description>Synchronous USB Interrupt Detect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Synchronous interrupt has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Synchronous interrupt has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBRESMEN</name>
|
|
<description>Asynchronous Resume Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB asynchronous wakeup from suspend mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interupt should only be enabled when the Transceiver is suspended.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBRESET</name>
|
|
<description>USB reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal USB module operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Returns the USB module to its reset state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP0</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<groupName>CMP</groupName>
|
|
<prependToName>CMP0_</prependToName>
|
|
<baseAddress>0x40073000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Level 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Level 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Level 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Level 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 consecutive sample must agree (comparator output is simply sampled).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The comparator output (CMPO) is not available on the associated CMPO output pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The comparator output (CMPO) is available on the associated CMPO output pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set CMPO to equal COUT (filtered comparator output).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set CMPO to equal COUTA (unfiltered comparator output).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Comparator INVERT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPR</name>
|
|
<description>CMP Filter Period Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT_PER</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>CMP Status and Control Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Falling edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rising edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMELB</name>
|
|
<description>Stop Mode Edge/Level Interrupt Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACCR</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vin1 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vin2 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUXCR</name>
|
|
<description>MUX Control Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input MUX Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input MUX Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>MMUX Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>PMUX Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP1</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<groupName>CMP</groupName>
|
|
<prependToName>CMP1_</prependToName>
|
|
<baseAddress>0x40073008</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP1</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Level 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Level 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Level 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Level 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 consecutive sample must agree (comparator output is simply sampled).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The comparator output (CMPO) is not available on the associated CMPO output pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The comparator output (CMPO) is available on the associated CMPO output pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set CMPO to equal COUT (filtered comparator output).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set CMPO to equal COUTA (unfiltered comparator output).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Comparator INVERT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPR</name>
|
|
<description>CMP Filter Period Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT_PER</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>CMP Status and Control Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Falling edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rising edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMELB</name>
|
|
<description>Stop Mode Edge/Level Interrupt Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACCR</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vin1 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vin2 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUXCR</name>
|
|
<description>MUX Control Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input MUX Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input MUX Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>MMUX Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>PMUX Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP2</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<groupName>CMP</groupName>
|
|
<prependToName>CMP2_</prependToName>
|
|
<baseAddress>0x40073010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP2</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Level 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Level 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Level 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Level 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 consecutive sample must agree (comparator output is simply sampled).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The comparator output (CMPO) is not available on the associated CMPO output pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The comparator output (CMPO) is available on the associated CMPO output pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set CMPO to equal COUT (filtered comparator output).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set CMPO to equal COUTA (unfiltered comparator output).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Comparator INVERT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPR</name>
|
|
<description>CMP Filter Period Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT_PER</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>CMP Status and Control Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Falling edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rising edge on COUT has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMELB</name>
|
|
<description>Stop Mode Edge/Level Interrupt Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACCR</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vin1 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vin2 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUXCR</name>
|
|
<description>MUX Control Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input MUX Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input MUX Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>MMUX Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>PMUX Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PMUX is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PMUX is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VREF</name>
|
|
<description>Voltage Reference</description>
|
|
<prependToName>VREF_</prependToName>
|
|
<baseAddress>0x40074000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TRM</name>
|
|
<description>VREF Trim Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>Trim bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000</name>
|
|
<description>Min</description>
|
|
<value>#000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111111</name>
|
|
<description>Max</description>
|
|
<value>#111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>VREF Status and Control Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE_LV</name>
|
|
<description>Buffer Mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bandgap on only, for stabilization and startup</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Tight-regulation buffer enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFST</name>
|
|
<description>Internal Voltage Reference has settled</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The bandgap is disabled or not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The bandgap is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGEN</name>
|
|
<description>Regulator enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal 1.75 V regulator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal 1.75 V regulator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>Internal Voltage Reference enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LLWU</name>
|
|
<description>Low-leakage wake-up module</description>
|
|
<prependToName>LLWU_</prependToName>
|
|
<baseAddress>0x4007C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x9</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LLW</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PE1</name>
|
|
<description>LLWU Pin Enable 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUPE0</name>
|
|
<description>Wakeup Pin Enable for LLWU_P0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE1</name>
|
|
<description>Wakeup Pin Enable for LLWU_P1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE2</name>
|
|
<description>Wakeup Pin Enable for LLWU_P2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE3</name>
|
|
<description>Wakeup Pin Enable for LLWU_P3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE2</name>
|
|
<description>LLWU Pin Enable 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUPE4</name>
|
|
<description>Wakeup Pin Enable for LLWU_P4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE5</name>
|
|
<description>Wakeup Pin Enable for LLWU_P5</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE6</name>
|
|
<description>Wakeup Pin Enable for LLWU_P6</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE7</name>
|
|
<description>Wakeup Pin Enable for LLWU_P7</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE3</name>
|
|
<description>LLWU Pin Enable 3 Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUPE8</name>
|
|
<description>Wakeup Pin Enable for LLWU_P8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE9</name>
|
|
<description>Wakeup Pin Enable for LLWU_P9</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE10</name>
|
|
<description>Wakeup Pin Enable for LLWU_P10</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE11</name>
|
|
<description>Wakeup Pin Enable for LLWU_P11</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE4</name>
|
|
<description>LLWU Pin Enable 4 Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUPE12</name>
|
|
<description>Wakeup Pin Enable for LLWU_P12</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE13</name>
|
|
<description>Wakeup Pin Enable for LLWU_P13</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE14</name>
|
|
<description>Wakeup Pin Enable for LLWU_P14</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE15</name>
|
|
<description>Wakeup Pin Enable for LLWU_P15</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External input pin disabled as wakeup input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External input pin enabled with rising edge detection</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External input pin enabled with falling edge detection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External input pin enabled with any change detection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ME</name>
|
|
<description>LLWU Module Enable Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUME0</name>
|
|
<description>Wakeup Module Enable for Module 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME1</name>
|
|
<description>Wakeup Module Enable for Module 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME2</name>
|
|
<description>Wakeup Module Enable for Module 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME3</name>
|
|
<description>Wakeup Module Enable for Module 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME4</name>
|
|
<description>Wakeup Module Enable for Module 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME5</name>
|
|
<description>Wakeup Module Enable for Module 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME6</name>
|
|
<description>Wakeup Module Enable for Module 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUME7</name>
|
|
<description>Wakeup Module Enable for Module 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal module flag not used as wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal module flag used as wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F1</name>
|
|
<description>LLWU Flag 1 Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUF0</name>
|
|
<description>Wakeup Flag for LLWU_P0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P0 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P0 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF1</name>
|
|
<description>Wakeup Flag for LLWU_P1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P1 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P1 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF2</name>
|
|
<description>Wakeup Flag for LLWU_P2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P2 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P2 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF3</name>
|
|
<description>Wakeup Flag for LLWU_P3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P3 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P3 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF4</name>
|
|
<description>Wakeup Flag for LLWU_P4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P4 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P4 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF5</name>
|
|
<description>Wakeup Flag for LLWU_P5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P5 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P5 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF6</name>
|
|
<description>Wakeup Flag for LLWU_P6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P6 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P6 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF7</name>
|
|
<description>Wakeup Flag for LLWU_P7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P7 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P7 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F2</name>
|
|
<description>LLWU Flag 2 Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUF8</name>
|
|
<description>Wakeup Flag for LLWU_P8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P8 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P8 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF9</name>
|
|
<description>Wakeup Flag for LLWU_P9</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P9 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P9 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF10</name>
|
|
<description>Wakeup Flag for LLWU_P10</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P10 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P10 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF11</name>
|
|
<description>Wakeup Flag for LLWU_P11</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P11 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P11 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF12</name>
|
|
<description>Wakeup Flag for LLWU_P12</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P12 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P12 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF13</name>
|
|
<description>Wakeup Flag for LLWU_P13</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P13 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P13 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF14</name>
|
|
<description>Wakeup Flag for LLWU_P14</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P14 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P14 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF15</name>
|
|
<description>Wakeup Flag for LLWU_P15</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLWU_P15 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLWU_P15 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F3</name>
|
|
<description>LLWU Flag 3 Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWUF0</name>
|
|
<description>Wakeup flag for module 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 0 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 0 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF1</name>
|
|
<description>Wakeup flag for module 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 1 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 1 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF2</name>
|
|
<description>Wakeup flag for module 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 2 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 2 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF3</name>
|
|
<description>Wakeup flag for module 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 3 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 3 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF4</name>
|
|
<description>Wakeup flag for module 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 4 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 4 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF5</name>
|
|
<description>Wakeup flag for module 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 5 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 5 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF6</name>
|
|
<description>Wakeup flag for module 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 6 input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 6 input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MWUF7</name>
|
|
<description>Wakeup flag for module 7 (Error Detect)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module 7 (Error Detect) input was not a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module 7 (Error Detect) input was a source of wakeup from LLS or VLLS mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>LLWU Control and Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTR</name>
|
|
<description>Digital Filter on RESET Pin</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Filter not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Filter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTEP</name>
|
|
<description>Digital Filter on External Pin</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Filter not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Filter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKISO</name>
|
|
<description>Acknowledge Isolation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripherals and I/O pads are in normal run state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Certain peripherals and I/O pads are in an isolated and latched state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<description>Mode Controller</description>
|
|
<prependToName>PMC_</prependToName>
|
|
<baseAddress>0x4007D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LVD_LVW</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>LVDSC1</name>
|
|
<description>Low Voltage Detect Status and Control 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDV</name>
|
|
<description>Low-Voltage Detect Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low trip point selected (VLVD = VLVDL)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>High trip point selected (VLVD = VLVDH)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDRE</name>
|
|
<description>Low-Voltage Detect Reset Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LVDF does not generate hardware resets</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force an MCU reset when LVDF = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDIE</name>
|
|
<description>Low-Voltage Detect Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVDF = 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDACK</name>
|
|
<description>Low-Voltage Detect Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDF</name>
|
|
<description>Low-Voltage Detect Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LVDSC2</name>
|
|
<description>Low Voltage Detect Status and Control 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVWV</name>
|
|
<description>Low-Voltage Warning Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low trip point selected (VLVW = VLVW1H/L)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mid 1 trip point selected (VLVW = VLVW2H/L)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mid 2 trip point selected (VLVW = VLVW3H/L)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High trip point selected (VLVW = VLVW4H/L)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWIE</name>
|
|
<description>Low-Voltage Warning Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVWF = 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWACK</name>
|
|
<description>Low-Voltage Warning Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVWF</name>
|
|
<description>Low-Voltage Warning Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage warning event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage warning event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGSC</name>
|
|
<description>Regulator Status and Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BGBE</name>
|
|
<description>Bandgap Buffer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bandgap buffer not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bandgap buffer enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGONS</name>
|
|
<description>Regulator in Run Regulation Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Regulator is in stop regulation or in transition to/from it</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Regulator is in run regulation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLPRS</name>
|
|
<description>Very Low Power Run Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MCU is not in VLPR mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MCU is in VLPR mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRAMPO</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No effect</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MC</name>
|
|
<description>Mode Controller</description>
|
|
<prependToName>MC_</prependToName>
|
|
<baseAddress>0x4007E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SRSH</name>
|
|
<description>System Reset Status Register High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>JTAG</name>
|
|
<description>JTAG generated reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by JTAG</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by JTAG</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>Core Lock-up</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by core LOCKUP event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by core LOCKUP event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>Software</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRSL</name>
|
|
<description>System Reset Status Register Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x82</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Low-leakage wakeup reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by LLWU module wakeup source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by LLWU module wakeup source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD</name>
|
|
<description>Low-voltage detect reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by LVD trip or POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by LVD trip or POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Loss-of-clock reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of external clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COP</name>
|
|
<description>Computer Operating Properly (COP) Watchdog</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by COP timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by COP timeout</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>External reset pin</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by external reset pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by external reset pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power-on reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMPROT</name>
|
|
<description>Power Mode Protection Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVLLS1</name>
|
|
<description>Allow very low leakage stop 1 mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLLS1 is not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLLS1 is allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVLLS2</name>
|
|
<description>Allow very low leakage stop 2 mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLLS2 is not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLLS2 is allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVLLS3</name>
|
|
<description>Allow Very Low Leakage Stop 3 Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLLS3 is not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLLS3 is allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALLS</name>
|
|
<description>Allow low leakage stop mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LLS is not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LLS is allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVLP</name>
|
|
<description>Allow very low power modes</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLPR, VLPW, and VLPS are not allowed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLPR, VLPW, and VLPS are allowed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMCTRL</name>
|
|
<description>Power Mode Control Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPLLSM</name>
|
|
<description>Low Power, Low Leakage Stop Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Normal stop</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Very low power stop (VLPS)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Low leakage stop (LLS)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Very low leakage stop 3 (VLLS3)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Very low leakage stop 2 (VLLS2)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Very low leakage stop 1 (VLLS1)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNM</name>
|
|
<description>Run Mode Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal run mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Very low power run mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPWUI</name>
|
|
<description>Low Power Wake Up on Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The voltage regulator remains in stop regulation on an interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The voltage regulator exits stop regulation on an interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RNG</name>
|
|
<description>Random Number Generator</description>
|
|
<prependToName>RNG_</prependToName>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RNG</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VER</name>
|
|
<description>RNGB Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10000280</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor version number.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major version number.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Random number generator type</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>RNGA</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>RNGB (This is the type used in this module)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>RNGC</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>RNGB Command Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Self test.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in self test mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Self test mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GS</name>
|
|
<description>Generate seed.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in seed generation mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate seed mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CI</name>
|
|
<description>Clear interrupt.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Clear error.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not clear errors and interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear errors and interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Software reset.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not perform a software reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>RNGB Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUFMOD</name>
|
|
<description>FIFO underflow response mode.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Return all zeros and set RNG_ESR[FUFE]</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Return all zeros and set RNG_ESR[FUFE]</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Generate bus transfer error</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Generate interrupt and return all zeros (Overrides RNG_CR[MASKERR])</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AR</name>
|
|
<description>Auto-reseed.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not enable automatic reseeding.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable automatic reseeding.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASKDONE</name>
|
|
<description>Mask done interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mask applied.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask applied.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASKERR</name>
|
|
<description>Mask error interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mask applied.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask applied to the error interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>RNGB Status Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x500D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not busy.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLP</name>
|
|
<description>Sleep.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RNGB is not in sleep mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RNGB is in sleep mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Reseed needed.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RNGB does not need to be reseeded.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RNGB needs to be reseeded.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDN</name>
|
|
<description>Self test done.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Self test not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Completed a self test since the last reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDN</name>
|
|
<description>Seed done.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Seed generation process not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Completed seed generation since the last reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSDN</name>
|
|
<description>New seed done.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_LVL</name>
|
|
<description>FIFO level.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_SIZE</name>
|
|
<description>FIFO size.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ST_PF</name>
|
|
<description>Self Test Pass Fail.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pass.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fail.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATPF</name>
|
|
<description>Statistics test pass fail.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pass.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fail.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ESR</name>
|
|
<description>RNGB Error Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFE</name>
|
|
<description>Linear feedback shift register (LFSR) error.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LFSRs are working properly.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LFSR failure has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCE</name>
|
|
<description>Oscillator error.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RNG oscillator is working properly.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Problem detected with the RNG oscillator.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STE</name>
|
|
<description>Self test error.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RNGB has not failed self test.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RNGB has failed self test.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SATE</name>
|
|
<description>Statistical test error.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RNGB has not failed the statistical tests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RNGB has failed the statistical tests during initialization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FUFE</name>
|
|
<description>FIFO underflow error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO underflow has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO underflow has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT</name>
|
|
<description>RNGB Output FIFO</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RANDOUT</name>
|
|
<description>Random Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SDHC</name>
|
|
<description>Secured Digital Host Controller</description>
|
|
<prependToName>SDHC_</prependToName>
|
|
<baseAddress>0x400B1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SDHC</name>
|
|
<value>80</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DSADDR</name>
|
|
<description>DMA System Address Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSADDR</name>
|
|
<description>DMA System Address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BLKATTR</name>
|
|
<description>Block Attributes Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BLKSIZE</name>
|
|
<description>Transfer Block Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1 Byte</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 Bytes</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>3 Bytes</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 Bytes</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111111111</name>
|
|
<description>511 Bytes</description>
|
|
<value>#111111111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000000000</name>
|
|
<description>512 Bytes</description>
|
|
<value>#1000000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100000000000</name>
|
|
<description>2048 Bytes</description>
|
|
<value>#100000000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000000000000</name>
|
|
<description>4096 Bytes</description>
|
|
<value>#1000000000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKCNT</name>
|
|
<description>Blocks Count For Current Transfer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop count</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1 block</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 blocks</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111111111111111</name>
|
|
<description>65535 blocks</description>
|
|
<value>#1111111111111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDARG</name>
|
|
<description>Command Argument Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDARG</name>
|
|
<description>Command Argument</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XFERTYP</name>
|
|
<description>Transfer Type Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCEN</name>
|
|
<description>Block Count Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12EN</name>
|
|
<description>Auto CMD12 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTDSEL</name>
|
|
<description>Data Transfer Direction Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write (host to card)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read (card to host)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBSEL</name>
|
|
<description>Multi/Single Block Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single block</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Multiple blocks</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTYP</name>
|
|
<description>Response Type Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Response length 136</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Response length 48</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Response length 48, check busy after response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCCEN</name>
|
|
<description>Command CRC Check Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CICEN</name>
|
|
<description>Command Index Check Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPSEL</name>
|
|
<description>Data Present Select</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDTYP</name>
|
|
<description>Command Type</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal other commands</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Suspend CMD52 for writing bus suspend in CCCR</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Resume CMD52 for writing function select in CCCR</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Abort CMD12, CMD52 for writing I/O abort in CCCR</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDINX</name>
|
|
<description>Command Index</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDRSP0</name>
|
|
<description>Command Response 0</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRSP0</name>
|
|
<description>Command Response 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDRSP1</name>
|
|
<description>Command Response 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRSP1</name>
|
|
<description>Command Response 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDRSP2</name>
|
|
<description>Command Response 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRSP2</name>
|
|
<description>Command Response 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDRSP3</name>
|
|
<description>Command Response 3</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRSP3</name>
|
|
<description>Command Response 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATPORT</name>
|
|
<description>Buffer Data Port Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATCONT</name>
|
|
<description>Data Content</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRSSTAT</name>
|
|
<description>Present State Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CIHB</name>
|
|
<description>Command Inhibit (CMD)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Can issue command using only CMD line</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cannot issue command</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDIHB</name>
|
|
<description>Command Inhibit (DAT)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Can issue command which uses the DAT line</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cannot issue command which uses the DAT line</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLA</name>
|
|
<description>Data Line Active</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAT line inactive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAT line active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDSTB</name>
|
|
<description>SD Clock Stable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock is changing frequency and not stable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock is stable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPGOFF</name>
|
|
<description>Bus Clock Gated Off Internally</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock is active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock is gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCKOFF</name>
|
|
<description>System Clock Gated Off Internally</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System clock is active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System clock is gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEROFF</name>
|
|
<description>SDHC clock Gated Off Internally</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDHC clock is active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDHC clock is gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDOFF</name>
|
|
<description>SD Clock Gated Off Internally</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD clock is active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD clock is gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTA</name>
|
|
<description>Write Transfer Active</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No valid data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transferring data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTA</name>
|
|
<description>Read Transfer Active</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No valid data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transferring data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWEN</name>
|
|
<description>Buffer Write Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write disable, the buffer can hold valid data less than the write watermark level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write enable, the buffer can hold valid data greater than the write watermark level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BREN</name>
|
|
<description>Buffer Read Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read disable, valid data less than the watermark level exist in the buffer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read enable, valid data greater than the watermark level exist in the buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINS</name>
|
|
<description>Card Inserted</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Power on reset or no card</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card inserted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLSL</name>
|
|
<description>CMD Line Signal Level</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DLSL</name>
|
|
<description>DAT Line Signal Level</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PROCTL</name>
|
|
<description>Protocol Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCTL</name>
|
|
<description>LED Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LED off</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LED on</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTW</name>
|
|
<description>Data Transfer Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1-bit mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>4-bit mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>8-bit mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>D3CD</name>
|
|
<description>DAT3 as Card Detection Pin</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAT3 does not monitor card Insertion</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAT3 as card detection pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMODE</name>
|
|
<description>Endian Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Big endian mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Half word big endian mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Little endian mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDTL</name>
|
|
<description>Card Detect Test Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card detect test level is 0, no card inserted</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card detect test level is 1, card inserted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDSS</name>
|
|
<description>Card Detect Signal Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card detection level is selected (for normal purpose)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card detection test level is selected (for test purpose)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAS</name>
|
|
<description>DMA Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No DMA or simple DMA is selected</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ADMA1 is selected</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ADMA2 is selected</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SABGREQ</name>
|
|
<description>Stop At Block Gap Request</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CREQ</name>
|
|
<description>Continue Request</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Restart</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWCTL</name>
|
|
<description>Read Wait Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable read wait control, and stop SD clock at block gap when SABGREQ bit is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IABG</name>
|
|
<description>Interrupt At Block Gap</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WECINT</name>
|
|
<description>Wakeup Event Enable On Card Interrupt</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WECINS</name>
|
|
<description>Wakeup Event Enable On SD Card Insertion</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WECRM</name>
|
|
<description>Wakeup Event Enable On SD Card Removal</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSCTL</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPGEN</name>
|
|
<description>IPG Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock will be internally gated off</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock will not be automatically gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCKEN</name>
|
|
<description>System Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System clock will be internally gated off</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System clock will not be automatically gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEREN</name>
|
|
<description>Peripheral Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDHC clock will be internally gated off</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDHC clock will not be automatically gated off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCLKEN</name>
|
|
<description>SD Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DVS</name>
|
|
<description>Divisor</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divisor by 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divisor by 2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divisor by 15</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divisor by 16</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCLKFS</name>
|
|
<description>SDCLK Frequency Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Base clock divided by 2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Base clock divided by 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Base clock divided by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Base clock divided by 16</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Base clock divided by 32</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100000</name>
|
|
<description>Base clock divided by 64</description>
|
|
<value>#100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000000</name>
|
|
<description>Base clock divided by 128</description>
|
|
<value>#1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000000</name>
|
|
<description>Base clock divided by 256</description>
|
|
<value>#10000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTOCV</name>
|
|
<description>Data Timeout Counter Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>SDCLK x 213</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>SDCLK x 214</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>SDCLK x 227</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Software Reset For ALL</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No reset</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Software Reset For CMD Line</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No reset</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTD</name>
|
|
<description>Software Reset For DAT Line</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No reset</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITA</name>
|
|
<description>Initialization Active</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSTAT</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Command Complete</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command not complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transfer Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer not complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGE</name>
|
|
<description>Block Gap Event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No block gap event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transaction stopped at block gap</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DINT</name>
|
|
<description>DMA Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No DMA Interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA Interrupt is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWR</name>
|
|
<description>Buffer Write Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not ready to write buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ready to write buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRR</name>
|
|
<description>Buffer Read Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not ready to read buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ready to read buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINS</name>
|
|
<description>Card Insertion</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card state unstable or removed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card inserted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRM</name>
|
|
<description>Card Removal</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card state unstable or inserted</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card removed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Card Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Card Interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate Card Interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTOE</name>
|
|
<description>Command Timeout Error</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCE</name>
|
|
<description>Command CRC Error</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC Error Generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEBE</name>
|
|
<description>Command End Bit Error</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End Bit Error Generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIE</name>
|
|
<description>Command Index Error</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Data Timeout Error</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCE</name>
|
|
<description>Data CRC Error</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBE</name>
|
|
<description>Data End Bit Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12E</name>
|
|
<description>Auto CMD12 Error</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAE</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSTATEN</name>
|
|
<description>Interrupt Status Enable Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x117F013F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Command Complete Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCSEN</name>
|
|
<description>Transfer Complete Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGESEN</name>
|
|
<description>Block Gap Event Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DINTSEN</name>
|
|
<description>DMA Interrupt Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRSEN</name>
|
|
<description>Buffer Write Ready Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRRSEN</name>
|
|
<description>Buffer Read Ready Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINSEN</name>
|
|
<description>Card Insertion Status Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRMSEN</name>
|
|
<description>Card Removal Status Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINTSEN</name>
|
|
<description>Card Interrupt Status Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTOESEN</name>
|
|
<description>Command Timeout Error Status Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCESEN</name>
|
|
<description>Command CRC Error Status Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEBESEN</name>
|
|
<description>Command End Bit Error Status Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIESEN</name>
|
|
<description>Command Index Error Status Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTOESEN</name>
|
|
<description>Data Timeout Error Status Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCESEN</name>
|
|
<description>Data CRC Error Status Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBESEN</name>
|
|
<description>Data End Bit Error Status Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12ESEN</name>
|
|
<description>Auto CMD12 Error Status Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAESEN</name>
|
|
<description>DMA Error Status Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSIGEN</name>
|
|
<description>Interrupt Signal Enable Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Command Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIEN</name>
|
|
<description>Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGEIEN</name>
|
|
<description>Block Gap Event Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DINTIEN</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRIEN</name>
|
|
<description>Buffer Write Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRRIEN</name>
|
|
<description>Buffer Read Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINSIEN</name>
|
|
<description>Card Insertion Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRMIEN</name>
|
|
<description>Card Removal Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINTIEN</name>
|
|
<description>Card Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTOEIEN</name>
|
|
<description>Command Timeout Error Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCEIEN</name>
|
|
<description>Command CRC Error Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEBEIEN</name>
|
|
<description>Command End Bit Error Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIEIEN</name>
|
|
<description>Command Index Error Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTOEIEN</name>
|
|
<description>Data Timeout Error Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCEIEN</name>
|
|
<description>Data CRC Error Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBEIEN</name>
|
|
<description>Data End Bit Error Interrupt Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12EIEN</name>
|
|
<description>Auto CMD12 Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEIEN</name>
|
|
<description>DMA Error Interrupt Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AC12ERR</name>
|
|
<description>Auto CMD12 Error Status Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC12NE</name>
|
|
<description>Auto CMD12 Not Executed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Executed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Not executed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12TOE</name>
|
|
<description>Auto CMD12 Timeout Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12EBE</name>
|
|
<description>Auto CMD12 End Bit Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End bit error generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12CE</name>
|
|
<description>Auto CMD12 CRC Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No CRC error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC Error met in auto CMD12 Response</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AC12IE</name>
|
|
<description>Auto CMD12 Index Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error, the CMD index in response is not CMD12</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNIBAC12E</name>
|
|
<description>Command Not Issued By Auto CMD12 Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Not issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HTCAPBLT</name>
|
|
<description>Host Controller Capabilities</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x7F30000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MBL</name>
|
|
<description>Max Block Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>512 bytes</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1024 bytes</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2048 bytes</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4096 bytes</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMAS</name>
|
|
<description>ADMA Support</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Advanced DMA not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Advanced DMA supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSS</name>
|
|
<description>High Speed Support</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High speed not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High speed supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAS</name>
|
|
<description>DMA Support</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRS</name>
|
|
<description>Suspend/Resume Support</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VS33</name>
|
|
<description>Voltage Support 3.3 V</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>3.3 V not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>3.3 V supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VS30</name>
|
|
<description>Voltage Support 3.0 V</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>3.0 V not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>3.0 V supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VS18</name>
|
|
<description>Voltage Support 1.8 V</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>1.8 V not supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1.8 V supported</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WML</name>
|
|
<description>Watermark Level Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDWML</name>
|
|
<description>Read Watermark Level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRWML</name>
|
|
<description>Write Watermark Level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRBRSTLEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEVT</name>
|
|
<description>Force Event Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC12NE</name>
|
|
<description>Force Event Auto Command 12 Not Executed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AC12TOE</name>
|
|
<description>Force Event Auto Command 12 Time Out Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AC12CE</name>
|
|
<description>Force Event Auto Command 12 CRC Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AC12EBE</name>
|
|
<description>Force Event Auto Command 12 End Bit Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AC12IE</name>
|
|
<description>Force Event Auto Command 12 Index Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNIBAC12E</name>
|
|
<description>Force Event Command Not Executed By Auto Command 12 Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTOE</name>
|
|
<description>Force Event Command Time Out Error</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCE</name>
|
|
<description>Force Event Command CRC Error</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CEBE</name>
|
|
<description>Force Event Command End Bit Error</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CIE</name>
|
|
<description>Force Event Command Index Error</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOE</name>
|
|
<description>Force Event Data Time Out Error</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCE</name>
|
|
<description>Force Event Data CRC Error</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBE</name>
|
|
<description>Force Event Data End Bit Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AC12E</name>
|
|
<description>Force Event Auto Command 12 Error</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAE</name>
|
|
<description>Force Event DMA Error</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Force Event Card Interrupt</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADMAES</name>
|
|
<description>ADMA Error Status Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADMAES</name>
|
|
<description>ADMA Error State (when ADMA Error is occurred.)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADMALME</name>
|
|
<description>ADMA Length Mismatch Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMADCE</name>
|
|
<description>ADMA Descritor Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSADDR</name>
|
|
<description>ADMA System Address Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADSADDR</name>
|
|
<description>ADMA System Address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VENDOR</name>
|
|
<description>Vendor Specific Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTDMAEN</name>
|
|
<description>External DMA Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>In any scenario, SDHC does not send out external DMA request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When internal DMA is not active, the external DMA request will be sent out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXBLKNU</name>
|
|
<description>Exact block number block read enable for SDIO CMD53</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>none exact block read.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Exact block read for SDIO CMD53.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTSTVAL</name>
|
|
<description>Internal State Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCBOOT</name>
|
|
<description>MMC Boot Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTOCVACK</name>
|
|
<description>Boot ACK time out counter value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>SDCLK x 2^8</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>SDCLK x 2^9</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>SDCLK x 2^10</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>SDCLK x 2^11</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>SDCLK x 2^12</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>SDCLK x 2^13</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>SDCLK x 2^14</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>SDCLK x 2^15</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>SDCLK x 2^22</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTACK</name>
|
|
<description>Boot ack mode select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No ack</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ack</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTMODE</name>
|
|
<description>Boot mode select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal boot</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternative boot</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTEN</name>
|
|
<description>Boot mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast boot disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast boot enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSABGEN</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOTBLKCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOSTVER</name>
|
|
<description>Host Controller Version</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1201</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVN</name>
|
|
<description>Specification Version Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD host specification version 2.0, supports test event register and ADMA.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VVN</name>
|
|
<description>Vendor Version Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Freescale SDHC version 1.0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Freescale SDHC version 2.0</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Freescale SDHC version 2.1</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Freescale SDHC version 2.2</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET</name>
|
|
<description>Ethernet MAC-NET Core</description>
|
|
<prependToName>ENET_</prependToName>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x624</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ENET_1588_Timer</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ENET_Transmit</name>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ENET_Receive</name>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ENET_Error</name>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>EIR</name>
|
|
<description>Interrupt Event Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS_TIMER</name>
|
|
<description>Timestamp timer</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS_AVAIL</name>
|
|
<description>Transmit timestamp available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Node wake-up request indication</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLR</name>
|
|
<description>Payload receive error</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UN</name>
|
|
<description>Transmit FIFO underrun</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RL</name>
|
|
<description>Collision Retry Limit.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LC</name>
|
|
<description>Late Collision</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EBERR</name>
|
|
<description>Ethernet Bus Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MII</name>
|
|
<description>MII Interrupt.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXB</name>
|
|
<description>Receive Buffer Interrupt.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXF</name>
|
|
<description>Receive Frame Interrupt</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXB</name>
|
|
<description>Transmit Buffer Interrupt</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXF</name>
|
|
<description>Transmit Frame Interrupt</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GRA</name>
|
|
<description>Graceful Stop Complete</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BABT</name>
|
|
<description>Babbling Transmit Error</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BABR</name>
|
|
<description>Babbling Receive Error</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EIMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS_TIMER</name>
|
|
<description>TS_TIMER interrupt mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS_AVAIL</name>
|
|
<description>TS_AVAIL interrupt mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>WAKEUP interrupt mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLR</name>
|
|
<description>PLR interrupt mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UN</name>
|
|
<description>UN interrupt mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RL</name>
|
|
<description>RL interrupt mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LC</name>
|
|
<description>LC interrupt mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EBERR</name>
|
|
<description>EBERR interrupt mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MII</name>
|
|
<description>MII interrupt mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXB</name>
|
|
<description>RXB interrupt mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXF</name>
|
|
<description>RXF interrupt mask</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXB</name>
|
|
<description>TXB interrupt mask</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding interrupt source is masked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding interrupt source is not masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXF</name>
|
|
<description>TXF interrupt mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding interrupt source is masked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding interrupt source is not masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRA</name>
|
|
<description>GRA interrupt mask</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding interrupt source is masked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding interrupt source is not masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BABT</name>
|
|
<description>BABT interrupt mask</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding interrupt source is masked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding interrupt source is not masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BABR</name>
|
|
<description>BABR interrupt mask</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding interrupt source is masked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding interrupt source is not masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDAR</name>
|
|
<description>Receive Descriptor Active Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDAR</name>
|
|
<description>Receive descriptor active</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDAR</name>
|
|
<description>Transmit Descriptor Active Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDAR</name>
|
|
<description>Transmit descriptor active</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<description>Ethernet Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Ethernet MAC reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETHEREN</name>
|
|
<description>Ethernet enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MAC is enabled, and reception and transmission are possible.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAGICEN</name>
|
|
<description>Magic packet detection enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Magic detection logic disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP</name>
|
|
<description>Sleep mode enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operating mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sleep mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN1588</name>
|
|
<description>EN1588 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy FEC buffer descriptors and functions enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced frame time-stamping functions enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MAC continues operation in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MAC enters hardware freeze mode when the processor is in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPEN</name>
|
|
<description>STOPEN Signal Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFR</name>
|
|
<description>MII Management Frame Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Management frame data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TA</name>
|
|
<description>Turn around</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Register address</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>PHY address</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OP</name>
|
|
<description>Operation code</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Write frame operation, but not MII compliant.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Write frame operation for a valid MII management frame.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Read frame operation for a valid MII management frame.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Read frame operation, but not MII compliant.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start of frame delimiter</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSCR</name>
|
|
<description>MII Speed Control Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MII_SPEED</name>
|
|
<description>MII speed</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS_PRE</name>
|
|
<description>Disable preamble</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Preamble enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Preamble (32 ones) is not prepended to the MII management frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOLDTIME</name>
|
|
<description>Holdtime on MDIO output</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 internal module clock cycle</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 internal module clock cycles</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 internal module clock cycles</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 internal module clock cycles</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIBC</name>
|
|
<description>MIB Control Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MIB_CLEAR</name>
|
|
<description>MIB clear</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MIB_IDLE</name>
|
|
<description>MIB idle</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MIB_DIS</name>
|
|
<description>Disable MIB logic</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>Receive Control Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5EE0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOOP</name>
|
|
<description>Internal loopback</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loopback disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. .</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRT</name>
|
|
<description>Disable receive on transmit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable reception of frames while transmitting (normally used for half duplex mode).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MII_MODE</name>
|
|
<description>Media independent interface mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MII or RMII mode, as indicated by the RMII_MODE bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROM</name>
|
|
<description>Promiscuous mode. All frames are accepted regardless of address matching.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC_REJ</name>
|
|
<description>Broadcast frame reject</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FCE</name>
|
|
<description>Flow control enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMII_MODE</name>
|
|
<description>RMII mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MAC configured for MII mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MAC configured for RMII operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMII_10T</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>100 Mbps operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10 Mbps operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PADEN</name>
|
|
<description>Enable frame padding remove on receive</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No padding is removed on receive by the MAC.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Padding is removed from received frames.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PAUFWD</name>
|
|
<description>Terminate/forward pause frames.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pause frames are terminated and discarded in the MAC.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pause frames are forwarded to the user application.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCFWD</name>
|
|
<description>Terminate/forward received CRC</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The CRC field of received frames is transmitted to the user application.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CRC field is stripped from the frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFEN</name>
|
|
<description>MAC control frame enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MAC control frames with any opcode other than 0x0001 are accepted and forwarded to the client interface.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAX_FL</name>
|
|
<description>Maximum frame length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NLC</name>
|
|
<description>Payload length check disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The payload length check is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRS</name>
|
|
<description>Graceful receive stopped</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Control Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTS</name>
|
|
<description>Graceful transmit stop</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDEN</name>
|
|
<description>Full duplex enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFC_PAUSE</name>
|
|
<description>Transmit frame control pause</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No PAUSE frame transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The MAC stops transmission of data frames after the current transmission is complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFC_PAUSE</name>
|
|
<description>Receive frame control pause</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDSEL</name>
|
|
<description>Source MAC address select on transmit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Node MAC address programmed on PADDR1/2 registers.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDINS</name>
|
|
<description>Set MAC address on transmit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The source MAC address is not modified by the MAC.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCFWD</name>
|
|
<description>Forward frame from application with CRC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TxBD[TC] controls whether the frame has a CRC from the application</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The transmitter does not append any CRC to transmitted frames as it is expecting a frame with CRC from the application.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PALR</name>
|
|
<description>Physical Address Lower Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR1</name>
|
|
<description>Pause address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAUR</name>
|
|
<description>Physical Address Upper Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8808</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Type field in PAUSE frames.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PADDR2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPD</name>
|
|
<description>Opcode/Pause Duration Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PAUSE_DUR</name>
|
|
<description>Pause duration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPCODE</name>
|
|
<description>Opcode field in PAUSE frames</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IAUR</name>
|
|
<description>Descriptor Individual Upper Address Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IADDR1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IALR</name>
|
|
<description>Descriptor Individual Lower Address Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IADDR2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAUR</name>
|
|
<description>Descriptor Group Upper Address Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GADDR1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GALR</name>
|
|
<description>Descriptor Group Lower Address Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GADDR2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFWR</name>
|
|
<description>Transmit FIFO Watermark Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFWR</name>
|
|
<description>Transmit FIFO write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000</name>
|
|
<description>64 bytes written</description>
|
|
<value>#000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000001</name>
|
|
<description>64 bytes written</description>
|
|
<value>#000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000010</name>
|
|
<description>128 bytes written</description>
|
|
<value>#000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000011</name>
|
|
<description>192 bytes written</description>
|
|
<value>#000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111111</name>
|
|
<description>4032 bytes written</description>
|
|
<value>#111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STRFWD</name>
|
|
<description>Store and forward enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled, the transmission start threshold is programmed in TFWR.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDSR</name>
|
|
<description>Receive Descriptor Ring Start Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R_DES_START</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDSR</name>
|
|
<description>Transmit Buffer Descriptor Ring Start Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>X_DES_START</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRBR</name>
|
|
<description>Maximum Receive Buffer Size Register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R_BUF_SIZE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSFL</name>
|
|
<description>Receive FIFO Section Full Threshold</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_SECTION_FULL</name>
|
|
<description>Value of receive FIFO section full threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSEM</name>
|
|
<description>Receive FIFO Section Empty Threshold</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_SECTION_EMPTY</name>
|
|
<description>Value of the receive FIFO section empty threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAEM</name>
|
|
<description>Receive FIFO Almost Empty Threshold</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_ALMOST_EMPTY</name>
|
|
<description>Value of the receive FIFO almost empty threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAFL</name>
|
|
<description>Receive FIFO Almost Full Threshold</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_ALMOST_FULL</name>
|
|
<description>Value of the receive FIFO almost full threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSEM</name>
|
|
<description>Transmit FIFO Section Empty Threshold</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_SECTION_EMPTY</name>
|
|
<description>Value of the transmit FIFO section empty threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAEM</name>
|
|
<description>Transmit FIFO Almost Empty Threshold</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_ALMOST_EMPTY</name>
|
|
<description>Value of transmit FIFO almost empty threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAFL</name>
|
|
<description>Transmit FIFO Almost Full Threshold</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_ALMOST_FULL</name>
|
|
<description>Value of the transmit FIFO almost full threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIPG</name>
|
|
<description>Transmit Inter-Packet Gap</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPG</name>
|
|
<description>Transmit inter-packet gap</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTRL</name>
|
|
<description>Frame Truncation Length</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRUNC_FL</name>
|
|
<description>Frame truncation length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TACC</name>
|
|
<description>Transmit Accelerator Function Configuration</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFT16</name>
|
|
<description>TX FIFO shift-16</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates to the transmit data FIFO, that the written frames contain two additional octets before the frame data. This means the actual frame starts at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPCHK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Checksum is not inserted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROCHK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Checksum not inserted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RACC</name>
|
|
<description>Receive Accelerator Function Configuration</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PADREM</name>
|
|
<description>Enable padding removal for short IP frames.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Padding not removed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Any bytes following the IP payload section of the frame are removed from the frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPDIS</name>
|
|
<description>Enable discard of frames with wrong IPv4 header checksum.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frames with wrong IPv4 header checksum are not discarded.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRODIS</name>
|
|
<description>Enable discard of frames with wrong protocol checksum</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frames with wrong checksum are not discarded.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LINEDIS</name>
|
|
<description>Enable discard of frames with MAC layer errors</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frames with errors are not discarded.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHIFT16</name>
|
|
<description>RX FIFO shift-16</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_DROP</name>
|
|
<description>Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable.</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_PACKETS</name>
|
|
<description>RMON Tx packet count (RMON_T_PACKETS)</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_BC_PKT</name>
|
|
<description>RMON Tx Broadcast Packets (RMON_T_BC_PKT)</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Broadcast packets</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_MC_PKT</name>
|
|
<description>RMON Tx Multicast Packets (RMON_T_MC_PKT)</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Multicast packets</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_CRC_ALIGN</name>
|
|
<description>RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN)</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packets with CRC/align error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_UNDERSIZE</name>
|
|
<description>RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE)</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_OVERSIZE</name>
|
|
<description>RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE)</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_FRAG</name>
|
|
<description>RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG)</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_JAB</name>
|
|
<description>RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB)</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_COL</name>
|
|
<description>RMON Tx collision count (RMON_T_COL)</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P64</name>
|
|
<description>RMON Tx 64 byte packets (RMON_T_P64)</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P65TO127</name>
|
|
<description>RMON Tx 65 to 127 byte packets (RMON_T_P65TO127)</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P128TO255</name>
|
|
<description>RMON Tx 128 to 255 byte packets (RMON_T_P128TO255)</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P256TO511</name>
|
|
<description>RMON Tx 256 to 511 byte packets (RMON_T_P256TO511)</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P512TO1023</name>
|
|
<description>RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023)</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P1024TO2047</name>
|
|
<description>RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047)</description>
|
|
<addressOffset>0x23C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_P_GTE2048</name>
|
|
<description>RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048)</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPKTS</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_T_OCTETS</name>
|
|
<description>RMON Tx Octets (RMON_T_OCTETS)</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXOCTS</name>
|
|
<description>Octet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_DROP</name>
|
|
<description>Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable.</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_FRAME_OK</name>
|
|
<description>Frames Transmitted OK (IEEE_T_FRAME_OK)</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_1COL</name>
|
|
<description>Frames Transmitted with Single Collision (IEEE_T_1COL)</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_MCOL</name>
|
|
<description>Frames Transmitted with Multiple Collisions (IEEE_T_MCOL)</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_DEF</name>
|
|
<description>Frames Transmitted after Deferral Delay (IEEE_T_DEF)</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_LCOL</name>
|
|
<description>Frames Transmitted with Late Collision (IEEE_T_LCOL)</description>
|
|
<addressOffset>0x25C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_EXCOL</name>
|
|
<description>Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL)</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_MACERR</name>
|
|
<description>Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR)</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_CSERR</name>
|
|
<description>Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR)</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_SQE</name>
|
|
<description>Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available.</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_FDXFC</name>
|
|
<description>Flow Control Pause frames transmitted (IEEE_T_FDXFC)</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_T_OCTETS_OK</name>
|
|
<description>Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields).</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Octet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_PACKETS</name>
|
|
<description>RMON Rx packet count (RMON_R_PACKETS)</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_BC_PKT</name>
|
|
<description>RMON Rx Broadcast Packets (RMON_R_BC_PKT)</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_MC_PKT</name>
|
|
<description>RMON Rx Multicast Packets (RMON_R_MC_PKT)</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_CRC_ALIGN</name>
|
|
<description>RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN)</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_UNDERSIZE</name>
|
|
<description>RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE)</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_OVERSIZE</name>
|
|
<description>RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE)</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_FRAG</name>
|
|
<description>RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG)</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_JAB</name>
|
|
<description>RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB)</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_RESVD_0</name>
|
|
<description>Reserved (RMON_R_RESVD_0)</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P64</name>
|
|
<description>RMON Rx 64 byte packets (RMON_R_P64)</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P65TO127</name>
|
|
<description>RMON Rx 65 to 127 byte packets (RMON_R_P65TO127)</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P128TO255</name>
|
|
<description>RMON Rx 128 to 255 byte packets (RMON_R_P128TO255)</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P256TO511</name>
|
|
<description>RMON Rx 256 to 511 byte packets (RMON_R_P256TO511)</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P512TO1023</name>
|
|
<description>RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023)</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P1024TO2047</name>
|
|
<description>RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047)</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_P_GTE2048</name>
|
|
<description>RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048)</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMON_R_OCTETS</name>
|
|
<description>RMON Rx Octets (RMON_R_OCTETS)</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Octet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_DROP</name>
|
|
<description>Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments.</description>
|
|
<addressOffset>0x2C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_FRAME_OK</name>
|
|
<description>Frames Received OK (IEEE_R_FRAME_OK)</description>
|
|
<addressOffset>0x2CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_CRC</name>
|
|
<description>Frames Received with CRC Error (IEEE_R_CRC)</description>
|
|
<addressOffset>0x2D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_ALIGN</name>
|
|
<description>Frames Received with Alignment Error (IEEE_R_ALIGN)</description>
|
|
<addressOffset>0x2D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_MACERR</name>
|
|
<description>Receive Fifo Overflow count (IEEE_R_MACERR)</description>
|
|
<addressOffset>0x2D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_FDXFC</name>
|
|
<description>Flow Control Pause frames received (IEEE_R_FDXFC)</description>
|
|
<addressOffset>0x2DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Pause frame count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEEE_R_OCTETS_OK</name>
|
|
<description>Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields).</description>
|
|
<addressOffset>0x2E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Octet count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCR</name>
|
|
<description>Timer Control Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The timer stops at the current value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The timer starts incrementing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFFEN</name>
|
|
<description>Enable one-shot offset event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The timer can be reset to zero when the given offset time is reached (offset event). The bit is cleared when the offset event is reached, so no further event occurs until the bit is set again. Set the timer offset value before setting this bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFFRST</name>
|
|
<description>Reset timer on offset event</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The timer is not affected and no action occurs (besides clearing OFFEN) when the offset is reached.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEREN</name>
|
|
<description>Enable periodical event</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. Set the timer period value before setting this bit. Not all devices contain the event signal output. See the Chip Configuration details.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINPER</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESTART</name>
|
|
<description>Reset timer</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timer value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current time is captured and can be read from the ATVR register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Enable timer slave mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The timer is active and all configuration bits in this register are relevant.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal timer is disabled and the externally provided timer value is used. All other bits, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATVR</name>
|
|
<description>Timer Value Register</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATIME</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATOFF</name>
|
|
<description>Timer Offset Register</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATPER</name>
|
|
<description>Timer Period Register</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3B9ACA00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATCOR</name>
|
|
<description>Timer Correction Register</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COR</name>
|
|
<description>Correction counter wrap-around value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATINC</name>
|
|
<description>Time-Stamping Clock Period Register</description>
|
|
<addressOffset>0x414</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INC</name>
|
|
<description>Clock period of the timestamping clock (ts_clk) in nanoseconds</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INC_CORR</name>
|
|
<description>Correction increment value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ATSTMP</name>
|
|
<description>Timestamp of Last Transmitted Frame</description>
|
|
<addressOffset>0x418</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TGSR</name>
|
|
<description>Timer Global Status Register</description>
|
|
<addressOffset>0x604</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TF0</name>
|
|
<description>Copy of Timer Flag for channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Flag for Channel 0 is clear</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Flag for Channel 0 is set</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TF1</name>
|
|
<description>Copy of Timer Flag for channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Flag for Channel 1 is clear</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Flag for Channel 1 is set</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TF2</name>
|
|
<description>Copy of Timer Flag for channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Flag for Channel 2 is clear</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Flag for Channel 2 is set</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TF3</name>
|
|
<description>Copy of Timer Flag for channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Flag for Channel 3 is clear</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Flag for Channel 3 is set</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TCSR%s</name>
|
|
<description>Timer Control Status Register</description>
|
|
<addressOffset>0x608</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Timer DMA Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMODE</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Timer Channel is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Timer Channel is configured for Input Capture on rising edge</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Timer Channel is configured for Input Capture on falling edge</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Timer Channel is configured for Input Capture on both edges</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Timer Channel is configured for Output Compare - software only</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Timer Channel is configured for Output Compare - toggle output on compare</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Timer Channel is configured for Output Compare - clear output on compare</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Timer Channel is configured for Output Compare - set output on compare</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Timer Channel is configured for Output Compare - clear output on compare, set output on overflow</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10x1</name>
|
|
<description>Timer Channel is configured for Output Compare - set output on compare, clear output on overflow</description>
|
|
<value>#10x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Timer Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input Capture or Output Compare has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input Capture or Output Compare has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TCCR%s</name>
|
|
<description>Timer Compare Capture Register</description>
|
|
<addressOffset>0x60C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCC</name>
|
|
<description>Timer Capture Compare</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC0</name>
|
|
<description>12-Bit Digital-to-Analog Converter</description>
|
|
<groupName>DAC</groupName>
|
|
<prependToName>DAC0_</prependToName>
|
|
<baseAddress>0x400CC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC0</name>
|
|
<value>81</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>DAT%sL</name>
|
|
<description>DAC Data Low Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>DAT%sH</name>
|
|
<description>DAC Data High Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>DAC Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFRPBF</name>
|
|
<description>DAC buffer read pointer bottom position flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer is not equal to the DACBFUP.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer is equal to the DACBFUP.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFRPTF</name>
|
|
<description>DAC buffer read pointer top position flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer is not zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer is zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFWMF</name>
|
|
<description>DAC buffer watermark flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer has not reached the watermark level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer has reached the watermark level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x21</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBBIEN</name>
|
|
<description>DAC buffer read pointer bottom flag interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer bottom flag interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer bottom flag interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBTIEN</name>
|
|
<description>DAC buffer read pointer top flag interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer top flag interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer top flag interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBWIEN</name>
|
|
<description>DAC buffer watermark interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer watermark interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer watermark interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>DAC low power control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>high power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACSWTRG</name>
|
|
<description>DAC software trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC soft trigger is not valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC soft trigger is valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACTRGSEL</name>
|
|
<description>DAC trigger select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC hardware trigger is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACRFS</name>
|
|
<description>DAC Reference Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC selets DACREF_1 as the reference voltage.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC selets DACREF_2 as the reference voltage.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC system is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC system is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>DAC Control Register 1</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFEN</name>
|
|
<description>DAC buffer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer read pointer disabled. The converted data is always the first word of the buffer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFMD</name>
|
|
<description>DAC buffer work mode select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal Mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Swing Mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>One-Time Scan Mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFWM</name>
|
|
<description>DAC buffer watermark select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1 word</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2 words</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3 words</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 words</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>DAC Control Register 2</description>
|
|
<addressOffset>0x23</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFUP</name>
|
|
<description>DAC buffer upper limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACBFRP</name>
|
|
<description>DAC buffer read pointer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC1</name>
|
|
<description>12-Bit Digital-to-Analog Converter</description>
|
|
<groupName>DAC</groupName>
|
|
<prependToName>DAC1_</prependToName>
|
|
<baseAddress>0x400CD000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC1</name>
|
|
<value>82</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>DAT%sL</name>
|
|
<description>DAC Data Low Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>DAT%sH</name>
|
|
<description>DAC Data High Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>DAC Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFRPBF</name>
|
|
<description>DAC buffer read pointer bottom position flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer is not equal to the DACBFUP.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer is equal to the DACBFUP.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFRPTF</name>
|
|
<description>DAC buffer read pointer top position flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer is not zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer is zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFWMF</name>
|
|
<description>DAC buffer watermark flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer has not reached the watermark level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer has reached the watermark level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>DAC Control Register</description>
|
|
<addressOffset>0x21</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBBIEN</name>
|
|
<description>DAC buffer read pointer bottom flag interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer bottom flag interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer bottom flag interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBTIEN</name>
|
|
<description>DAC buffer read pointer top flag interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer read pointer top flag interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer read pointer top flag interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBWIEN</name>
|
|
<description>DAC buffer watermark interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC buffer watermark interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC buffer watermark interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>DAC low power control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>high power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACSWTRG</name>
|
|
<description>DAC software trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC soft trigger is not valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC soft trigger is valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACTRGSEL</name>
|
|
<description>DAC trigger select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC hardware trigger is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACRFS</name>
|
|
<description>DAC Reference Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC selets DACREF_1 as the reference voltage.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC selets DACREF_2 as the reference voltage.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC system is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC system is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>DAC Control Register 1</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFEN</name>
|
|
<description>DAC buffer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer read pointer disabled. The converted data is always the first word of the buffer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFMD</name>
|
|
<description>DAC buffer work mode select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal Mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Swing Mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>One-Time Scan Mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACBFWM</name>
|
|
<description>DAC buffer watermark select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1 word</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2 words</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3 words</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 words</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>DAC Control Register 2</description>
|
|
<addressOffset>0x23</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACBFUP</name>
|
|
<description>DAC buffer upper limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACBFRP</name>
|
|
<description>DAC buffer read pointer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OPAMP0</name>
|
|
<description>General Purpose Operational Amplifier</description>
|
|
<groupName>OPAMP</groupName>
|
|
<prependToName>OPAMP0_</prependToName>
|
|
<baseAddress>0x400F5000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>OPAMP Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>General purpose</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Inverting PGA</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Non-inverting PGA</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>Low-Power Mode Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-speed mode selected. In this mode, OPAMP has faster slew rate and unity gain bandwidth performance with higher current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-power mode selected. In this mode, OPAMP has lower current consumption with slower slew rate and unity gain bandwidth performance.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>OPAMP Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OPAMP is disabled and not powered</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OPAMP is enabled and powered</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMPRI</name>
|
|
<description>Gains Selector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AMPRF</name>
|
|
<description>Gains Selector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>Control Register 2</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMPNSEL</name>
|
|
<description>Amplifier Negative Input Terminal Selector.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Negative input 0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Negative input 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Negative input 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Negative input 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Negative input 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Negative input 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Negative input 6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Negative input 7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AMPPSEL</name>
|
|
<description>Amplifier Positive Input Terminal Selector</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Positive input 0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Positive input 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Positive input 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Positive input 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Positive input 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Positive input 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Positive input 6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Positive input 7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OPAMP1</name>
|
|
<description>General Purpose Operational Amplifier</description>
|
|
<groupName>OPAMP</groupName>
|
|
<prependToName>OPAMP1_</prependToName>
|
|
<baseAddress>0x400F5800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>OPAMP Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>General purpose</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Inverting PGA</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Non-inverting PGA</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>Low-Power Mode Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-speed mode selected. In this mode, OPAMP has faster slew rate and unity gain bandwidth performance with higher current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-power mode selected. In this mode, OPAMP has lower current consumption with slower slew rate and unity gain bandwidth performance.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>OPAMP Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OPAMP is disabled and not powered</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OPAMP is enabled and powered</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMPRI</name>
|
|
<description>Gains Selector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AMPRF</name>
|
|
<description>Gains Selector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>Control Register 2</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMPNSEL</name>
|
|
<description>Amplifier Negative Input Terminal Selector.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Negative input 0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Negative input 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Negative input 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Negative input 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Negative input 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Negative input 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Negative input 6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Negative input 7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AMPPSEL</name>
|
|
<description>Amplifier Positive Input Terminal Selector</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Positive input 0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Positive input 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Positive input 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Positive input 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Positive input 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Positive input 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Positive input 6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Positive input 7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRIAMP0</name>
|
|
<description>Trans-Impedance Amplifier</description>
|
|
<groupName>TRIAMP</groupName>
|
|
<prependToName>TRIAMP0_</prependToName>
|
|
<baseAddress>0x400F8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>Low-Power Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-speed mode selected. In this mode, TRIAMP has faster slew rate and unity gain bandwidth performance with higher current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-power mode selected. In this mode, TRIAMP has lower current consumption with slower slew rate and unity gain bandwidth performance.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIAMPEN</name>
|
|
<description>TRIAMP Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier is disabled and not powered.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TRIAMP system is enabled. In this mode the amplifier is powered and enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRIAMP1</name>
|
|
<description>Trans-Impedance Amplifier</description>
|
|
<groupName>TRIAMP</groupName>
|
|
<prependToName>TRIAMP1_</prependToName>
|
|
<baseAddress>0x400F8800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>Low-Power Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-speed mode selected. In this mode, TRIAMP has faster slew rate and unity gain bandwidth performance with higher current consumption.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-power mode selected. In this mode, TRIAMP has lower current consumption with slower slew rate and unity gain bandwidth performance.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIAMPEN</name>
|
|
<description>TRIAMP Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier is disabled and not powered.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TRIAMP system is enabled. In this mode the amplifier is powered and enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOA_</prependToName>
|
|
<baseAddress>0x400FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTA</name>
|
|
<value>87</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic zero or is configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port data direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general purpose input, if configured for the GPIO function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured for general purpose output, if configured for the GPIO function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOB_</prependToName>
|
|
<baseAddress>0x400FF040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTB</name>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic zero or is configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port data direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general purpose input, if configured for the GPIO function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured for general purpose output, if configured for the GPIO function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTC</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOC_</prependToName>
|
|
<baseAddress>0x400FF080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTC</name>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic zero or is configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port data direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general purpose input, if configured for the GPIO function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured for general purpose output, if configured for the GPIO function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTD</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOD_</prependToName>
|
|
<baseAddress>0x400FF0C0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTD</name>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic zero or is configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port data direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general purpose input, if configured for the GPIO function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured for general purpose output, if configured for the GPIO function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTE</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOE_</prependToName>
|
|
<baseAddress>0x400FF100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTE</name>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin provided pin is configured for General Purpose Output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic zero or is configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port data direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general purpose input, if configured for the GPIO function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured for general purpose output, if configured for the GPIO function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SystemControl</name>
|
|
<description>System Control Registers</description>
|
|
<prependToName>SCB_</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0xD38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<description>Auxiliary Control Register,</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DISMCYCINT</name>
|
|
<description>Disables interruption of multi-cycle instructions.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISDEFWBUF</name>
|
|
<description>Disables write buffer use during default memory map accesses.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISFOLD</name>
|
|
<description>Disables folding of IT instructions.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPUID Base Register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410FC240</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Indicates patch release: 0x0 = Patch 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARTNO</name>
|
|
<description>Indicates part number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VARIANT</name>
|
|
<description>Indicates processor revision: 0x2 = Revision 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTER</name>
|
|
<description>Implementer code</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<description>Interrupt Control and State Register</description>
|
|
<addressOffset>0xD04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Active exception number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>there are preempted active exceptions to execute</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>there are no active exceptions, or the currently-executing exception is the only active exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Exception number of the highest priority pending enabled exception</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISRPREEMPT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Will not service</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Will service a pending exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>removes the pending state from the SysTick exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: SysTick exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>removes the pending state from the PendSV exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: PendSV exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: NMI exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes NMI exception state to pending; read: NMI exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0xD08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<description>Application Interrupt and Reset Control Register</description>
|
|
<addressOffset>0xD0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTRESET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no system reset request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>asserts a signal to the outer system that requests a reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRIGROUP</name>
|
|
<description>Interrupt priority grouping field. This field determines the split of group priority from subpriority.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANNESS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little-endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big-endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0xD10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>o not sleep when returning to Thread mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enter sleep, or deep sleep, on return from an ISR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>sleep</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>deep sleep</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Configuration and Control Register</description>
|
|
<addressOffset>0xD14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NONBASETHRDENA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>processor can enter Thread mode only when no exception is active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>processor can enter Thread mode from any level under the control of an EXC_RETURN value</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>Enables unprivileged software access to the STIR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Enables unaligned access traps</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>do not trap unaligned halfword and word accesses</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>trap unaligned halfword and word accesses</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>do not trap divide by 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>trap divide by 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>data bus faults caused by load and store instructions cause a lock-up</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>Indicates stack alignment on exception entry</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>4-byte aligned</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>8-byte aligned</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR1</name>
|
|
<description>System Handler Priority Register 1</description>
|
|
<addressOffset>0xD18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of system handler 4, MemManage</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of system handler 5, BusFault</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of system handler 6, UsageFault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<description>System Handler Priority Register 2</description>
|
|
<addressOffset>0xD1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11, SVCall</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<description>System Handler Priority Register 3</description>
|
|
<addressOffset>0xD20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14, PendSV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15, SysTick exception</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0xD24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEMFAULTACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONITORACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not active</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTPENDED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTPENDED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTPENDED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTENA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>disable the exception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enable the exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTENA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>disable the exception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enable the exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTENA</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>disable the exception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enable the exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFSR</name>
|
|
<description>Configurable Fault Status Registers</description>
|
|
<addressOffset>0xD28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IACCVIOL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no instruction access violation fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor attempted an instruction fetch from a location that does not permit execution</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACCVIOL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no data access violation fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor attempted a load or store at a location that does not permit the operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUNSTKERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no unstacking fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>unstack for an exception return has caused one or more access violations</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTKERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no stacking fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>stacking for an exception entry has caused one or more access violations</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MLSPERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No MemManage fault occurred during floating-point lazy state preservation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A MemManage fault occurred during floating-point lazy state preservation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MMARVALID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>value in MMAR is not a valid fault address</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MMAR holds a valid fault address</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IBUSERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no instruction bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>instruction bus error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRECISERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no precise data bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMPRECISERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no imprecise data bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNSTKERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no unstacking fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>unstack for an exception return has caused one or more BusFaults</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STKERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no stacking fault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>stacking for an exception entry has caused one or more BusFaults</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSPERR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus fault occurred during floating-point lazy state preservation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus fault occurred during floating-point lazy state preservation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFARVALID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>value in BFAR is not a valid fault address</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BFAR holds a valid fault address</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNDEFINSTR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no undefined instruction UsageFault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has attempted to execute an undefined instruction</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVSTATE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no invalid state UsageFault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has attempted to execute an instruction that makes illegal use of the EPSR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVPC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no invalid PC load UsageFault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has attempted an illegal load of EXC_RETURN to the PC</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOCP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no UsageFault caused by attempting to access a coprocessor</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has attempted to access a coprocessor</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGNED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no unaligned access fault, or unaligned access trapping not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has made an unaligned memory access</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVBYZERO</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no divide by zero fault, or divide by zero trapping not enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the processor has executed an SDIV or UDIV instruction with a divisor of 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFSR</name>
|
|
<description>HardFault Status register</description>
|
|
<addressOffset>0xD2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTTBL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no BusFault on vector table read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BusFault on vector table read</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no forced HardFault</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>forced HardFault</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGEVT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0xD30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active halt request debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Halt request debug event active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No current breakpoint debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one current breakpoint debug event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No current debug events generated by the DWT</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one current debug event generated by the DWT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Vector catch triggered</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vector catch triggered</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No EDBGRQ debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EDBGRQ debug event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFAR</name>
|
|
<description>MemManage Address Register</description>
|
|
<addressOffset>0xD34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address of MemManage fault location</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFAR</name>
|
|
<description>BusFault Address Register</description>
|
|
<addressOffset>0xD38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address of the BusFault location</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<description>Auxiliary Fault Status Register</description>
|
|
<addressOffset>0xD3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUXFAULT</name>
|
|
<description>Latched version of the AUXFAULT inputs</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SysTick</name>
|
|
<description>System timer</description>
|
|
<prependToName>SYST_</prependToName>
|
|
<baseAddress>0xE000E010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>counter disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>counter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>counting down to 0 does not assert the SysTick exception request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>counting down to 0 asserts the SysTick exception request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>external clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>processor clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RVR</name>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Value to load into the SysTick Current Value Register when the counter reaches 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CVR</name>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current value at the time the register is accessed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>SysTick Calibration Value Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Reload value to use for 10ms timing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>10ms calibration value is exact</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10ms calibration value is inexact, because of the clock frequency</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The reference clock is provided</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The reference clock is not provided</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>NVICISER0</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER1</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER2</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER3</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER0</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER1</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER2</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER3</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR0</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR1</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR2</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR3</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR0</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR1</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR2</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR3</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR0</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR1</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR2</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR3</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP0</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI0</name>
|
|
<description>Priority of interrupt 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP1</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x301</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI1</name>
|
|
<description>Priority of interrupt 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP2</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x302</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI2</name>
|
|
<description>Priority of interrupt 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP3</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x303</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI3</name>
|
|
<description>Priority of interrupt 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP4</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI4</name>
|
|
<description>Priority of interrupt 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP5</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x305</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI5</name>
|
|
<description>Priority of interrupt 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP6</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x306</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI6</name>
|
|
<description>Priority of interrupt 6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP7</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x307</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI7</name>
|
|
<description>Priority of interrupt 7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP8</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI8</name>
|
|
<description>Priority of interrupt 8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP9</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x309</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI9</name>
|
|
<description>Priority of interrupt 9</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP10</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI10</name>
|
|
<description>Priority of interrupt 10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP11</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI11</name>
|
|
<description>Priority of interrupt 11</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP12</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI12</name>
|
|
<description>Priority of interrupt 12</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP13</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI13</name>
|
|
<description>Priority of interrupt 13</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP14</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI14</name>
|
|
<description>Priority of interrupt 14</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP15</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x30F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI15</name>
|
|
<description>Priority of interrupt 15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP16</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI16</name>
|
|
<description>Priority of interrupt 16</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP17</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x311</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI17</name>
|
|
<description>Priority of interrupt 17</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP18</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x312</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI18</name>
|
|
<description>Priority of interrupt 18</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP19</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x313</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI19</name>
|
|
<description>Priority of interrupt 19</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP20</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI20</name>
|
|
<description>Priority of interrupt 20</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP21</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x315</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI21</name>
|
|
<description>Priority of interrupt 21</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP22</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x316</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI22</name>
|
|
<description>Priority of interrupt 22</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP23</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x317</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI23</name>
|
|
<description>Priority of interrupt 23</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP24</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI24</name>
|
|
<description>Priority of interrupt 24</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP25</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x319</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI25</name>
|
|
<description>Priority of interrupt 25</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP26</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI26</name>
|
|
<description>Priority of interrupt 26</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP27</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI27</name>
|
|
<description>Priority of interrupt 27</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP28</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI28</name>
|
|
<description>Priority of interrupt 28</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP29</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI29</name>
|
|
<description>Priority of interrupt 29</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP30</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI30</name>
|
|
<description>Priority of interrupt 30</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP31</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x31F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI31</name>
|
|
<description>Priority of interrupt 31</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP32</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI32</name>
|
|
<description>Priority of interrupt 32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP33</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x321</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI33</name>
|
|
<description>Priority of interrupt 33</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP34</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x322</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI34</name>
|
|
<description>Priority of interrupt 34</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP35</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x323</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI35</name>
|
|
<description>Priority of interrupt 35</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP36</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x324</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI36</name>
|
|
<description>Priority of interrupt 36</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP37</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x325</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI37</name>
|
|
<description>Priority of interrupt 37</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP38</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x326</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI38</name>
|
|
<description>Priority of interrupt 38</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP39</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x327</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI39</name>
|
|
<description>Priority of interrupt 39</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP40</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI40</name>
|
|
<description>Priority of interrupt 40</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP41</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x329</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI41</name>
|
|
<description>Priority of interrupt 41</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP42</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI42</name>
|
|
<description>Priority of interrupt 42</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP43</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI43</name>
|
|
<description>Priority of interrupt 43</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP44</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI44</name>
|
|
<description>Priority of interrupt 44</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP45</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI45</name>
|
|
<description>Priority of interrupt 45</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP46</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI46</name>
|
|
<description>Priority of interrupt 46</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP47</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x32F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI47</name>
|
|
<description>Priority of interrupt 47</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP48</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI48</name>
|
|
<description>Priority of interrupt 48</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP49</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x331</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI49</name>
|
|
<description>Priority of interrupt 49</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP50</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x332</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI50</name>
|
|
<description>Priority of interrupt 50</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP51</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x333</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI51</name>
|
|
<description>Priority of interrupt 51</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP52</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI52</name>
|
|
<description>Priority of interrupt 52</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP53</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x335</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI53</name>
|
|
<description>Priority of interrupt 53</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP54</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x336</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI54</name>
|
|
<description>Priority of interrupt 54</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP55</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x337</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI55</name>
|
|
<description>Priority of interrupt 55</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP56</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI56</name>
|
|
<description>Priority of interrupt 56</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP57</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x339</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI57</name>
|
|
<description>Priority of interrupt 57</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP58</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI58</name>
|
|
<description>Priority of interrupt 58</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP59</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI59</name>
|
|
<description>Priority of interrupt 59</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP60</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI60</name>
|
|
<description>Priority of interrupt 60</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP61</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI61</name>
|
|
<description>Priority of interrupt 61</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP62</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI62</name>
|
|
<description>Priority of interrupt 62</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP63</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x33F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI63</name>
|
|
<description>Priority of interrupt 63</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP64</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI64</name>
|
|
<description>Priority of interrupt 64</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP65</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x341</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI65</name>
|
|
<description>Priority of interrupt 65</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP66</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x342</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI66</name>
|
|
<description>Priority of interrupt 66</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP67</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x343</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI67</name>
|
|
<description>Priority of interrupt 67</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP68</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x344</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI68</name>
|
|
<description>Priority of interrupt 68</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP69</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x345</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI69</name>
|
|
<description>Priority of interrupt 69</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP70</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x346</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI70</name>
|
|
<description>Priority of interrupt 70</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP71</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x347</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI71</name>
|
|
<description>Priority of interrupt 71</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP72</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI72</name>
|
|
<description>Priority of interrupt 72</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP73</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x349</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI73</name>
|
|
<description>Priority of interrupt 73</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP74</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI74</name>
|
|
<description>Priority of interrupt 74</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP75</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI75</name>
|
|
<description>Priority of interrupt 75</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP76</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI76</name>
|
|
<description>Priority of interrupt 76</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP77</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI77</name>
|
|
<description>Priority of interrupt 77</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP78</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI78</name>
|
|
<description>Priority of interrupt 78</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP79</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x34F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI79</name>
|
|
<description>Priority of interrupt 79</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP80</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI80</name>
|
|
<description>Priority of interrupt 80</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP81</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x351</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI81</name>
|
|
<description>Priority of interrupt 81</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP82</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x352</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI82</name>
|
|
<description>Priority of interrupt 82</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP83</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x353</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI83</name>
|
|
<description>Priority of interrupt 83</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP84</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x354</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI84</name>
|
|
<description>Priority of interrupt 84</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP85</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x355</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI85</name>
|
|
<description>Priority of interrupt 85</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP86</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x356</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI86</name>
|
|
<description>Priority of interrupt 86</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP87</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x357</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI87</name>
|
|
<description>Priority of interrupt 87</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP88</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x358</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI88</name>
|
|
<description>Priority of interrupt 88</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP89</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x359</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI89</name>
|
|
<description>Priority of interrupt 89</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP90</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI90</name>
|
|
<description>Priority of interrupt 90</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP91</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI91</name>
|
|
<description>Priority of interrupt 91</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP92</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI92</name>
|
|
<description>Priority of interrupt 92</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP93</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI93</name>
|
|
<description>Priority of interrupt 93</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP94</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI94</name>
|
|
<description>Priority of interrupt 94</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP95</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x35F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI95</name>
|
|
<description>Priority of interrupt 95</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP96</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x360</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI96</name>
|
|
<description>Priority of interrupt 96</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP97</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x361</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI97</name>
|
|
<description>Priority of interrupt 97</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP98</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x362</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI98</name>
|
|
<description>Priority of interrupt 98</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP99</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x363</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI99</name>
|
|
<description>Priority of interrupt 99</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP100</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x364</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI100</name>
|
|
<description>Priority of interrupt 100</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP101</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x365</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI101</name>
|
|
<description>Priority of interrupt 101</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP102</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x366</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI102</name>
|
|
<description>Priority of interrupt 102</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP103</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x367</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI103</name>
|
|
<description>Priority of interrupt 103</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP104</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x368</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI104</name>
|
|
<description>Priority of interrupt 104</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP105</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x369</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI105</name>
|
|
<description>Priority of interrupt 105</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICSTIR</name>
|
|
<description>Software Trigger Interrupt Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCM</name>
|
|
<description>Core Platform Miscellaneous Control Module</description>
|
|
<prependToName>MCM_</prependToName>
|
|
<baseAddress>0xE0080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PLASC</name>
|
|
<description>Crossbar switch (AXBS) slave configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus slave connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus slave connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLAMC</name>
|
|
<description>Crossbar switch (AXBS) master configuration</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x3F</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMC</name>
|
|
<description>Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus master connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus master connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMAP</name>
|
|
<description>SRAM arbitration and protection</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRAMUAP</name>
|
|
<description>SRAM_U arbitration priority</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Round robin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Special round robin (favors SRAM backoor accesses over the processor)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed priority. Processor has highest, backdoor has lowest</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fixed priority. Backdoor has highest, processor has lowest</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMUWP</name>
|
|
<description>SRAM_U write protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRAMLAP</name>
|
|
<description>SRAM_L arbitration priority</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Round robin</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Special round robin (favors SRAM backoor accesses over the processor)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed priority. Processor has highest, backdoor has lowest</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fixed priority. Backdoor has highest, processor has lowest</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMLWP</name>
|
|
<description>SRAM_L write protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Normal interrupt pending</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No pending interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Due to the ETB counter expiring, a normal interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>Non-maskable interrupt pending</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No pending NMI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Due to the ETB counter expiring, an NMI is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETBCC</name>
|
|
<description>ETB counter control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ETB counter disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ETB counter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPT</name>
|
|
<description>Response type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No response when the ETB count expires</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate a normal interrupt when the ETB count expires</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Generate an NMI when the ETB count expires</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Generate a debug halt when the ETB count expires</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RLRQ</name>
|
|
<description>Reload request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears pending debug halt, NMI, or IRQ interrupt requests</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETDIS</name>
|
|
<description>ETM-to-TPIU disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ETM-to-TPIU trace path enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ETM-to-TPIU trace path disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITDIS</name>
|
|
<description>ITM-to-TPIU disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ITM-to-TPIU trace path enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ITM-to-TPIU trace path disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETBRL</name>
|
|
<description>ETB reload register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Byte count reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETBCNT</name>
|
|
<description>ETB counter value register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Byte count counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAU</name>
|
|
<description>Memory Mapped Cryptographic Acceleration Unit (MMCAU)</description>
|
|
<baseAddress>0xE0081000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xB6C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CAU_DIRECT0</name>
|
|
<description>Direct access register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT0</name>
|
|
<description>Direct register 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT1</name>
|
|
<description>Direct access register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT1</name>
|
|
<description>Direct register 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT2</name>
|
|
<description>Direct access register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT2</name>
|
|
<description>Direct register 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT3</name>
|
|
<description>Direct access register 3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT3</name>
|
|
<description>Direct register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT4</name>
|
|
<description>Direct access register 4</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT4</name>
|
|
<description>Direct register 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT5</name>
|
|
<description>Direct access register 5</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT5</name>
|
|
<description>Direct register 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT6</name>
|
|
<description>Direct access register 6</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT6</name>
|
|
<description>Direct register 6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT7</name>
|
|
<description>Direct access register 7</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT7</name>
|
|
<description>Direct register 7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT8</name>
|
|
<description>Direct access register 8</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT8</name>
|
|
<description>Direct register 8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT9</name>
|
|
<description>Direct access register 9</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT9</name>
|
|
<description>Direct register 9</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT10</name>
|
|
<description>Direct access register 10</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT10</name>
|
|
<description>Direct register 10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT11</name>
|
|
<description>Direct access register 11</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT11</name>
|
|
<description>Direct register 11</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT12</name>
|
|
<description>Direct access register 12</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT12</name>
|
|
<description>Direct register 12</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT13</name>
|
|
<description>Direct access register 13</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT13</name>
|
|
<description>Direct register 13</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT14</name>
|
|
<description>Direct access register 14</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT14</name>
|
|
<description>Direct register 14</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_DIRECT15</name>
|
|
<description>Direct access register 15</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAU_DIRECT15</name>
|
|
<description>Direct register 15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CASR</name>
|
|
<description>Status register - Load Register command</description>
|
|
<addressOffset>0x840</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CAA</name>
|
|
<description>Accumulator register - Load Register command</description>
|
|
<addressOffset>0x844</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA0</name>
|
|
<description>General Purpose Register 0 - Load Register command</description>
|
|
<addressOffset>0x848</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA1</name>
|
|
<description>General Purpose Register 1 - Load Register command</description>
|
|
<addressOffset>0x84C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA2</name>
|
|
<description>General Purpose Register 2 - Load Register command</description>
|
|
<addressOffset>0x850</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA3</name>
|
|
<description>General Purpose Register 3 - Load Register command</description>
|
|
<addressOffset>0x854</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA4</name>
|
|
<description>General Purpose Register 4 - Load Register command</description>
|
|
<addressOffset>0x858</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA5</name>
|
|
<description>General Purpose Register 5 - Load Register command</description>
|
|
<addressOffset>0x85C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA6</name>
|
|
<description>General Purpose Register 6 - Load Register command</description>
|
|
<addressOffset>0x860</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA7</name>
|
|
<description>General Purpose Register 7 - Load Register command</description>
|
|
<addressOffset>0x864</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_LDR_CA8</name>
|
|
<description>General Purpose Register 8 - Load Register command</description>
|
|
<addressOffset>0x868</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CASR</name>
|
|
<description>Status register - Store Register command</description>
|
|
<addressOffset>0x880</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CAA</name>
|
|
<description>Accumulator register - Store Register command</description>
|
|
<addressOffset>0x884</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA0</name>
|
|
<description>General Purpose Register 0 - Store Register command</description>
|
|
<addressOffset>0x888</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA1</name>
|
|
<description>General Purpose Register 1 - Store Register command</description>
|
|
<addressOffset>0x88C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA2</name>
|
|
<description>General Purpose Register 2 - Store Register command</description>
|
|
<addressOffset>0x890</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA3</name>
|
|
<description>General Purpose Register 3 - Store Register command</description>
|
|
<addressOffset>0x894</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA4</name>
|
|
<description>General Purpose Register 4 - Store Register command</description>
|
|
<addressOffset>0x898</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA5</name>
|
|
<description>General Purpose Register 5 - Store Register command</description>
|
|
<addressOffset>0x89C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA6</name>
|
|
<description>General Purpose Register 6 - Store Register command</description>
|
|
<addressOffset>0x8A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA7</name>
|
|
<description>General Purpose Register 7 - Store Register command</description>
|
|
<addressOffset>0x8A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_STR_CA8</name>
|
|
<description>General Purpose Register 8 - Store Register command</description>
|
|
<addressOffset>0x8A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CASR</name>
|
|
<description>Status register - Add Register command</description>
|
|
<addressOffset>0x8C0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CAA</name>
|
|
<description>Accumulator register - Add to register command</description>
|
|
<addressOffset>0x8C4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA0</name>
|
|
<description>General Purpose Register 0 - Add to register command</description>
|
|
<addressOffset>0x8C8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA1</name>
|
|
<description>General Purpose Register 1 - Add to register command</description>
|
|
<addressOffset>0x8CC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA2</name>
|
|
<description>General Purpose Register 2 - Add to register command</description>
|
|
<addressOffset>0x8D0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA3</name>
|
|
<description>General Purpose Register 3 - Add to register command</description>
|
|
<addressOffset>0x8D4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA4</name>
|
|
<description>General Purpose Register 4 - Add to register command</description>
|
|
<addressOffset>0x8D8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA5</name>
|
|
<description>General Purpose Register 5 - Add to register command</description>
|
|
<addressOffset>0x8DC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA6</name>
|
|
<description>General Purpose Register 6 - Add to register command</description>
|
|
<addressOffset>0x8E0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA7</name>
|
|
<description>General Purpose Register 7 - Add to register command</description>
|
|
<addressOffset>0x8E4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ADR_CA8</name>
|
|
<description>General Purpose Register 8 - Add to register command</description>
|
|
<addressOffset>0x8E8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CASR</name>
|
|
<description>Status register - Reverse and Add to Register command</description>
|
|
<addressOffset>0x900</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CAA</name>
|
|
<description>Accumulator register - Reverse and Add to Register command</description>
|
|
<addressOffset>0x904</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA0</name>
|
|
<description>General Purpose Register 0 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x908</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA1</name>
|
|
<description>General Purpose Register 1 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x90C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA2</name>
|
|
<description>General Purpose Register 2 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x910</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA3</name>
|
|
<description>General Purpose Register 3 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x914</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA4</name>
|
|
<description>General Purpose Register 4 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x918</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA5</name>
|
|
<description>General Purpose Register 5 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x91C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA6</name>
|
|
<description>General Purpose Register 6 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x920</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA7</name>
|
|
<description>General Purpose Register 7 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x924</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_RADR_CA8</name>
|
|
<description>General Purpose Register 8 - Reverse and Add to Register command</description>
|
|
<addressOffset>0x928</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CASR</name>
|
|
<description>Status register - Exclusive Or command</description>
|
|
<addressOffset>0x980</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CAA</name>
|
|
<description>Accumulator register - Exclusive Or command</description>
|
|
<addressOffset>0x984</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA0</name>
|
|
<description>General Purpose Register 0 - Exclusive Or command</description>
|
|
<addressOffset>0x988</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA1</name>
|
|
<description>General Purpose Register 1 - Exclusive Or command</description>
|
|
<addressOffset>0x98C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA2</name>
|
|
<description>General Purpose Register 2 - Exclusive Or command</description>
|
|
<addressOffset>0x990</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA3</name>
|
|
<description>General Purpose Register 3 - Exclusive Or command</description>
|
|
<addressOffset>0x994</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA4</name>
|
|
<description>General Purpose Register 4 - Exclusive Or command</description>
|
|
<addressOffset>0x998</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA5</name>
|
|
<description>General Purpose Register 5 - Exclusive Or command</description>
|
|
<addressOffset>0x99C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA6</name>
|
|
<description>General Purpose Register 6 - Exclusive Or command</description>
|
|
<addressOffset>0x9A0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA7</name>
|
|
<description>General Purpose Register 7 - Exclusive Or command</description>
|
|
<addressOffset>0x9A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_XOR_CA8</name>
|
|
<description>General Purpose Register 8 - Exclusive Or command</description>
|
|
<addressOffset>0x9A8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CASR</name>
|
|
<description>Status register - Rotate Left command</description>
|
|
<addressOffset>0x9C0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CAA</name>
|
|
<description>Accumulator register - Rotate Left command</description>
|
|
<addressOffset>0x9C4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA0</name>
|
|
<description>General Purpose Register 0 - Rotate Left command</description>
|
|
<addressOffset>0x9C8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA1</name>
|
|
<description>General Purpose Register 1 - Rotate Left command</description>
|
|
<addressOffset>0x9CC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA2</name>
|
|
<description>General Purpose Register 2 - Rotate Left command</description>
|
|
<addressOffset>0x9D0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA3</name>
|
|
<description>General Purpose Register 3 - Rotate Left command</description>
|
|
<addressOffset>0x9D4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA4</name>
|
|
<description>General Purpose Register 4 - Rotate Left command</description>
|
|
<addressOffset>0x9D8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA5</name>
|
|
<description>General Purpose Register 5 - Rotate Left command</description>
|
|
<addressOffset>0x9DC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA6</name>
|
|
<description>General Purpose Register 6 - Rotate Left command</description>
|
|
<addressOffset>0x9E0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA7</name>
|
|
<description>General Purpose Register 7 - Rotate Left command</description>
|
|
<addressOffset>0x9E4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_ROTL_CA8</name>
|
|
<description>General Purpose Register 8 - Rotate Left command</description>
|
|
<addressOffset>0x9E8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CASR</name>
|
|
<description>Status register - AES Column Operation command</description>
|
|
<addressOffset>0xB00</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CAA</name>
|
|
<description>Accumulator register - AES Column Operation command</description>
|
|
<addressOffset>0xB04</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA0</name>
|
|
<description>General Purpose Register 0 - AES Column Operation command</description>
|
|
<addressOffset>0xB08</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA1</name>
|
|
<description>General Purpose Register 1 - AES Column Operation command</description>
|
|
<addressOffset>0xB0C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA2</name>
|
|
<description>General Purpose Register 2 - AES Column Operation command</description>
|
|
<addressOffset>0xB10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA3</name>
|
|
<description>General Purpose Register 3 - AES Column Operation command</description>
|
|
<addressOffset>0xB14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA4</name>
|
|
<description>General Purpose Register 4 - AES Column Operation command</description>
|
|
<addressOffset>0xB18</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA5</name>
|
|
<description>General Purpose Register 5 - AES Column Operation command</description>
|
|
<addressOffset>0xB1C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA6</name>
|
|
<description>General Purpose Register 6 - AES Column Operation command</description>
|
|
<addressOffset>0xB20</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA7</name>
|
|
<description>General Purpose Register 7 - AES Column Operation command</description>
|
|
<addressOffset>0xB24</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESC_CA8</name>
|
|
<description>General Purpose Register 8 - AES Column Operation command</description>
|
|
<addressOffset>0xB28</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CASR</name>
|
|
<description>Status register - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB40</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No illegal commands issued</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal command issued</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DES key parity error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VER</name>
|
|
<description>CAU version</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Initial CAU version</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Second version, added support for SHA-256 algorithm.(This is the value on this device)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CAA</name>
|
|
<description>Accumulator register - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB44</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>ACC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA0</name>
|
|
<description>General Purpose Register 0 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB48</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA0</name>
|
|
<description>CA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA1</name>
|
|
<description>General Purpose Register 1 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB4C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA1</name>
|
|
<description>CA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA2</name>
|
|
<description>General Purpose Register 2 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB50</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA2</name>
|
|
<description>CA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA3</name>
|
|
<description>General Purpose Register 3 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB54</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA3</name>
|
|
<description>CA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA4</name>
|
|
<description>General Purpose Register 4 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB58</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA4</name>
|
|
<description>CA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA5</name>
|
|
<description>General Purpose Register 5 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB5C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA5</name>
|
|
<description>CA5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA6</name>
|
|
<description>General Purpose Register 6 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB60</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA6</name>
|
|
<description>CA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA7</name>
|
|
<description>General Purpose Register 7 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB64</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA7</name>
|
|
<description>CA7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAU_AESIC_CA8</name>
|
|
<description>General Purpose Register 8 - AES Inverse Column Operation command</description>
|
|
<addressOffset>0xB68</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CA8</name>
|
|
<description>CA8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|