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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright (c) 2017 Microchip Technology Inc.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
schemaVersion="1.1"
xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>Microchip Technology</vendor>
<vendorID>MCHP</vendorID>
<name>ATSAMV71N19B</name>
<series>SAMV71</series>
<version>0</version>
<description>Microchip ATSAMV71N19B Microcontroller</description>
<cpu>
<name>CM7</name>
<revision>r1p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>ACC</name>
<version>6490J</version>
<description>Analog Comparator Controller</description>
<groupName>ACC</groupName>
<prependToName>ACC_</prependToName>
<baseAddress>0x40044000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ACC</name>
<value>33</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>SELMINUS</name>
<description>Selection for Minus Comparator Input</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>SELMINUSSelect</name>
<enumeratedValue>
<name>TS</name>
<description>Select TS</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>VREFP</name>
<description>Select VREFP</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DAC0</name>
<description>Select DAC0</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DAC1</name>
<description>Select DAC1</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD0</name>
<description>Select AFE0_AD0</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD1</name>
<description>Select AFE0_AD1</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD2</name>
<description>Select AFE0_AD2</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD3</name>
<description>Select AFE0_AD3</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SELPLUS</name>
<description>Selection For Plus Comparator Input</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>SELPLUSSelect</name>
<enumeratedValue>
<name>AFE0_AD0</name>
<description>Select AFE0_AD0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD1</name>
<description>Select AFE0_AD1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD2</name>
<description>Select AFE0_AD2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD3</name>
<description>Select AFE0_AD3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD4</name>
<description>Select AFE0_AD4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE0_AD5</name>
<description>Select AFE0_AD5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE1_AD0</name>
<description>Select AFE1_AD0</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>AFE1_AD1</name>
<description>Select AFE1_AD1</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACEN</name>
<description>Analog Comparator Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ACENSelect</name>
<enumeratedValue>
<name>DIS</name>
<description>Analog comparator disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>Analog comparator enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGETYP</name>
<description>Edge Type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>EDGETYPSelect</name>
<enumeratedValue>
<name>RISING</name>
<description>Only rising edge of comparator output</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge of comparator output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ANY</name>
<description>Any edge of comparator output</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert Comparator Output</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INVSelect</name>
<enumeratedValue>
<name>DIS</name>
<description>Analog comparator output is directly processed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>Analog comparator output is inverted prior to being processed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SELFS</name>
<description>Selection Of Fault Source</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SELFSSelect</name>
<enumeratedValue>
<name>CE</name>
<description>The CE flag is used to drive the FAULT output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTPUT</name>
<description>The output of the analog comparator flag is used to drive the FAULT output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Fault Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FESelect</name>
<enumeratedValue>
<name>DIS</name>
<description>The FAULT output is tied to 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The FAULT output is driven by the signal defined by SELFS.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CE</name>
<description>Comparison Edge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CE</name>
<description>Comparison Edge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CE</name>
<description>Comparison Edge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CE</name>
<description>Comparison Edge (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCO</name>
<description>Synchronized Comparator Output</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK</name>
<description>Flag Mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR</name>
<description>Analog Control Register</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<fields>
<field>
<name>ISEL</name>
<description>Current Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ISELSelect</name>
<enumeratedValue>
<name>LOPW</name>
<description>Low-power option.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HISP</name>
<description>High-speed option.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYST</name>
<description>Hysteresis Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x414343</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AES</name>
<version>6149W</version>
<description>Advanced Encryption Standard</description>
<groupName>AES</groupName>
<prependToName>AES_</prependToName>
<baseAddress>0x4006C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xAC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AES</name>
<value>56</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>START</name>
<description>Start Processing</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOADSEED</name>
<description>Random Number Generator Seed Loading</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>CIPHER</name>
<description>Processing Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTAGEN</name>
<description>GCM Automatic Tag Generation Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUALBUFF</name>
<description>Dual Input Buffer</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DUALBUFFSelect</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>AES_IDATARx cannot be written during processing of previous block.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROCDLY</name>
<description>Processing Delay</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SMOD</name>
<description>Start Mode</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SMODSelect</name>
<enumeratedValue>
<name>MANUAL_START</name>
<description>Manual Mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_START</name>
<description>Auto Mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IDATAR0_START</name>
<description>AES_IDATAR0 access only Auto Mode (DMA)</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYSIZE</name>
<description>Key Size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>KEYSIZESelect</name>
<enumeratedValue>
<name>AES128</name>
<description>AES Key Size is 128 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AES192</name>
<description>AES Key Size is 192 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AES256</name>
<description>AES Key Size is 256 bits</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPMOD</name>
<description>Operating Mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>OPMODSelect</name>
<enumeratedValue>
<name>ECB</name>
<description>ECB: Electronic Code Book mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CBC</name>
<description>CBC: Cipher Block Chaining mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OFB</name>
<description>OFB: Output Feedback mode</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CFB</name>
<description>CFB: Cipher Feedback mode</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CTR</name>
<description>CTR: Counter mode (16-bit internal counter)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>GCM</name>
<description>GCM: Galois/Counter mode</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOD</name>
<description>Last Output Data Mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFBS</name>
<description>Cipher Feedback Data Size</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CFBSSelect</name>
<enumeratedValue>
<name>SIZE_128BIT</name>
<description>128-bit</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SIZE_64BIT</name>
<description>64-bit</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SIZE_32BIT</name>
<description>32-bit</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SIZE_16BIT</name>
<description>16-bit</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SIZE_8BIT</name>
<description>8-bit</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKEY</name>
<description>Countermeasure Key</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>CKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0.</description>
<value>0xE</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Unspecified Register Access Detection Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAGRDY</name>
<description>GCM Tag Ready Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Unspecified Register Access Detection Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAGRDY</name>
<description>GCM Tag Ready Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Unspecified Register Access Detection Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAGRDY</name>
<description>GCM Tag Ready Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URAT</name>
<description>Unspecified Register Access (cleared by writing SWRST in AES_CR)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>URATSelect</name>
<enumeratedValue>
<name>IDR_WR_PROCESSING</name>
<description>Input Data Register written during the data processing when SMOD = 0x2 mode.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ODR_RD_PROCESSING</name>
<description>Output Data Register read during the data processing.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MR_WR_PROCESSING</name>
<description>Mode Register written during the data processing.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ODR_RD_SUBKGEN</name>
<description>Output Data Register read during the sub-keys generation.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MR_WR_SUBKGEN</name>
<description>Mode Register written during the sub-keys generation.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>WOR_RD_ACCESS</name>
<description>Write-only register read access.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAGRDY</name>
<description>GCM Tag Ready</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>KEYWR[%s]</name>
<description>Key Word Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>KEYW</name>
<description>Key Word</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>IDATAR[%s]</name>
<description>Input Data Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>IDATA</name>
<description>Input Data Word</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>ODATAR[%s]</name>
<description>Output Data Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ODATA</name>
<description>Output Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>IVR[%s]</name>
<description>Initialization Vector Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>IV</name>
<description>Initialization Vector</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AADLENR</name>
<description>Additional Authenticated Data Length Register</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<fields>
<field>
<name>AADLEN</name>
<description>Additional Authenticated Data Length</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLENR</name>
<description>Plaintext/Ciphertext Length Register</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<fields>
<field>
<name>CLEN</name>
<description>Plaintext/Ciphertext Length</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>GHASHR[%s]</name>
<description>GCM Intermediate Hash Word Register</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<fields>
<field>
<name>GHASH</name>
<description>Intermediate GCM Hash Word x</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>TAGR[%s]</name>
<description>GCM Authentication Tag Word Register</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TAG</name>
<description>GCM Authentication Tag x</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRR</name>
<description>GCM Encryption Counter Value Register</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CTR</name>
<description>GCM Encryption Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>GCMHR[%s]</name>
<description>GCM H Word Register</description>
<addressOffset>0x9C</addressOffset>
<size>32</size>
<fields>
<field>
<name>H</name>
<description>GCM H Word x</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AFEC0</name>
<version>11147S</version>
<description>Analog Front-End Controller</description>
<groupName>AFEC</groupName>
<prependToName>AFEC_</prependToName>
<baseAddress>0x4003C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AFEC0</name>
<value>29</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>AFEC Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start Conversion</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>AFEC Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>TRGEN</name>
<description>Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRGENSelect</name>
<enumeratedValue>
<name>DIS</name>
<description>Hardware triggers are disabled. Starting a conversion is only possible by software.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>Hardware trigger selected by TRGSEL field is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL</name>
<description>Trigger Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TRGSELSelect</name>
<enumeratedValue>
<name>AFEC_TRIG0</name>
<description>AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG1</name>
<description>TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG2</name>
<description>TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG3</name>
<description>TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG4</name>
<description>PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG5</name>
<description>PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC_TRIG6</name>
<description>Analog Comparator</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEEP</name>
<description>Sleep Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SLEEPSelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal mode: The AFE and reference voltage circuitry are kept ON between conversions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLEEP</name>
<description>Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FWUP</name>
<description>Fast Wake-up</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FWUPSelect</name>
<enumeratedValue>
<name>OFF</name>
<description>Normal Sleep mode: The sleep mode is defined by the SLEEP bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ON</name>
<description>Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FREERUN</name>
<description>Free Run Mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FREERUNSelect</name>
<enumeratedValue>
<name>OFF</name>
<description>Normal mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ON</name>
<description>Free Run mode: Never wait for any trigger.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCAL</name>
<description>Prescaler Rate Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>STARTUP</name>
<description>Start-up Time</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>STARTUPSelect</name>
<enumeratedValue>
<name>SUT0</name>
<description>0 periods of AFE clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT8</name>
<description>8 periods of AFE clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT16</name>
<description>16 periods of AFE clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT24</name>
<description>24 periods of AFE clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT64</name>
<description>64 periods of AFE clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT80</name>
<description>80 periods of AFE clock</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT96</name>
<description>96 periods of AFE clock</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT112</name>
<description>112 periods of AFE clock</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT512</name>
<description>512 periods of AFE clock</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT576</name>
<description>576 periods of AFE clock</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT640</name>
<description>640 periods of AFE clock</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT704</name>
<description>704 periods of AFE clock</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT768</name>
<description>768 periods of AFE clock</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT832</name>
<description>832 periods of AFE clock</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT896</name>
<description>896 periods of AFE clock</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>SUT960</name>
<description>960 periods of AFE clock</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONE</name>
<description>One</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACKTIM</name>
<description>Tracking Time</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRANSFER</name>
<description>Transfer Period</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>USEQ</name>
<description>User Sequence Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>USEQSelect</name>
<enumeratedValue>
<name>NUM_ORDER</name>
<description>Normal mode: The controller converts channels in a simple numeric order.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REG_ORDER</name>
<description>User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>AFEC Extended Mode Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>CMPMODE</name>
<description>Comparison Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CMPMODESelect</name>
<enumeratedValue>
<name>LOW</name>
<description>Generates an event when the converted data is lower than the low threshold of the window.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Generates an event when the converted data is higher than the high threshold of the window.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>Generates an event when the converted data is in the comparison window.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT</name>
<description>Generates an event when the converted data is out of the comparison window.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPSEL</name>
<description>Comparison Selected Channel</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CMPALL</name>
<description>Compare All Channels</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPFILTER</name>
<description>Compare Event Filtering</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RES</name>
<description>Resolution</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>RESSelect</name>
<enumeratedValue>
<name>NO_AVERAGE</name>
<description>12-bit resolution, AFE sample rate is maximum (no averaging).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR4</name>
<description>13-bit resolution, AFE sample rate divided by 4 (averaging).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR16</name>
<description>14-bit resolution, AFE sample rate divided by 16 (averaging).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR64</name>
<description>15-bit resolution, AFE sample rate divided by 64 (averaging).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR256</name>
<description>16-bit resolution, AFE sample rate divided by 256 (averaging).</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAG</name>
<description>TAG of the AFEC_LDCR</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STM</name>
<description>Single Trigger Mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIGNMODE</name>
<description>Sign Mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SIGNMODESelect</name>
<enumeratedValue>
<name>SE_UNSG_DF_SIGN</name>
<description>Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SE_SIGN_DF_UNSG</name>
<description>Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ALL_UNSIGNED</name>
<description>All channels: Unsigned conversions.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ALL_SIGNED</name>
<description>All channels: Signed conversions.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQ1R</name>
<description>AFEC Channel Sequence 1 Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>USCH0</name>
<description>User Sequence Number 0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH1</name>
<description>User Sequence Number 1</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH2</name>
<description>User Sequence Number 2</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH3</name>
<description>User Sequence Number 3</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH4</name>
<description>User Sequence Number 4</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH5</name>
<description>User Sequence Number 5</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH6</name>
<description>User Sequence Number 6</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH7</name>
<description>User Sequence Number 7</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SEQ2R</name>
<description>AFEC Channel Sequence 2 Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>USCH8</name>
<description>User Sequence Number 8</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH9</name>
<description>User Sequence Number 9</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH10</name>
<description>User Sequence Number 10</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USCH11</name>
<description>User Sequence Number 11</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHER</name>
<description>AFEC Channel Enable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH10</name>
<description>Channel 10 Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH11</name>
<description>Channel 11 Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHDR</name>
<description>AFEC Channel Disable Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH10</name>
<description>Channel 10 Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH11</name>
<description>Channel 11 Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHSR</name>
<description>AFEC Channel Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH10</name>
<description>Channel 10 Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH11</name>
<description>Channel 11 Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCDR</name>
<description>AFEC Last Converted Data Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LDATA</name>
<description>Last Data Converted</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CHNB</name>
<description>Channel Number</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>AFEC Interrupt Enable Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Enable 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Enable 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC2</name>
<description>End of Conversion Interrupt Enable 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC3</name>
<description>End of Conversion Interrupt Enable 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC4</name>
<description>End of Conversion Interrupt Enable 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC5</name>
<description>End of Conversion Interrupt Enable 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC6</name>
<description>End of Conversion Interrupt Enable 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC7</name>
<description>End of Conversion Interrupt Enable 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC8</name>
<description>End of Conversion Interrupt Enable 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC9</name>
<description>End of Conversion Interrupt Enable 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC10</name>
<description>End of Conversion Interrupt Enable 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC11</name>
<description>End of Conversion Interrupt Enable 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRDY</name>
<description>Data Ready Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GOVRE</name>
<description>General Overrun Error Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPE</name>
<description>Comparison Event Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMPCHG</name>
<description>Temperature Change Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>AFEC Interrupt Disable Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Disable 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Disable 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC2</name>
<description>End of Conversion Interrupt Disable 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC3</name>
<description>End of Conversion Interrupt Disable 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC4</name>
<description>End of Conversion Interrupt Disable 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC5</name>
<description>End of Conversion Interrupt Disable 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC6</name>
<description>End of Conversion Interrupt Disable 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC7</name>
<description>End of Conversion Interrupt Disable 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC8</name>
<description>End of Conversion Interrupt Disable 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC9</name>
<description>End of Conversion Interrupt Disable 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC10</name>
<description>End of Conversion Interrupt Disable 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC11</name>
<description>End of Conversion Interrupt Disable 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRDY</name>
<description>Data Ready Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GOVRE</name>
<description>General Overrun Error Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPE</name>
<description>Comparison Event Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMPCHG</name>
<description>Temperature Change Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>AFEC Interrupt Mask Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Mask 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Mask 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC2</name>
<description>End of Conversion Interrupt Mask 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC3</name>
<description>End of Conversion Interrupt Mask 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC4</name>
<description>End of Conversion Interrupt Mask 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC5</name>
<description>End of Conversion Interrupt Mask 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC6</name>
<description>End of Conversion Interrupt Mask 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC7</name>
<description>End of Conversion Interrupt Mask 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC8</name>
<description>End of Conversion Interrupt Mask 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC9</name>
<description>End of Conversion Interrupt Mask 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC10</name>
<description>End of Conversion Interrupt Mask 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC11</name>
<description>End of Conversion Interrupt Mask 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRDY</name>
<description>Data Ready Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GOVRE</name>
<description>General Overrun Error Interrupt Mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPE</name>
<description>Comparison Event Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMPCHG</name>
<description>Temperature Change Interrupt Mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>AFEC Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>EOC0</name>
<description>End of Conversion 0 (cleared by reading AFEC_CDRx)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion 1 (cleared by reading AFEC_CDRx)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC2</name>
<description>End of Conversion 2 (cleared by reading AFEC_CDRx)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC3</name>
<description>End of Conversion 3 (cleared by reading AFEC_CDRx)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC4</name>
<description>End of Conversion 4 (cleared by reading AFEC_CDRx)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC5</name>
<description>End of Conversion 5 (cleared by reading AFEC_CDRx)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC6</name>
<description>End of Conversion 6 (cleared by reading AFEC_CDRx)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC7</name>
<description>End of Conversion 7 (cleared by reading AFEC_CDRx)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC8</name>
<description>End of Conversion 8 (cleared by reading AFEC_CDRx)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC9</name>
<description>End of Conversion 9 (cleared by reading AFEC_CDRx)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC10</name>
<description>End of Conversion 10 (cleared by reading AFEC_CDRx)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC11</name>
<description>End of Conversion 11 (cleared by reading AFEC_CDRx)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRDY</name>
<description>Data Ready (cleared by reading AFEC_LCDR)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GOVRE</name>
<description>General Overrun Error (cleared by reading AFEC_ISR)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPE</name>
<description>Comparison Error (cleared by reading AFEC_ISR)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMPCHG</name>
<description>Temperature Change (cleared on read)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OVER</name>
<description>AFEC Overrun Status Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>OVRE0</name>
<description>Overrun Error 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE1</name>
<description>Overrun Error 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE2</name>
<description>Overrun Error 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE3</name>
<description>Overrun Error 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE4</name>
<description>Overrun Error 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE5</name>
<description>Overrun Error 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE6</name>
<description>Overrun Error 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE7</name>
<description>Overrun Error 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE8</name>
<description>Overrun Error 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE9</name>
<description>Overrun Error 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE10</name>
<description>Overrun Error 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE11</name>
<description>Overrun Error 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWR</name>
<description>AFEC Compare Window Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<fields>
<field>
<name>LOWTHRES</name>
<description>Low Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HIGHTHRES</name>
<description>High Threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CGR</name>
<description>AFEC Channel Gain Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<fields>
<field>
<name>GAIN0</name>
<description>Gain for Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN1</name>
<description>Gain for Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN2</name>
<description>Gain for Channel 2</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN3</name>
<description>Gain for Channel 3</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN4</name>
<description>Gain for Channel 4</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN5</name>
<description>Gain for Channel 5</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN6</name>
<description>Gain for Channel 6</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN7</name>
<description>Gain for Channel 7</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN8</name>
<description>Gain for Channel 8</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN9</name>
<description>Gain for Channel 9</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN10</name>
<description>Gain for Channel 10</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GAIN11</name>
<description>Gain for Channel 11</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIFFR</name>
<description>AFEC Channel Differential Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<fields>
<field>
<name>DIFF0</name>
<description>Differential inputs for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF1</name>
<description>Differential inputs for channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF2</name>
<description>Differential inputs for channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF3</name>
<description>Differential inputs for channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF4</name>
<description>Differential inputs for channel 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF5</name>
<description>Differential inputs for channel 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF6</name>
<description>Differential inputs for channel 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF7</name>
<description>Differential inputs for channel 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF8</name>
<description>Differential inputs for channel 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF9</name>
<description>Differential inputs for channel 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF10</name>
<description>Differential inputs for channel 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF11</name>
<description>Differential inputs for channel 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSELR</name>
<description>AFEC Channel Selection Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSEL</name>
<description>Channel Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDR</name>
<description>AFEC Channel Data Register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATA</name>
<description>Converted Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>COCR</name>
<description>AFEC Channel Offset Compensation Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<fields>
<field>
<name>AOFF</name>
<description>Analog Offset</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>TEMPMR</name>
<description>AFEC Temperature Sensor Mode Register</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<fields>
<field>
<name>RTCT</name>
<description>Temperature Sensor RTC Trigger Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMPCMPMOD</name>
<description>Temperature Comparison Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TEMPCMPMODSelect</name>
<enumeratedValue>
<name>LOW</name>
<description>Generates an event when the converted data is lower than the low threshold of the window.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Generates an event when the converted data is higher than the high threshold of the window.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>Generates an event when the converted data is in the comparison window.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT</name>
<description>Generates an event when the converted data is out of the comparison window.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TEMPCWR</name>
<description>AFEC Temperature Compare Window Register</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<fields>
<field>
<name>TLOWTHRES</name>
<description>Temperature Low Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>THIGHTHRES</name>
<description>Temperature High Threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR</name>
<description>AFEC Analog Control Register</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<fields>
<field>
<name>PGA0EN</name>
<description>PGA0 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGA1EN</name>
<description>PGA1 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IBCTL</name>
<description>AFE Bias Current Control</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHMR</name>
<description>AFEC Sample &amp; Hold Mode Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<fields>
<field>
<name>DUAL0</name>
<description>Dual Sample &amp; Hold for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL1</name>
<description>Dual Sample &amp; Hold for channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL2</name>
<description>Dual Sample &amp; Hold for channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL3</name>
<description>Dual Sample &amp; Hold for channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL4</name>
<description>Dual Sample &amp; Hold for channel 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL5</name>
<description>Dual Sample &amp; Hold for channel 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL6</name>
<description>Dual Sample &amp; Hold for channel 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL7</name>
<description>Dual Sample &amp; Hold for channel 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL8</name>
<description>Dual Sample &amp; Hold for channel 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL9</name>
<description>Dual Sample &amp; Hold for channel 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL10</name>
<description>Dual Sample &amp; Hold for channel 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUAL11</name>
<description>Dual Sample &amp; Hold for channel 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>COSR</name>
<description>AFEC Correction Select Register</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSEL</name>
<description>Sample &amp; Hold unit Correction Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVR</name>
<description>AFEC Correction Values Register</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<fields>
<field>
<name>OFFSETCORR</name>
<description>Offset Correction</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GAINCORR</name>
<description>Gain Correction</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CECR</name>
<description>AFEC Channel Error Correction Register</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<fields>
<field>
<name>ECORR0</name>
<description>Error Correction Enable for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR1</name>
<description>Error Correction Enable for channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR2</name>
<description>Error Correction Enable for channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR3</name>
<description>Error Correction Enable for channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR4</name>
<description>Error Correction Enable for channel 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR5</name>
<description>Error Correction Enable for channel 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR6</name>
<description>Error Correction Enable for channel 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR7</name>
<description>Error Correction Enable for channel 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR8</name>
<description>Error Correction Enable for channel 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR9</name>
<description>Error Correction Enable for channel 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR10</name>
<description>Error Correction Enable for channel 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECORR11</name>
<description>Error Correction Enable for channel 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>AFEC Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protect KEY</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
<value>0x414443</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>AFEC Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protect Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protect Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="AFEC0">
<name>AFEC1</name>
<baseAddress>0x40064000</baseAddress>
<interrupt>
<name>AFEC1</name>
<value>40</value>
</interrupt>
</peripheral>
<peripheral>
<name>CHIPID</name>
<version>6417ZK</version>
<description>Chip Identifier</description>
<groupName>CHIPID</groupName>
<prependToName>CHIPID_</prependToName>
<baseAddress>0x400E0940</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CIDR</name>
<description>Chip ID Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>VERSION</name>
<description>Version of the Device</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EPROC</name>
<description>Embedded Processor</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>EPROCSelect</name>
<enumeratedValue>
<name>SAMx7</name>
<description>Cortex-M7</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ARM946ES</name>
<description>ARM946ES</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ARM7TDMI</name>
<description>ARM7TDMI</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CM3</name>
<description>Cortex-M3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>ARM920T</name>
<description>ARM920T</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ARM926EJS</name>
<description>ARM926EJS</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CA5</name>
<description>Cortex-A5</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CM4</name>
<description>Cortex-M4</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NVPSIZ</name>
<description>Nonvolatile Program Memory Size</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>NVPSIZSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_8K</name>
<description>8 Kbytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16K</name>
<description>16 Kbytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_32K</name>
<description>32 Kbytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_64K</name>
<description>64 Kbytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_128K</name>
<description>128 Kbytes</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>_160K</name>
<description>160 Kbytes</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>_256K</name>
<description>256 Kbytes</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>_512K</name>
<description>512 Kbytes</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024K</name>
<description>1024 Kbytes</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>_2048K</name>
<description>2048 Kbytes</description>
<value>0xE</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NVPSIZ2</name>
<description>Second Nonvolatile Program Memory Size</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>NVPSIZ2Select</name>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_8K</name>
<description>8 Kbytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16K</name>
<description>16 Kbytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_32K</name>
<description>32 Kbytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_64K</name>
<description>64 Kbytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_128K</name>
<description>128 Kbytes</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>_256K</name>
<description>256 Kbytes</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>_512K</name>
<description>512 Kbytes</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024K</name>
<description>1024 Kbytes</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>_2048K</name>
<description>2048 Kbytes</description>
<value>0xE</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRAMSIZ</name>
<description>Internal SRAM Size</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>SRAMSIZSelect</name>
<enumeratedValue>
<name>_48K</name>
<description>48 Kbytes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_192K</name>
<description>192 Kbytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_384K</name>
<description>384 Kbytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_6K</name>
<description>6 Kbytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_24K</name>
<description>24 Kbytes</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_4K</name>
<description>4 Kbytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_80K</name>
<description>80 Kbytes</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_160K</name>
<description>160 Kbytes</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>_8K</name>
<description>8 Kbytes</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>_16K</name>
<description>16 Kbytes</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>_32K</name>
<description>32 Kbytes</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>_64K</name>
<description>64 Kbytes</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>_128K</name>
<description>128 Kbytes</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>_256K</name>
<description>256 Kbytes</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>_96K</name>
<description>96 Kbytes</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>_512K</name>
<description>512 Kbytes</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARCH</name>
<description>Architecture Identifier</description>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>ARCHSelect</name>
<enumeratedValue>
<name>SAME70</name>
<description>SAM E70</description>
<value>0x10</value>
</enumeratedValue>
<enumeratedValue>
<name>SAMS70</name>
<description>SAM S70</description>
<value>0x11</value>
</enumeratedValue>
<enumeratedValue>
<name>SAMV71</name>
<description>SAM V71</description>
<value>0x12</value>
</enumeratedValue>
<enumeratedValue>
<name>SAMV70</name>
<description>SAM V70</description>
<value>0x13</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NVPTYP</name>
<description>Nonvolatile Program Memory Type</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>NVPTYPSelect</name>
<enumeratedValue>
<name>ROM</name>
<description>ROM</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ROMLESS</name>
<description>ROMless or on-chip Flash</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FLASH</name>
<description>Embedded Flash Memory</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ROM_FLASH</name>
<description>ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SRAM</name>
<description>SRAM emulating ROM</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXT</name>
<description>Extension Flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXID</name>
<description>Chip ID Extension Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>EXID</name>
<description>Chip ID Extension</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DACC</name>
<version>11246E</version>
<description>Digital-to-Analog Converter Controller</description>
<groupName>DACC</groupName>
<prependToName>DACC_</prependToName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DACC</name>
<value>30</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>MAXS0</name>
<description>Max Speed Mode for Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MAXS0Select</name>
<enumeratedValue>
<name>TRIG_EVENT</name>
<description>External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAXIMUM</name>
<description>Max speed mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAXS1</name>
<description>Max Speed Mode for Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MAXS1Select</name>
<enumeratedValue>
<name>TRIG_EVENT</name>
<description>External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAXIMUM</name>
<description>Max speed mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WORD</name>
<description>Word Transfer Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WORDSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>One data to convert is written to the FIFO per access to DACC.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ZERO</name>
<description>Must always be written to 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIFF</name>
<description>Differential Mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIFFSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>DAC0 and DAC1 are single-ended outputs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>DACP and DACN are differential outputs. The differential level is configured by the channel 0 value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALER</name>
<description>Peripheral Clock to DAC Clock Ratio</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TRIGR</name>
<description>Trigger Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>TRGEN0</name>
<description>Trigger Enable of Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRGEN0Select</name>
<enumeratedValue>
<name>DIS</name>
<description>External trigger mode disabled. DACC is in Free-running mode or Max speed mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>External trigger mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGEN1</name>
<description>Trigger Enable of Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRGEN1Select</name>
<enumeratedValue>
<name>DIS</name>
<description>External trigger mode disabled. DACC is in Free-running mode or Max speed mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>External trigger mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL0</name>
<description>Trigger Selection of Channel 0</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TRGSEL0Select</name>
<enumeratedValue>
<name>TRGSEL0</name>
<description>DAC External Trigger Input (DATRG)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL1</name>
<description>TC0 Channel 0 Output (TIOA0)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL2</name>
<description>TC0 Channel 1 Output (TIOA1)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL3</name>
<description>TC0 Channel 2 Output (TIOA2)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL4</name>
<description>PWM0 Event Line 0</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL5</name>
<description>PWM0 Event Line 1</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL6</name>
<description>PWM1 Event Line 0</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL7</name>
<description>PWM1 Event Line 1</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL1</name>
<description>Trigger Selection of Channel 1</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TRGSEL1Select</name>
<enumeratedValue>
<name>TRGSEL0</name>
<description>DAC External Trigger Input (DATRG)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL1</name>
<description>TC0 Channel 0 Output (TIOA0)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL2</name>
<description>TC0 Channel 1 Output (TIOA1)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL3</name>
<description>TC0 Channel 2 Output (TIOA2)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL4</name>
<description>PWM0 Event Line 0</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL5</name>
<description>PWM0 Event Line 1</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL6</name>
<description>PWM1 Event Line 0</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>TRGSEL7</name>
<description>PWM1 Event Line 1</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSR0</name>
<description>Over Sampling Ratio of Channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>OSR0Select</name>
<enumeratedValue>
<name>OSR_1</name>
<description>OSR = 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_2</name>
<description>OSR = 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_4</name>
<description>OSR = 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_8</name>
<description>OSR = 8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_16</name>
<description>OSR = 16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_32</name>
<description>OSR = 32</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSR1</name>
<description>Over Sampling Ratio of Channel 1</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>OSR1Select</name>
<enumeratedValue>
<name>OSR_1</name>
<description>OSR = 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_2</name>
<description>OSR = 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_4</name>
<description>OSR = 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_8</name>
<description>OSR = 8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_16</name>
<description>OSR = 16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>OSR_32</name>
<description>OSR = 32</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHER</name>
<description>Channel Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHDR</name>
<description>Channel Disable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHSR</name>
<description>Channel Status Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACRDY0</name>
<description>DAC Ready Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACRDY1</name>
<description>DAC Ready Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>CDR[%s]</name>
<description>Conversion Data Register 0</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATA0</name>
<description>Data to Convert for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DATA1</name>
<description>Data to Convert for channel 1</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXRDY0</name>
<description>Transmit Ready Interrupt Enable of channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY1</name>
<description>Transmit Ready Interrupt Enable of channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Enable of channel 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Enable of channel 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXRDY0</name>
<description>Transmit Ready Interrupt Disable of channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY1</name>
<description>Transmit Ready Interrupt Disable of channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Disable of channel 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Disable of channel 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXRDY0</name>
<description>Transmit Ready Interrupt Mask of channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY1</name>
<description>Transmit Ready Interrupt Mask of channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Mask of channel 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Mask of channel 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXRDY0</name>
<description>Transmit Ready Interrupt Flag of channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY1</name>
<description>Transmit Ready Interrupt Flag of channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC0</name>
<description>End of Conversion Interrupt Flag of channel 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of Conversion Interrupt Flag of channel 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR</name>
<description>Analog Current Register</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<fields>
<field>
<name>IBCTLCH0</name>
<description>Analog Output Current Control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IBCTLCH1</name>
<description>Analog Output Current Control</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protect Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0.</description>
<value>0x444143</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EFC</name>
<version>6450Y</version>
<description>Embedded Flash Controller</description>
<groupName>EFC</groupName>
<prependToName>EFC_</prependToName>
<baseAddress>0x400E0C00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EFC</name>
<value>6</value>
</interrupt>
<registers>
<register>
<name>EEFC_FMR</name>
<description>EEFC Flash Mode Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>FRDY</name>
<description>Flash Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FWS</name>
<description>Flash Wait State</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCOD</name>
<description>Sequential Code Optimization Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLOE</name>
<description>Code Loop Optimization Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFC_FCR</name>
<description>EEFC Flash Command Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>FCMD</name>
<description>Flash Command</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>FCMDSelect</name>
<enumeratedValue>
<name>GETD</name>
<description>Get Flash descriptor</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>WP</name>
<description>Write page</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>WPL</name>
<description>Write page and lock</description>
<value>0x02</value>
</enumeratedValue>
<enumeratedValue>
<name>EWP</name>
<description>Erase page and write page</description>
<value>0x03</value>
</enumeratedValue>
<enumeratedValue>
<name>EWPL</name>
<description>Erase page and write page then lock</description>
<value>0x04</value>
</enumeratedValue>
<enumeratedValue>
<name>EA</name>
<description>Erase all</description>
<value>0x05</value>
</enumeratedValue>
<enumeratedValue>
<name>EPA</name>
<description>Erase pages</description>
<value>0x07</value>
</enumeratedValue>
<enumeratedValue>
<name>SLB</name>
<description>Set lock bit</description>
<value>0x08</value>
</enumeratedValue>
<enumeratedValue>
<name>CLB</name>
<description>Clear lock bit</description>
<value>0x09</value>
</enumeratedValue>
<enumeratedValue>
<name>GLB</name>
<description>Get lock bit</description>
<value>0x0A</value>
</enumeratedValue>
<enumeratedValue>
<name>SGPB</name>
<description>Set GPNVM bit</description>
<value>0x0B</value>
</enumeratedValue>
<enumeratedValue>
<name>CGPB</name>
<description>Clear GPNVM bit</description>
<value>0x0C</value>
</enumeratedValue>
<enumeratedValue>
<name>GGPB</name>
<description>Get GPNVM bit</description>
<value>0x0D</value>
</enumeratedValue>
<enumeratedValue>
<name>STUI</name>
<description>Start read unique identifier</description>
<value>0x0E</value>
</enumeratedValue>
<enumeratedValue>
<name>SPUI</name>
<description>Stop read unique identifier</description>
<value>0x0F</value>
</enumeratedValue>
<enumeratedValue>
<name>GCALB</name>
<description>Get CALIB bit</description>
<value>0x10</value>
</enumeratedValue>
<enumeratedValue>
<name>ES</name>
<description>Erase sector</description>
<value>0x11</value>
</enumeratedValue>
<enumeratedValue>
<name>WUS</name>
<description>Write user signature</description>
<value>0x12</value>
</enumeratedValue>
<enumeratedValue>
<name>EUS</name>
<description>Erase user signature</description>
<value>0x13</value>
</enumeratedValue>
<enumeratedValue>
<name>STUS</name>
<description>Start read user signature</description>
<value>0x14</value>
</enumeratedValue>
<enumeratedValue>
<name>SPUS</name>
<description>Stop read user signature</description>
<value>0x15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FARG</name>
<description>Flash Command Argument</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FKEY</name>
<description>Flash Writing Protection Key</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>FKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.</description>
<value>0x5A</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EEFC_FSR</name>
<description>EEFC Flash Status Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FRDY</name>
<description>Flash Ready Status (cleared when Flash is busy)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCMDE</name>
<description>Flash Command Error Status (cleared on read or by writing EEFC_FCR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLOCKE</name>
<description>Flash Lock Error Status (cleared on read)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLERR</name>
<description>Flash Error Status (cleared when a programming operation starts)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UECCELSB</name>
<description>Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MECCELSB</name>
<description>Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UECCEMSB</name>
<description>Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MECCEMSB</name>
<description>Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFC_FRR</name>
<description>EEFC Flash Result Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FVALUE</name>
<description>Flash Result Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFC_WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
<value>0x454643</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GMAC</name>
<version>11046S</version>
<description>Gigabit Ethernet MAC</description>
<groupName>GMAC</groupName>
<prependToName>GMAC_</prependToName>
<baseAddress>0x40050000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x820</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GMAC</name>
<value>39</value>
</interrupt>
<interrupt>
<name>GMAC_Q1</name>
<value>66</value>
</interrupt>
<interrupt>
<name>GMAC_Q2</name>
<value>67</value>
</interrupt>
<interrupt>
<name>GMAC_Q3</name>
<value>71</value>
</interrupt>
<interrupt>
<name>GMAC_Q4</name>
<value>72</value>
</interrupt>
<interrupt>
<name>GMAC_Q5</name>
<value>73</value>
</interrupt>
<registers>
<register>
<name>NCR</name>
<description>Network Control Register</description>
<addressOffset>0x000</addressOffset>
<size>32</size>
<fields>
<field>
<name>LBL</name>
<description>Loop Back Local</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receive Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmit Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPE</name>
<description>Management Port Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLRSTAT</name>
<description>Clear Statistics Registers</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INCSTAT</name>
<description>Increment Statistics Registers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WESTAT</name>
<description>Write Enable for Statistics Registers</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BP</name>
<description>Back pressure</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTART</name>
<description>Start Transmission</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THALT</name>
<description>Transmit Halt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXPF</name>
<description>Transmit Pause Frame</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXZQPF</name>
<description>Transmit Zero Quantum Pause Frame</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRTSM</name>
<description>Store Receive Time Stamp to Memory</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENPBPR</name>
<description>Enable PFC Priority-based Pause Reception</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXPBPF</name>
<description>Transmit PFC Priority-based Pause Frame</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FNP</name>
<description>Flush Next Packet</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXLPIEN</name>
<description>Enable LPI Transmission</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NCFGR</name>
<description>Network Configuration Register</description>
<addressOffset>0x004</addressOffset>
<size>32</size>
<fields>
<field>
<name>SPD</name>
<description>Speed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FD</name>
<description>Full Duplex</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DNVLAN</name>
<description>Discard Non-VLAN FRAMES</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JFRAME</name>
<description>Jumbo Frame Size</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAF</name>
<description>Copy All Frames</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBC</name>
<description>No Broadcast</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTIHEN</name>
<description>Multicast Hash Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNIHEN</name>
<description>Unicast Hash Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MAXFS</name>
<description>1536 Maximum Frame Size</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTY</name>
<description>Retry Test</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN</name>
<description>Pause Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBUFO</name>
<description>Receive Buffer Offset</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LFERD</name>
<description>Length Field Error Frame Discard</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFCS</name>
<description>Remove FCS</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK</name>
<description>MDC CLock Division</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CLKSelect</name>
<enumeratedValue>
<name>MCK_8</name>
<description>MCK divided by 8 (MCK up to 20 MHz)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_16</name>
<description>MCK divided by 16 (MCK up to 40 MHz)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_32</name>
<description>MCK divided by 32 (MCK up to 80 MHz)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_48</name>
<description>MCK divided by 48 (MCK up to 120 MHz)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_64</name>
<description>MCK divided by 64 (MCK up to 160 MHz)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_96</name>
<description>MCK divided by 96 (MCK up to 240 MHz)</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBW</name>
<description>Data Bus Width</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DCPF</name>
<description>Disable Copy of Pause Frames</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXCOEN</name>
<description>Receive Checksum Offload Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFRHD</name>
<description>Enable Frames Received in Half Duplex</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRXFCS</name>
<description>Ignore RX FCS</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPGSEN</name>
<description>IP Stretch Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBP</name>
<description>Receive Bad Preamble</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRXER</name>
<description>Ignore IPG GRXER</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NSR</name>
<description>Network Status Register</description>
<addressOffset>0x008</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MDIO</name>
<description>MDIO Input Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>PHY Management Logic Idle</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLPIS</name>
<description>LPI Indication</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>UR</name>
<description>User Register</description>
<addressOffset>0x00C</addressOffset>
<size>32</size>
<fields>
<field>
<name>RMII</name>
<description>Reduced MII Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCFGR</name>
<description>DMA Configuration Register</description>
<addressOffset>0x010</addressOffset>
<size>32</size>
<fields>
<field>
<name>FBLDO</name>
<description>Fixed Burst Length for DMA Data Operations:</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<name>FBLDOSelect</name>
<enumeratedValue>
<name>SINGLE</name>
<description>00001: Always use SINGLE AHB bursts</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INCR4</name>
<description>001xx: Attempt to use INCR4 AHB bursts (Default)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INCR8</name>
<description>01xxx: Attempt to use INCR8 AHB bursts</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>INCR16</name>
<description>1xxxx: Attempt to use INCR16 AHB bursts</description>
<value>0x10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ESMA</name>
<description>Endian Swap Mode Enable for Management Descriptor Accesses</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESPA</name>
<description>Endian Swap Mode Enable for Packet Data Accesses</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBMS</name>
<description>Receiver Packet Buffer Memory Size Select</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>RXBMSSelect</name>
<enumeratedValue>
<name>EIGHTH</name>
<description>4/8 Kbyte Memory Size</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>QUARTER</name>
<description>4/4 Kbytes Memory Size</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>4/2 Kbytes Memory Size</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>4 Kbytes Memory Size</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXPBMS</name>
<description>Transmitter Packet Buffer Memory Size Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXCOEN</name>
<description>Transmitter Checksum Generation Offload Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRBS</name>
<description>DMA Receive Buffer Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DDRP</name>
<description>DMA Discard Receive Packets</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSR</name>
<description>Transmit Status Register</description>
<addressOffset>0x014</addressOffset>
<size>32</size>
<fields>
<field>
<name>UBR</name>
<description>Used Bit Read</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COL</name>
<description>Collision Occurred</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLE</name>
<description>Retry Limit Exceeded</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXGO</name>
<description>Transmit Go</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXCOMP</name>
<description>Transmit Complete</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RBQB</name>
<description>Receive Buffer Queue Base Address Register</description>
<addressOffset>0x018</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Receive Buffer Queue Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBQB</name>
<description>Transmit Buffer Queue Base Address Register</description>
<addressOffset>0x01C</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Transmit Buffer Queue Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSR</name>
<description>Receive Status Register</description>
<addressOffset>0x020</addressOffset>
<size>32</size>
<fields>
<field>
<name>BNA</name>
<description>Buffer Not Available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REC</name>
<description>Frame Received</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVR</name>
<description>Receive Overrun</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNO</name>
<description>HRESP Not OK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x024</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MFS</name>
<description>Management Frame Sent</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUBR</name>
<description>TX Used Bit Read</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TUR</name>
<description>Transmit Underrun</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFNZ</name>
<description>Pause Frame with Non-zero Pause Quantum Received</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTZ</name>
<description>Pause Time Zero</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFTR</name>
<description>Pause Frame Transmitted</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFR</name>
<description>PTP Delay Request Frame Received</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFR</name>
<description>PTP Sync Frame Received</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFT</name>
<description>PTP Delay Request Frame Transmitted</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFT</name>
<description>PTP Sync Frame Transmitted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFR</name>
<description>PDelay Request Frame Received</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFR</name>
<description>PDelay Response Frame Received</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFT</name>
<description>PDelay Request Frame Transmitted</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFT</name>
<description>PDelay Response Frame Transmitted</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRI</name>
<description>TSU Seconds Register Increment</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLPISBC</name>
<description>Receive LPI indication Status Bit Change</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WOL</name>
<description>Wake On LAN</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSUTIMCOMP</name>
<description>TSU Timer Comparison</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x028</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>MFS</name>
<description>Management Frame Sent</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUBR</name>
<description>TX Used Bit Read</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TUR</name>
<description>Transmit Underrun</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFNZ</name>
<description>Pause Frame with Non-zero Pause Quantum Received</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTZ</name>
<description>Pause Time Zero</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFTR</name>
<description>Pause Frame Transmitted</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXINT</name>
<description>External Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFR</name>
<description>PTP Delay Request Frame Received</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFR</name>
<description>PTP Sync Frame Received</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFT</name>
<description>PTP Delay Request Frame Transmitted</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFT</name>
<description>PTP Sync Frame Transmitted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFR</name>
<description>PDelay Request Frame Received</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFR</name>
<description>PDelay Response Frame Received</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFT</name>
<description>PDelay Request Frame Transmitted</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFT</name>
<description>PDelay Response Frame Transmitted</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRI</name>
<description>TSU Seconds Register Increment</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLPISBC</name>
<description>Enable RX LPI Indication</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WOL</name>
<description>Wake On LAN</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSUTIMCOMP</name>
<description>TSU Timer Comparison</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x02C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>MFS</name>
<description>Management Frame Sent</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUBR</name>
<description>TX Used Bit Read</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TUR</name>
<description>Transmit Underrun</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFNZ</name>
<description>Pause Frame with Non-zero Pause Quantum Received</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTZ</name>
<description>Pause Time Zero</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFTR</name>
<description>Pause Frame Transmitted</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXINT</name>
<description>External Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFR</name>
<description>PTP Delay Request Frame Received</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFR</name>
<description>PTP Sync Frame Received</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFT</name>
<description>PTP Delay Request Frame Transmitted</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFT</name>
<description>PTP Sync Frame Transmitted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFR</name>
<description>PDelay Request Frame Received</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFR</name>
<description>PDelay Response Frame Received</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFT</name>
<description>PDelay Request Frame Transmitted</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFT</name>
<description>PDelay Response Frame Transmitted</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRI</name>
<description>TSU Seconds Register Increment</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLPISBC</name>
<description>Enable RX LPI Indication</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WOL</name>
<description>Wake On LAN</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSUTIMCOMP</name>
<description>TSU Timer Comparison</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x030</addressOffset>
<size>32</size>
<fields>
<field>
<name>MFS</name>
<description>Management Frame Sent</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUBR</name>
<description>TX Used Bit Read</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TUR</name>
<description>Transmit Underrun</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFNZ</name>
<description>Pause Frame with Non-zero Pause Quantum Received</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTZ</name>
<description>Pause Time Zero</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFTR</name>
<description>Pause Frame Transmitted</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXINT</name>
<description>External Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFR</name>
<description>PTP Delay Request Frame Received</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFR</name>
<description>PTP Sync Frame Received</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRQFT</name>
<description>PTP Delay Request Frame Transmitted</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFT</name>
<description>PTP Sync Frame Transmitted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFR</name>
<description>PDelay Request Frame Received</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFR</name>
<description>PDelay Response Frame Received</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRQFT</name>
<description>PDelay Request Frame Transmitted</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDRSFT</name>
<description>PDelay Response Frame Transmitted</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRI</name>
<description>TSU Seconds Register Increment</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLPISBC</name>
<description>Enable RX LPI Indication</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WOL</name>
<description>Wake On LAN</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSUTIMCOMP</name>
<description>TSU Timer Comparison</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MAN</name>
<description>PHY Maintenance Register</description>
<addressOffset>0x034</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATA</name>
<description>PHY Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>WTN</name>
<description>Write Ten</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>REGA</name>
<description>Register Address</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PHYA</name>
<description>PHY Address</description>
<bitOffset>23</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OP</name>
<description>Operation</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLTTO</name>
<description>Clause 22 Operation</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WZO</name>
<description>Write ZERO</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RPQ</name>
<description>Received Pause Quantum Register</description>
<addressOffset>0x038</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RPQ</name>
<description>Received Pause Quantum</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TPQ</name>
<description>Transmit Pause Quantum Register</description>
<addressOffset>0x03C</addressOffset>
<size>32</size>
<fields>
<field>
<name>TPQ</name>
<description>Transmit Pause Quantum</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TPSF</name>
<description>TX Partial Store and Forward Register</description>
<addressOffset>0x040</addressOffset>
<size>32</size>
<fields>
<field>
<name>TPB1ADR</name>
<description>Transmit Partial Store and Forward Address</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>ENTXP</name>
<description>Enable TX Partial Store and Forward Operation</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RPSF</name>
<description>RX Partial Store and Forward Register</description>
<addressOffset>0x044</addressOffset>
<size>32</size>
<fields>
<field>
<name>RPB1ADR</name>
<description>Receive Partial Store and Forward Address</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>ENRXP</name>
<description>Enable RX Partial Store and Forward Operation</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RJFML</name>
<description>RX Jumbo Frame Max Length Register</description>
<addressOffset>0x048</addressOffset>
<size>32</size>
<fields>
<field>
<name>FML</name>
<description>Frame Max Length</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>HRB</name>
<description>Hash Register Bottom</description>
<addressOffset>0x080</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Hash Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HRT</name>
<description>Hash Register Top</description>
<addressOffset>0x084</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Hash Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>4</dim>
<dimIncrement>8</dimIncrement>
<dimIndex>1-4</dimIndex>
<name>GMAC_SA%s</name>
<description>Specific Address 1 Bottom Register</description>
<addressOffset>0x088</addressOffset>
<register>
<name>SAB</name>
<description>Specific Address 1 Bottom Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Specific Address 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAT</name>
<description>Specific Address 1 Top Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Specific Address 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>TIDM1</name>
<description>Type ID Match 1 Register</description>
<addressOffset>0x0A8</addressOffset>
<size>32</size>
<fields>
<field>
<name>TID</name>
<description>Type ID Match 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ENID1</name>
<description>Enable Copying of TID Matched Frames</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIDM2</name>
<description>Type ID Match 2 Register</description>
<addressOffset>0x0AC</addressOffset>
<size>32</size>
<fields>
<field>
<name>TID</name>
<description>Type ID Match 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ENID2</name>
<description>Enable Copying of TID Matched Frames</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIDM3</name>
<description>Type ID Match 3 Register</description>
<addressOffset>0x0B0</addressOffset>
<size>32</size>
<fields>
<field>
<name>TID</name>
<description>Type ID Match 3</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ENID3</name>
<description>Enable Copying of TID Matched Frames</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIDM4</name>
<description>Type ID Match 4 Register</description>
<addressOffset>0x0B4</addressOffset>
<size>32</size>
<fields>
<field>
<name>TID</name>
<description>Type ID Match 4</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ENID4</name>
<description>Enable Copying of TID Matched Frames</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WOL</name>
<description>Wake on LAN Register</description>
<addressOffset>0x0B8</addressOffset>
<size>32</size>
<fields>
<field>
<name>IP</name>
<description>ARP Request IP Address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>MAG</name>
<description>Magic Packet Event Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARP</name>
<description>ARP Request IP Address</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SA1</name>
<description>Specific Address Register 1 Event Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTI</name>
<description>Multicast Hash Event Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPGS</name>
<description>IPG Stretch Register</description>
<addressOffset>0x0BC</addressOffset>
<size>32</size>
<fields>
<field>
<name>FL</name>
<description>Frame Length</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SVLAN</name>
<description>Stacked VLAN Register</description>
<addressOffset>0x0C0</addressOffset>
<size>32</size>
<fields>
<field>
<name>VLAN_TYPE</name>
<description>User Defined VLAN_TYPE Field</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ESVLAN</name>
<description>Enable Stacked VLAN Processing Mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TPFCP</name>
<description>Transmit PFC Pause Register</description>
<addressOffset>0x0C4</addressOffset>
<size>32</size>
<fields>
<field>
<name>PEV</name>
<description>Priority Enable Vector</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PQ</name>
<description>Pause Quantum</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAMB1</name>
<description>Specific Address 1 Mask Bottom Register</description>
<addressOffset>0x0C8</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Specific Address 1 Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAMT1</name>
<description>Specific Address 1 Mask Top Register</description>
<addressOffset>0x0CC</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Specific Address 1 Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>NSC</name>
<description>1588 Timer Nanosecond Comparison Register</description>
<addressOffset>0x0DC</addressOffset>
<size>32</size>
<fields>
<field>
<name>NANOSEC</name>
<description>1588 Timer Nanosecond Comparison Value</description>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL</name>
<description>1588 Timer Second Comparison Low Register</description>
<addressOffset>0x0E0</addressOffset>
<size>32</size>
<fields>
<field>
<name>SEC</name>
<description>1588 Timer Second Comparison Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCH</name>
<description>1588 Timer Second Comparison High Register</description>
<addressOffset>0x0E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>SEC</name>
<description>1588 Timer Second Comparison Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFTSH</name>
<description>PTP Event Frame Transmitted Seconds High Register</description>
<addressOffset>0x0E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFRSH</name>
<description>PTP Event Frame Received Seconds High Register</description>
<addressOffset>0x0EC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFTSH</name>
<description>PTP Peer Event Frame Transmitted Seconds High Register</description>
<addressOffset>0x0F0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFRSH</name>
<description>PTP Peer Event Frame Received Seconds High Register</description>
<addressOffset>0x0F4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTLO</name>
<description>Octets Transmitted Low Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXO</name>
<description>Transmitted Octets</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTHI</name>
<description>Octets Transmitted High Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXO</name>
<description>Transmitted Octets</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FT</name>
<description>Frames Transmitted Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FTX</name>
<description>Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCFT</name>
<description>Broadcast Frames Transmitted Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>BFTX</name>
<description>Broadcast Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MFT</name>
<description>Multicast Frames Transmitted Register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MFTX</name>
<description>Multicast Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PFT</name>
<description>Pause Frames Transmitted Register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PFTX</name>
<description>Pause Frames Transmitted Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFT64</name>
<description>64 Byte Frames Transmitted Register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>64 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFT127</name>
<description>65 to 127 Byte Frames Transmitted Register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>65 to 127 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFT255</name>
<description>128 to 255 Byte Frames Transmitted Register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>128 to 255 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFT511</name>
<description>256 to 511 Byte Frames Transmitted Register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>256 to 511 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFT1023</name>
<description>512 to 1023 Byte Frames Transmitted Register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>512 to 1023 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFT1518</name>
<description>1024 to 1518 Byte Frames Transmitted Register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>1024 to 1518 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTBFT1518</name>
<description>Greater Than 1518 Byte Frames Transmitted Register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFTX</name>
<description>Greater than 1518 Byte Frames Transmitted without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TUR</name>
<description>Transmit Underruns Register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXUNR</name>
<description>Transmit Underruns</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCF</name>
<description>Single Collision Frames Register</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>SCOL</name>
<description>Single Collision</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCF</name>
<description>Multiple Collision Frames Register</description>
<addressOffset>0x13C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MCOL</name>
<description>Multiple Collision</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>EC</name>
<description>Excessive Collisions Register</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>XCOL</name>
<description>Excessive Collisions</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LC</name>
<description>Late Collisions Register</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LCOL</name>
<description>Late Collisions</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTF</name>
<description>Deferred Transmission Frames Register</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DEFT</name>
<description>Deferred Transmission</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSE</name>
<description>Carrier Sense Errors Register</description>
<addressOffset>0x14C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CSR</name>
<description>Carrier Sense Error</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>ORLO</name>
<description>Octets Received Low Received Register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXO</name>
<description>Received Octets</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ORHI</name>
<description>Octets Received High Received Register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXO</name>
<description>Received Octets</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FR</name>
<description>Frames Received Register</description>
<addressOffset>0x158</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FRX</name>
<description>Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCFR</name>
<description>Broadcast Frames Received Register</description>
<addressOffset>0x15C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>BFRX</name>
<description>Broadcast Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MFR</name>
<description>Multicast Frames Received Register</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MFRX</name>
<description>Multicast Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PFR</name>
<description>Pause Frames Received Register</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PFRX</name>
<description>Pause Frames Received Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFR64</name>
<description>64 Byte Frames Received Register</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>64 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFR127</name>
<description>65 to 127 Byte Frames Received Register</description>
<addressOffset>0x16C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>65 to 127 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFR255</name>
<description>128 to 255 Byte Frames Received Register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>128 to 255 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFR511</name>
<description>256 to 511 Byte Frames Received Register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>256 to 511 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFR1023</name>
<description>512 to 1023 Byte Frames Received Register</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>512 to 1023 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TBFR1518</name>
<description>1024 to 1518 Byte Frames Received Register</description>
<addressOffset>0x17C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>1024 to 1518 Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TMXBFR</name>
<description>1519 to Maximum Byte Frames Received Register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NFRX</name>
<description>1519 to Maximum Byte Frames Received without Error</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>UFR</name>
<description>Undersize Frames Received Register</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>UFRX</name>
<description>Undersize Frames Received</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR</name>
<description>Oversize Frames Received Register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>OFRX</name>
<description>Oversized Frames Received</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>JR</name>
<description>Jabbers Received Register</description>
<addressOffset>0x18C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>JRX</name>
<description>Jabbers Received</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCSE</name>
<description>Frame Check Sequence Errors Register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FCKR</name>
<description>Frame Check Sequence Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LFFE</name>
<description>Length Field Frame Errors Register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LFER</name>
<description>Length Field Frame Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSE</name>
<description>Receive Symbol Errors Register</description>
<addressOffset>0x198</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXSE</name>
<description>Receive Symbol Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>AE</name>
<description>Alignment Errors Register</description>
<addressOffset>0x19C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>AER</name>
<description>Alignment Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>RRE</name>
<description>Receive Resource Errors Register</description>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRER</name>
<description>Receive Resource Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROE</name>
<description>Receive Overrun Register</description>
<addressOffset>0x1A4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXOVR</name>
<description>Receive Overruns</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>IHCE</name>
<description>IP Header Checksum Errors Register</description>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>HCKER</name>
<description>IP Header Checksum Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TCE</name>
<description>TCP Checksum Errors Register</description>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TCKER</name>
<description>TCP Checksum Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>UCE</name>
<description>UDP Checksum Errors Register</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>UCKER</name>
<description>UDP Checksum Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISUBN</name>
<description>1588 Timer Increment Sub-nanoseconds Register</description>
<addressOffset>0x1BC</addressOffset>
<size>32</size>
<fields>
<field>
<name>LSBTIR</name>
<description>Lower Significant Bits of Timer Increment Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSH</name>
<description>1588 Timer Seconds High Register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<fields>
<field>
<name>TCS</name>
<description>Timer Count in Seconds</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSL</name>
<description>1588 Timer Seconds Low Register</description>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<fields>
<field>
<name>TCS</name>
<description>Timer Count in Seconds</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TN</name>
<description>1588 Timer Nanoseconds Register</description>
<addressOffset>0x1D4</addressOffset>
<size>32</size>
<fields>
<field>
<name>TNS</name>
<description>Timer Count in Nanoseconds</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>TA</name>
<description>1588 Timer Adjust Register</description>
<addressOffset>0x1D8</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ITDT</name>
<description>Increment/Decrement</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
<field>
<name>ADJ</name>
<description>Adjust 1588 Timer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TI</name>
<description>1588 Timer Increment Register</description>
<addressOffset>0x1DC</addressOffset>
<size>32</size>
<fields>
<field>
<name>CNS</name>
<description>Count Nanoseconds</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ACNS</name>
<description>Alternative Count Nanoseconds</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NIT</name>
<description>Number of Increments</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFTSL</name>
<description>PTP Event Frame Transmitted Seconds Low Register</description>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFTN</name>
<description>PTP Event Frame Transmitted Nanoseconds Register</description>
<addressOffset>0x1E4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFRSL</name>
<description>PTP Event Frame Received Seconds Low Register</description>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>EFRN</name>
<description>PTP Event Frame Received Nanoseconds Register</description>
<addressOffset>0x1EC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFTSL</name>
<description>PTP Peer Event Frame Transmitted Seconds Low Register</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFTN</name>
<description>PTP Peer Event Frame Transmitted Nanoseconds Register</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFRSL</name>
<description>PTP Peer Event Frame Received Seconds Low Register</description>
<addressOffset>0x1F8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PEFRN</name>
<description>PTP Peer Event Frame Received Nanoseconds Register</description>
<addressOffset>0x1FC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RUD</name>
<description>Register Update</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXLPI</name>
<description>Received LPI Transitions</description>
<addressOffset>0x270</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>COUNT</name>
<description>Count of RX LPI transitions (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXLPITIME</name>
<description>Received LPI Time</description>
<addressOffset>0x274</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LPITIME</name>
<description>Time in LPI (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXLPI</name>
<description>Transmit LPI Transitions</description>
<addressOffset>0x278</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>COUNT</name>
<description>Count of LPI transitions (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXLPITIME</name>
<description>Transmit LPI Time</description>
<addressOffset>0x27C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LPITIME</name>
<description>Time in LPI (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>ISRPQ[%s]</name>
<description>Interrupt Status Register Priority Queue (1..5)</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>TBQBAPQ[%s]</name>
<description>Transmit Buffer Queue Base Address Register Priority Queue (1..5)</description>
<addressOffset>0x440</addressOffset>
<size>32</size>
<fields>
<field>
<name>TXBQBA</name>
<description>Transmit Buffer Queue Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>RBQBAPQ[%s]</name>
<description>Receive Buffer Queue Base Address Register Priority Queue (1..5)</description>
<addressOffset>0x480</addressOffset>
<size>32</size>
<fields>
<field>
<name>RXBQBA</name>
<description>Receive Buffer Queue Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>RBSRPQ[%s]</name>
<description>Receive Buffer Size Register Priority Queue (1..5)</description>
<addressOffset>0x4A0</addressOffset>
<size>32</size>
<fields>
<field>
<name>RBS</name>
<description>Receive Buffer Size</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CBSCR</name>
<description>Credit-Based Shaping Control Register</description>
<addressOffset>0x4BC</addressOffset>
<size>32</size>
<fields>
<field>
<name>QBE</name>
<description>Queue B CBS Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QAE</name>
<description>Queue A CBS Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CBSISQA</name>
<description>Credit-Based Shaping IdleSlope Register for Queue A</description>
<addressOffset>0x4C0</addressOffset>
<size>32</size>
<fields>
<field>
<name>IS</name>
<description>IdleSlope</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CBSISQB</name>
<description>Credit-Based Shaping IdleSlope Register for Queue B</description>
<addressOffset>0x4C4</addressOffset>
<size>32</size>
<fields>
<field>
<name>IS</name>
<description>IdleSlope</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>ST1RPQ[%s]</name>
<description>Screening Type 1 Register Priority Queue</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<fields>
<field>
<name>QNB</name>
<description>Queue Number (0-5)</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DSTCM</name>
<description>Differentiated Services or Traffic Class Match</description>
<bitOffset>4</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>UDPM</name>
<description>UDP Port Match</description>
<bitOffset>12</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DSTCE</name>
<description>Differentiated Services or Traffic Class Match Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPE</name>
<description>UDP Port Match Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>ST2RPQ[%s]</name>
<description>Screening Type 2 Register Priority Queue</description>
<addressOffset>0x540</addressOffset>
<size>32</size>
<fields>
<field>
<name>QNB</name>
<description>Queue Number (0-5)</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>VLANP</name>
<description>VLAN Priority</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>VLANE</name>
<description>VLAN Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2ETH</name>
<description>Index of Screening Type 2 EtherType register x</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ETHE</name>
<description>EtherType Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPA</name>
<description>Index of Screening Type 2 Compare Word 0/Word 1 register x</description>
<bitOffset>13</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>COMPAE</name>
<description>Compare A Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPB</name>
<description>Index of Screening Type 2 Compare Word 0/Word 1 register x</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>COMPBE</name>
<description>Compare B Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPC</name>
<description>Index of Screening Type 2 Compare Word 0/Word 1 register x</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>COMPCE</name>
<description>Compare C Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>IERPQ[%s]</name>
<description>Interrupt Enable Register Priority Queue (1..5)</description>
<addressOffset>0x600</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>IDRPQ[%s]</name>
<description>Interrupt Disable Register Priority Queue (1..5)</description>
<addressOffset>0x620</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFC</name>
<description>Transmit Frame Corruption Due to AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>IMRPQ[%s]</name>
<description>Interrupt Mask Register Priority Queue (1..5)</description>
<addressOffset>0x640</addressOffset>
<size>32</size>
<fields>
<field>
<name>RCOMP</name>
<description>Receive Complete</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXUBR</name>
<description>RX Used Bit Read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RLEX</name>
<description>Retry Limit Exceeded or Late Collision</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB</name>
<description>AHB Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOMP</name>
<description>Transmit Complete</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVR</name>
<description>Receive Overrun</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRESP</name>
<description>HRESP Not OK</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>ST2ER[%s]</name>
<description>Screening Type 2 Ethertype Register</description>
<addressOffset>0x6E0</addressOffset>
<size>32</size>
<fields>
<field>
<name>COMPVAL</name>
<description>Ethertype Compare Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>24</dim>
<dimIncrement>8</dimIncrement>
<name>GMAC_ST2CW[%s]</name>
<description>Screening Type 2 Compare Word 0 Register</description>
<addressOffset>0x700</addressOffset>
<register>
<name>ST2CW0</name>
<description>Screening Type 2 Compare Word 0 Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>MASKVAL</name>
<description>Mask Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>COMPVAL</name>
<description>Compare Value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ST2CW1</name>
<description>Screening Type 2 Compare Word 1 Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>OFFSVAL</name>
<description>Offset Value in Bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>OFFSSTRT</name>
<description>Ethernet Frame Offset Start</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>OFFSSTRTSelect</name>
<enumeratedValue>
<name>FRAMESTART</name>
<description>Offset from the start of the frame</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ETHERTYPE</name>
<description>Offset from the byte after the EtherType field</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IP</name>
<description>Offset from the byte after the IP header field</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TCP_UDP</name>
<description>Offset from the byte after the TCP/UDP header field</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>GPBR</name>
<version>6378J</version>
<description>General Purpose Backup Registers</description>
<groupName>GPBR</groupName>
<prependToName>GPBR_</prependToName>
<baseAddress>0x400E1890</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>SYS_GPBR[%s]</name>
<description>General Purpose Backup Register 0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<fields>
<field>
<name>GPBR_VALUE</name>
<description>Value of GPBR x</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HSMCI</name>
<version>6449R</version>
<description>High Speed MultiMedia Card Interface</description>
<groupName>HSMCI</groupName>
<prependToName>HSMCI_</prependToName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xB58</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>HSMCI</name>
<value>18</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>MCIEN</name>
<description>Multi-Media Interface Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCIDIS</name>
<description>Multi-Media Interface Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWSEN</name>
<description>Power Save Mode Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWSDIS</name>
<description>Power Save Mode Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PWSDIV</name>
<description>Power Saving Divider</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RDPROOF</name>
<description>Read Proof Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPROOF</name>
<description>Write Proof Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBYTE</name>
<description>Force Byte Transfer</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PADV</name>
<description>Padding Value</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKODD</name>
<description>Clock divider is odd</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTOR</name>
<description>Data Timeout Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>DTOCYC</name>
<description>Data Timeout Cycle Number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTOMUL</name>
<description>Data Timeout Multiplier</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>DTOMULSelect</name>
<enumeratedValue>
<name>_1</name>
<description>DTOCYC</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_16</name>
<description>DTOCYC x 16</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_128</name>
<description>DTOCYC x 128</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_256</name>
<description>DTOCYC x 256</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024</name>
<description>DTOCYC x 1024</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_4096</name>
<description>DTOCYC x 4096</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_65536</name>
<description>DTOCYC x 65536</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_1048576</name>
<description>DTOCYC x 1048576</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDCR</name>
<description>SD/SDIO Card Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>SDCSEL</name>
<description>SDCard/SDIO Slot</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SDCSELSelect</name>
<enumeratedValue>
<name>SLOTA</name>
<description>Slot A is selected.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDCBUS</name>
<description>SDCard/SDIO Bus Width</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SDCBUSSelect</name>
<enumeratedValue>
<name>_1</name>
<description>1 bit</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_4</name>
<description>4 bits</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8</name>
<description>8 bits</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARGR</name>
<description>Argument Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>ARG</name>
<description>Command Argument</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMDR</name>
<description>Command Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CMDNB</name>
<description>Command Number</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>RSPTYP</name>
<description>Response Type</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>RSPTYPSelect</name>
<enumeratedValue>
<name>NORESP</name>
<description>No response</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_48_BIT</name>
<description>48-bit response</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_136_BIT</name>
<description>136-bit response</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>R1B</name>
<description>R1b response type</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPCMD</name>
<description>Special Command</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>SPCMDSelect</name>
<enumeratedValue>
<name>STD</name>
<description>Not a special CMD.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INIT</name>
<description>Initialization CMD: 74 clock cycles for initialization sequence.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNC</name>
<description>Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CE_ATA</name>
<description>CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IT_CMD</name>
<description>Interrupt command: Corresponds to the Interrupt Mode (CMD40).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IT_RESP</name>
<description>Interrupt response: Corresponds to the Interrupt Mode (CMD40).</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>BOR</name>
<description>Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EBO</name>
<description>End Boot Operation. This command allows the host processor to terminate the boot operation mode.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPDCMD</name>
<description>Open Drain Command</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>OPDCMDSelect</name>
<enumeratedValue>
<name>PUSHPULL</name>
<description>Push pull command.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPENDRAIN</name>
<description>Open drain command.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAXLAT</name>
<description>Max Latency for Command to Response</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MAXLATSelect</name>
<enumeratedValue>
<name>_5</name>
<description>5-cycle max latency.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>_64</name>
<description>64-cycle max latency.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRCMD</name>
<description>Transfer Command</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TRCMDSelect</name>
<enumeratedValue>
<name>NO_DATA</name>
<description>No data transfer</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_DATA</name>
<description>Start data transfer</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP_DATA</name>
<description>Stop data transfer</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRDIR</name>
<description>Transfer Direction</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRDIRSelect</name>
<enumeratedValue>
<name>WRITE</name>
<description>Write.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>READ</name>
<description>Read.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRTYP</name>
<description>Transfer Type</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TRTYPSelect</name>
<enumeratedValue>
<name>SINGLE</name>
<description>MMC/SD Card Single Block</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MULTIPLE</name>
<description>MMC/SD Card Multiple Block</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STREAM</name>
<description>MMC Stream</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>BYTE</name>
<description>SDIO Byte</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>BLOCK</name>
<description>SDIO Block</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOSPCMD</name>
<description>SDIO Special Command</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>IOSPCMDSelect</name>
<enumeratedValue>
<name>STD</name>
<description>Not an SDIO Special Command</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SUSPEND</name>
<description>SDIO Suspend Command</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESUME</name>
<description>SDIO Resume Command</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATACS</name>
<description>ATA with Command Completion Signal</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ATACSSelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal operation mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>COMPLETION</name>
<description>This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOOT_ACK</name>
<description>Boot Operation Acknowledge</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLKR</name>
<description>Block Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>BCNT</name>
<description>MMC/SDIO Block Count - SDIO Byte Count</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>BLKLEN</name>
<description>Data Block Length</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSTOR</name>
<description>Completion Signal Timeout Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSTOCYC</name>
<description>Completion Signal Timeout Cycle Number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CSTOMUL</name>
<description>Completion Signal Timeout Multiplier</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CSTOMULSelect</name>
<enumeratedValue>
<name>_1</name>
<description>CSTOCYC x 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_16</name>
<description>CSTOCYC x 16</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_128</name>
<description>CSTOCYC x 128</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_256</name>
<description>CSTOCYC x 256</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024</name>
<description>CSTOCYC x 1024</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_4096</name>
<description>CSTOCYC x 4096</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_65536</name>
<description>CSTOCYC x 65536</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_1048576</name>
<description>CSTOCYC x 1048576</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>RSPR[%s]</name>
<description>Response Register 0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RSP</name>
<description>Response</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<description>Receive Data Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATA</name>
<description>Data to Read</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<description>Transmit Data Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATA</name>
<description>Data to Write</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CMDRDY</name>
<description>Command Ready (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receiver Ready (cleared by reading HSMCI_RDR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready (cleared by writing in HSMCI_TDR)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKE</name>
<description>Data Block Ended (cleared on read)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIP</name>
<description>Data Transfer in Progress (cleared at the end of CRC16 calculation)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOTBUSY</name>
<description>HSMCI Not Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOIRQA</name>
<description>SDIO Interrupt for Slot A (cleared on read)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOWAIT</name>
<description>SDIO Read Wait Operation Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRCV</name>
<description>CE-ATA Completion Signal Received (cleared on read)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RINDE</name>
<description>Response Index Error (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDIRE</name>
<description>Response Direction Error (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCRCE</name>
<description>Response CRC Error (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RENDE</name>
<description>Response End Bit Error (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOE</name>
<description>Response Time-out Error (cleared by writing in HSMCI_CMDR)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCE</name>
<description>Data CRC Error (cleared on read)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTOE</name>
<description>Data Time-out Error (cleared on read)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSTOE</name>
<description>Completion Signal Time-out Error (cleared on read)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKOVRE</name>
<description>DMA Block Overrun Error (cleared on read)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEMPTY</name>
<description>FIFO empty flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRDONE</name>
<description>Transfer Done flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCV</name>
<description>Boot Operation Acknowledge Received (cleared on read)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCVE</name>
<description>Boot Operation Acknowledge Error (cleared on read)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CMDRDY</name>
<description>Command Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKE</name>
<description>Data Block Ended Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIP</name>
<description>Data Transfer in Progress Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOTBUSY</name>
<description>Data Not Busy Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOIRQA</name>
<description>SDIO Interrupt for Slot A Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOWAIT</name>
<description>SDIO Read Wait Operation Status Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRCV</name>
<description>Completion Signal Received Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RINDE</name>
<description>Response Index Error Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDIRE</name>
<description>Response Direction Error Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCRCE</name>
<description>Response CRC Error Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RENDE</name>
<description>Response End Bit Error Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOE</name>
<description>Response Time-out Error Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCE</name>
<description>Data CRC Error Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTOE</name>
<description>Data Time-out Error Interrupt Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSTOE</name>
<description>Completion Signal Timeout Error Interrupt Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKOVRE</name>
<description>DMA Block Overrun Error Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEMPTY</name>
<description>FIFO empty Interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRDONE</name>
<description>Transfer Done Interrupt enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCV</name>
<description>Boot Acknowledge Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCVE</name>
<description>Boot Acknowledge Error Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CMDRDY</name>
<description>Command Ready Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKE</name>
<description>Data Block Ended Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIP</name>
<description>Data Transfer in Progress Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOTBUSY</name>
<description>Data Not Busy Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOIRQA</name>
<description>SDIO Interrupt for Slot A Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOWAIT</name>
<description>SDIO Read Wait Operation Status Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRCV</name>
<description>Completion Signal received interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RINDE</name>
<description>Response Index Error Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDIRE</name>
<description>Response Direction Error Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCRCE</name>
<description>Response CRC Error Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RENDE</name>
<description>Response End Bit Error Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOE</name>
<description>Response Time-out Error Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCE</name>
<description>Data CRC Error Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTOE</name>
<description>Data Time-out Error Interrupt Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSTOE</name>
<description>Completion Signal Time out Error Interrupt Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKOVRE</name>
<description>DMA Block Overrun Error Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEMPTY</name>
<description>FIFO empty Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRDONE</name>
<description>Transfer Done Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCV</name>
<description>Boot Acknowledge Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCVE</name>
<description>Boot Acknowledge Error Interrupt Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Interrupt Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CMDRDY</name>
<description>Command Ready Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKE</name>
<description>Data Block Ended Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIP</name>
<description>Data Transfer in Progress Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOTBUSY</name>
<description>Data Not Busy Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOIRQA</name>
<description>SDIO Interrupt for Slot A Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOWAIT</name>
<description>SDIO Read Wait Operation Status Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRCV</name>
<description>Completion Signal Received Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RINDE</name>
<description>Response Index Error Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDIRE</name>
<description>Response Direction Error Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCRCE</name>
<description>Response CRC Error Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RENDE</name>
<description>Response End Bit Error Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOE</name>
<description>Response Time-out Error Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCE</name>
<description>Data CRC Error Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTOE</name>
<description>Data Time-out Error Interrupt Mask</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSTOE</name>
<description>Completion Signal Time-out Error Interrupt Mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLKOVRE</name>
<description>DMA Block Overrun Error Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEMPTY</name>
<description>FIFO Empty Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRDONE</name>
<description>Transfer Done Interrupt Mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCV</name>
<description>Boot Operation Acknowledge Received Interrupt Mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKRCVE</name>
<description>Boot Operation Acknowledge Error Interrupt Mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Interrupt Mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Interrupt Mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA</name>
<description>DMA Configuration Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHKSIZE</name>
<description>DMA Channel Read and Write Chunk Size</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CHKSIZESelect</name>
<enumeratedValue>
<name>_1</name>
<description>1 data available</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_2</name>
<description>2 data available</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_4</name>
<description>4 data available</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8</name>
<description>8 data available</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_16</name>
<description>16 data available</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Hardware Handshaking Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG</name>
<description>Configuration Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<fields>
<field>
<name>FIFOMODE</name>
<description>HSMCI Internal FIFO control mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FERRCTRL</name>
<description>Flow Error flag reset control mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSMODE</name>
<description>High Speed Mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSYNC</name>
<description>Synchronize on the last block</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protect Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protect Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x4D4349</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>256</dim>
<dimIncrement>4</dimIncrement>
<name>FIFO[%s]</name>
<description>FIFO Memory Aperture0 0</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATA</name>
<description>Data to Read or Data to Write</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2SC0</name>
<version>11241N</version>
<description>Inter-IC Sound Controller</description>
<groupName>I2SC</groupName>
<prependToName>I2SC_</prependToName>
<baseAddress>0x4008C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2SC0</name>
<value>69</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXEN</name>
<description>Receiver Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receiver Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN</name>
<description>Clocks Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKDIS</name>
<description>Clocks Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmitter Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>MODE</name>
<description>Inter-IC Sound Controller Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MODESelect</name>
<enumeratedValue>
<name>SLAVE</name>
<description>I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATALENGTH</name>
<description>Data Word Length</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>DATALENGTHSelect</name>
<enumeratedValue>
<name>_32_BITS</name>
<description>Data length is set to 32 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_24_BITS</name>
<description>Data length is set to 24 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_20_BITS</name>
<description>Data length is set to 20 bits</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_18_BITS</name>
<description>Data length is set to 18 bits</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BITS</name>
<description>Data length is set to 16 bits</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BITS_COMPACT</name>
<description>Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_BITS</name>
<description>Data length is set to 8 bits</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_BITS_COMPACT</name>
<description>Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXMONO</name>
<description>Receive Mono</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMA</name>
<description>Single or Multiple DMA Controller Channels for Receiver</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXLOOP</name>
<description>Loopback Test Mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMONO</name>
<description>Transmit Mono</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMA</name>
<description>Single or Multiple DMA Controller Channels for Transmitter</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSAME</name>
<description>Transmit Data when Underrun</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMCKDIV</name>
<description>Selected Clock to I2SC Master Clock Ratio</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>IMCKFS</name>
<description>Master Clock to fs Ratio</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues>
<name>IMCKFSSelect</name>
<enumeratedValue>
<name>M2SF32</name>
<description>Sample frequency ratio set to 32</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF64</name>
<description>Sample frequency ratio set to 64</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF96</name>
<description>Sample frequency ratio set to 96</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF128</name>
<description>Sample frequency ratio set to 128</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF192</name>
<description>Sample frequency ratio set to 192</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF256</name>
<description>Sample frequency ratio set to 256</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF384</name>
<description>Sample frequency ratio set to 384</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF512</name>
<description>Sample frequency ratio set to 512</description>
<value>0xF</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF768</name>
<description>Sample frequency ratio set to 768</description>
<value>0x17</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF1024</name>
<description>Sample frequency ratio set to 1024</description>
<value>0x1F</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF1536</name>
<description>Sample frequency ratio set to 1536</description>
<value>0x2F</value>
</enumeratedValue>
<enumeratedValue>
<name>M2SF2048</name>
<description>Sample frequency ratio set to 2048</description>
<value>0x3F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IMCKMODE</name>
<description>Master Clock Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWS</name>
<description>I2SC_WS Slot Width</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXEN</name>
<description>Receiver Enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOR</name>
<description>Receive Overrun</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underrun</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORCH</name>
<description>Receive Overrun Channel</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXURCH</name>
<description>Transmit Underrun Channel</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>Status Clear Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXOR</name>
<description>Receive Overrun Status Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underrun Status Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORCH</name>
<description>Receive Overrun Per Channel Status Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXURCH</name>
<description>Transmit Underrun Per Channel Status Clear</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SSR</name>
<description>Status Set Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXOR</name>
<description>Receive Overrun Status Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underrun Status Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORCH</name>
<description>Receive Overrun Per Channel Status Set</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXURCH</name>
<description>Transmit Underrun Per Channel Status Set</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOR</name>
<description>Receiver Overrun Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOR</name>
<description>Receiver Overrun Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underflow Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOR</name>
<description>Receiver Overrun Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUR</name>
<description>Transmit Underflow Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RHR</name>
<description>Receiver Holding Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RHR</name>
<description>Receiver Holding Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmitter Holding Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>THR</name>
<description>Transmitter Holding Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ICM</name>
<version>11105H</version>
<description>Integrity Check Monitor</description>
<groupName>ICM</groupName>
<prependToName>ICM_</prependToName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x58</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ICM</name>
<value>32</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>Configuration Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>WBDIS</name>
<description>Write Back Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOMDIS</name>
<description>End of Monitoring Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLBDIS</name>
<description>Secondary List Branching Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBC</name>
<description>Bus Burden Control</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ASCD</name>
<description>Automatic Switch To Compare Digest</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUALBUFF</name>
<description>Dual Input Buffer</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIHASH</name>
<description>User Initial Hash Value</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UALGO</name>
<description>User SHA Algorithm</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>UALGOSelect</name>
<enumeratedValue>
<name>SHA1</name>
<description>SHA1 algorithm processed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SHA256</name>
<description>SHA256 algorithm processed</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SHA224</name>
<description>SHA224 algorithm processed</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>Control Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ENABLE</name>
<description>ICM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE</name>
<description>ICM Disable Register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REHASH</name>
<description>Recompute Internal Hash</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RMDIS</name>
<description>Region Monitoring Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RMEN</name>
<description>Region Monitoring Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ENABLE</name>
<description>ICM Controller Enable Register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RAWRMDIS</name>
<description>Region Monitoring Disabled Raw Status</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RMDIS</name>
<description>Region Monitoring Disabled Status</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RHC</name>
<description>Region Hash Completed Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RDM</name>
<description>Region Digest Mismatch Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RBE</name>
<description>Region Bus Error Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RWC</name>
<description>Region Wrap Condition detected Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REC</name>
<description>Region End bit Condition Detected Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RSU</name>
<description>Region Status Updated Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Undefined Register Access Detection Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RHC</name>
<description>Region Hash Completed Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RDM</name>
<description>Region Digest Mismatch Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RBE</name>
<description>Region Bus Error Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RWC</name>
<description>Region Wrap Condition Detected Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REC</name>
<description>Region End bit Condition detected Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RSU</name>
<description>Region Status Updated Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Undefined Register Access Detection Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RHC</name>
<description>Region Hash Completed Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RDM</name>
<description>Region Digest Mismatch Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RBE</name>
<description>Region Bus Error Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RWC</name>
<description>Region Wrap Condition Detected Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REC</name>
<description>Region End bit Condition Detected Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RSU</name>
<description>Region Status Updated Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Undefined Register Access Detection Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RHC</name>
<description>Region Hash Completed</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RDM</name>
<description>Region Digest Mismatch</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RBE</name>
<description>Region Bus Error</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RWC</name>
<description>Region Wrap Condition Detected</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REC</name>
<description>Region End bit Condition Detected</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RSU</name>
<description>Region Status Updated Detected</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>URAD</name>
<description>Undefined Register Access Detection Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>UASR</name>
<description>Undefined Access Status Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>URAT</name>
<description>Undefined Register Access Trace</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>URATSelect</name>
<enumeratedValue>
<name>UNSPEC_STRUCT_MEMBER</name>
<description>Unspecified structure member set to one detected when the descriptor is loaded.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ICM_CFG_MODIFIED</name>
<description>ICM_CFG modified during active monitoring.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ICM_DSCR_MODIFIED</name>
<description>ICM_DSCR modified during active monitoring.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ICM_HASH_MODIFIED</name>
<description>ICM_HASH modified during active monitoring</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>READ_ACCESS</name>
<description>Write-only register read access</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSCR</name>
<description>Region Descriptor Area Start Address Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>DASA</name>
<description>Descriptor Area Start Address</description>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>HASH</name>
<description>Region Hash Area Start Address Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<fields>
<field>
<name>HASA</name>
<description>Hash Area Start Address</description>
<bitOffset>7</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>UIHVAL[%s]</name>
<description>User Initial Hash Value 0 Register 0</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>VAL</name>
<description>Initial Hash Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ISI</name>
<version>6350K</version>
<description>Image Sensor Interface</description>
<groupName>ISI</groupName>
<prependToName>ISI_</prependToName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ISI</name>
<value>59</value>
</interrupt>
<registers>
<register>
<name>CFG1</name>
<description>ISI Configuration 1 Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>HSYNC_POL</name>
<description>Horizontal Synchronization Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_POL</name>
<description>Vertical Synchronization Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIXCLK_POL</name>
<description>Pixel Clock Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GRAYLE</name>
<description>Grayscale Little Endian</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EMB_SYNC</name>
<description>Embedded Synchronization</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_SYNC</name>
<description>Embedded Synchronization Correction</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRATE</name>
<description>Frame Rate [0..7]</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DISCR</name>
<description>Disable Codec Request</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FULL</name>
<description>Full Mode is Allowed</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THMASK</name>
<description>Threshold Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>THMASKSelect</name>
<enumeratedValue>
<name>BEATS_4</name>
<description>Only 4 beats AHB burst allowed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BEATS_8</name>
<description>Only 4 and 8 beats AHB burst allowed</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BEATS_16</name>
<description>4, 8 and 16 beats AHB burst allowed</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLD</name>
<description>Start of Line Delay</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SFD</name>
<description>Start of Frame Delay</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<description>ISI Configuration 2 Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>IM_VSIZE</name>
<description>Vertical Size of the Image Sensor [0..2047]</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>GS_MODE</name>
<description>Grayscale Pixel Format Mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RGB_MODE</name>
<description>RGB Input Mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GRAYSCALE</name>
<description>Grayscale Mode Format Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RGB_SWAP</name>
<description>RGB Format Swap Mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COL_SPACE</name>
<description>Color Space for the Image Data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM_HSIZE</name>
<description>Horizontal Size of the Image Sensor [0..2047]</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>YCC_SWAP</name>
<description>YCrCb Format Swap Mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>YCC_SWAPSelect</name>
<enumeratedValue>
<name>DEFAULT</name>
<description>Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RGB_CFG</name>
<description>RGB Pixel Mapping Configuration</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>RGB_CFGSelect</name>
<enumeratedValue>
<name>DEFAULT</name>
<description>Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSIZE</name>
<description>ISI Preview Size Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>PREV_VSIZE</name>
<description>Vertical Size for the Preview Path</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>PREV_HSIZE</name>
<description>Horizontal Size for the Preview Path</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDECF</name>
<description>ISI Preview Decimation Factor Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>DEC_FACTOR</name>
<description>Decimation Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>Y2R_SET0</name>
<description>ISI Color Space Conversion YCrCb To RGB Set 0 Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>C0</name>
<description>Color Space Conversion Matrix Coefficient C0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>C1</name>
<description>Color Space Conversion Matrix Coefficient C1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>C2</name>
<description>Color Space Conversion Matrix Coefficient C2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>C3</name>
<description>Color Space Conversion Matrix Coefficient C3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>Y2R_SET1</name>
<description>ISI Color Space Conversion YCrCb To RGB Set 1 Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>C4</name>
<description>Color Space Conversion Matrix Coefficient C4</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>Yoff</name>
<description>Color Space Conversion Luminance Default Offset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Croff</name>
<description>Color Space Conversion Red Chrominance Default Offset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Cboff</name>
<description>Color Space Conversion Blue Chrominance Default Offset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R2Y_SET0</name>
<description>ISI Color Space Conversion RGB To YCrCb Set 0 Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>C0</name>
<description>Color Space Conversion Matrix Coefficient C0</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C1</name>
<description>Color Space Conversion Matrix Coefficient C1</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C2</name>
<description>Color Space Conversion Matrix Coefficient C2</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>Roff</name>
<description>Color Space Conversion Red Component Offset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R2Y_SET1</name>
<description>ISI Color Space Conversion RGB To YCrCb Set 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>C3</name>
<description>Color Space Conversion Matrix Coefficient C3</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C4</name>
<description>Color Space Conversion Matrix Coefficient C4</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C5</name>
<description>Color Space Conversion Matrix Coefficient C5</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>Goff</name>
<description>Color Space Conversion Green Component Offset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R2Y_SET2</name>
<description>ISI Color Space Conversion RGB To YCrCb Set 2 Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<fields>
<field>
<name>C6</name>
<description>Color Space Conversion Matrix Coefficient C6</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C7</name>
<description>Color Space Conversion Matrix Coefficient C7</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>C8</name>
<description>Color Space Conversion Matrix Coefficient C8</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>Boff</name>
<description>Color Space Conversion Blue Component Offset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<description>ISI Control Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ISI_EN</name>
<description>ISI Module Enable Request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISI_DIS</name>
<description>ISI Module Disable Request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISI_SRST</name>
<description>ISI Software Reset Request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISI_CDC</name>
<description>ISI Codec Request</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>ISI Status Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ENABLE</name>
<description>Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_DONE</name>
<description>Module Disable Request has Terminated (cleared on read)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRST</name>
<description>Module Software Reset Request has Terminated (cleared on read)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDC_PND</name>
<description>Pending Codec Request</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>Vertical Synchronization (cleared on read)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXFR_DONE</name>
<description>Preview DMA Transfer has Terminated (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CXFR_DONE</name>
<description>Codec DMA Transfer has Terminated (cleared on read)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIP</name>
<description>Synchronization in Progress</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_OVR</name>
<description>Preview Datapath Overflow (cleared on read)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_OVR</name>
<description>Codec Datapath Overflow (cleared on read)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_ERR</name>
<description>CRC Synchronization Error (cleared on read)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FR_OVR</name>
<description>Frame Rate Overrun (cleared on read)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>ISI Interrupt Enable Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DIS_DONE</name>
<description>Disable Done Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRST</name>
<description>Software Reset Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>Vertical Synchronization Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXFR_DONE</name>
<description>Preview DMA Transfer Done Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CXFR_DONE</name>
<description>Codec DMA Transfer Done Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_OVR</name>
<description>Preview Datapath Overflow Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_OVR</name>
<description>Codec Datapath Overflow Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_ERR</name>
<description>Embedded Synchronization CRC Error Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FR_OVR</name>
<description>Frame Rate Overflow Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>ISI Interrupt Disable Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DIS_DONE</name>
<description>Disable Done Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRST</name>
<description>Software Reset Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>Vertical Synchronization Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXFR_DONE</name>
<description>Preview DMA Transfer Done Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CXFR_DONE</name>
<description>Codec DMA Transfer Done Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_OVR</name>
<description>Preview Datapath Overflow Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_OVR</name>
<description>Codec Datapath Overflow Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_ERR</name>
<description>Embedded Synchronization CRC Error Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FR_OVR</name>
<description>Frame Rate Overflow Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>ISI Interrupt Mask Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DIS_DONE</name>
<description>Module Disable Operation Completed</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRST</name>
<description>Software Reset Completed</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>Vertical Synchronization</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXFR_DONE</name>
<description>Preview DMA Transfer Completed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CXFR_DONE</name>
<description>Codec DMA Transfer Completed</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_OVR</name>
<description>Preview FIFO Overflow</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_OVR</name>
<description>Codec FIFO Overflow</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_ERR</name>
<description>CRC Synchronization Error</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FR_OVR</name>
<description>Frame Rate Overrun</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_CHER</name>
<description>DMA Channel Enable Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P_CH_EN</name>
<description>Preview Channel Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_CH_EN</name>
<description>Codec Channel Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_CHDR</name>
<description>DMA Channel Disable Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P_CH_DIS</name>
<description>Preview Channel Disable Request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_CH_DIS</name>
<description>Codec Channel Disable Request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_CHSR</name>
<description>DMA Channel Status Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P_CH_S</name>
<description>Preview DMA Channel Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_CH_S</name>
<description>Code DMA Channel Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_P_ADDR</name>
<description>DMA Preview Base Address Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<fields>
<field>
<name>P_ADDR</name>
<description>Preview Image Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_P_CTRL</name>
<description>DMA Preview Control Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<fields>
<field>
<name>P_FETCH</name>
<description>Descriptor Fetch Control Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_WB</name>
<description>Descriptor Writeback Control Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_IEN</name>
<description>Transfer Done Flag Control</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P_DONE</name>
<description>Preview Transfer Done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_P_DSCR</name>
<description>DMA Preview Descriptor Address Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<fields>
<field>
<name>P_DSCR</name>
<description>Preview Descriptor Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_C_ADDR</name>
<description>DMA Codec Base Address Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<fields>
<field>
<name>C_ADDR</name>
<description>Codec Image Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_C_CTRL</name>
<description>DMA Codec Control Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<fields>
<field>
<name>C_FETCH</name>
<description>Descriptor Fetch Control Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_WB</name>
<description>Descriptor Writeback Control Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_IEN</name>
<description>Transfer Done Flag Control</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C_DONE</name>
<description>Codec Transfer Done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_C_DSCR</name>
<description>DMA Codec Descriptor Address Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<fields>
<field>
<name>C_DSCR</name>
<description>Codec Descriptor Base Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key Password</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x495349</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MATRIX</name>
<version>11282L</version>
<description>AHB Bus Matrix</description>
<groupName>MATRIX</groupName>
<prependToName>MATRIX_</prependToName>
<baseAddress>0x40088000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1EC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>13</dim>
<dimIncrement>4</dimIncrement>
<name>MCFG[%s]</name>
<description>Master Configuration Register 0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<fields>
<field>
<name>ULBT</name>
<description>Undefined Length Burst Type</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>ULBTSelect</name>
<enumeratedValue>
<name>UNLTD_LENGTH</name>
<description>Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SINGLE_ACCESS</name>
<description>Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_4BEAT_BURST</name>
<description>4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8BEAT_BURST</name>
<description>8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_16BEAT_BURST</name>
<description>16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32BEAT_BURST</name>
<description>32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_64BEAT_BURST</name>
<description>64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_128BEAT_BURST</name>
<description>128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>9</dim>
<dimIncrement>4</dimIncrement>
<name>SCFG[%s]</name>
<description>Slave Configuration Register 0</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<fields>
<field>
<name>SLOT_CYCLE</name>
<description>Maximum Bus Grant Duration for Masters</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DEFMSTR_TYPE</name>
<description>Default Master Type</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DEFMSTR_TYPESelect</name>
<enumeratedValue>
<name>NONE</name>
<description>No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LAST</name>
<description>Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FIXED</name>
<description>Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIXED_DEFMSTR</name>
<description>Fixed Default Master</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>9</dim>
<dimIncrement>8</dimIncrement>
<name>MATRIX_PR[%s]</name>
<description>Priority Register A for Slave 0</description>
<addressOffset>0x0080</addressOffset>
<register>
<name>PRAS</name>
<description>Priority Register A for Slave 0</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>M0PR</name>
<description>Master 0 Priority</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M1PR</name>
<description>Master 1 Priority</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M2PR</name>
<description>Master 2 Priority</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M3PR</name>
<description>Master 3 Priority</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M4PR</name>
<description>Master 4 Priority</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M5PR</name>
<description>Master 5 Priority</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M6PR</name>
<description>Master 6 Priority</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M7PR</name>
<description>Master 7 Priority</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRBS</name>
<description>Priority Register B for Slave 0</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>M8PR</name>
<description>Master 8 Priority</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M9PR</name>
<description>Master 9 Priority</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M10PR</name>
<description>Master 10 Priority</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M11PR</name>
<description>Master 11 Priority</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>M12PR</name>
<description>Master 12 Priority</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>MRCR</name>
<description>Master Remap Control Register</description>
<addressOffset>0x0100</addressOffset>
<size>32</size>
<fields>
<field>
<name>RCB0</name>
<description>Remap Command Bit for Master 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB1</name>
<description>Remap Command Bit for Master 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB2</name>
<description>Remap Command Bit for Master 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB3</name>
<description>Remap Command Bit for Master 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB4</name>
<description>Remap Command Bit for Master 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB5</name>
<description>Remap Command Bit for Master 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB6</name>
<description>Remap Command Bit for Master 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB7</name>
<description>Remap Command Bit for Master 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB8</name>
<description>Remap Command Bit for Master 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB9</name>
<description>Remap Command Bit for Master 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB10</name>
<description>Remap Command Bit for Master 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB11</name>
<description>Remap Command Bit for Master 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCB12</name>
<description>Remap Command Bit for Master 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCFG_CAN0</name>
<description>CAN0 Configuration Register</description>
<addressOffset>0x0110</addressOffset>
<size>32</size>
<fields>
<field>
<name>CAN0DMABA</name>
<description>CAN0 DMA Base Address</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCFG_SYSIO</name>
<description>System I/O and CAN1 Configuration Register</description>
<addressOffset>0x0114</addressOffset>
<size>32</size>
<fields>
<field>
<name>SYSIO4</name>
<description>PB4 or TDI Assignment</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSIO5</name>
<description>PB5 or TDO/TRACESWO Assignment</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSIO6</name>
<description>PB6 or TMS/SWDIO Assignment</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSIO7</name>
<description>PB7 or TCK/SWCLK Assignment</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSIO12</name>
<description>PB12 or ERASE Assignment</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAN1DMABA</name>
<description>CAN1 DMA Base Address</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCFG_PCCR</name>
<description>Peripheral Clock Configuration Register</description>
<addressOffset>0x0118</addressOffset>
<size>32</size>
<fields>
<field>
<name>TC0CC</name>
<description>TC0 Clock Configuration</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SC0CC</name>
<description>I2SC0 Clock Configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SC1CC</name>
<description>I2SC1 Clock Configuration</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCFG_DYNCKG</name>
<description>Dynamic Clock Gating Register</description>
<addressOffset>0x011C</addressOffset>
<size>32</size>
<fields>
<field>
<name>MATCKG</name>
<description>MATRIX Dynamic Clock Gating</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRIDCKG</name>
<description>Bridge Dynamic Clock Gating Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFCCKG</name>
<description>EFC Dynamic Clock Gating Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCFG_SMCNFCS</name>
<description>SMC NAND Flash Chip Select Configuration Register</description>
<addressOffset>0x0124</addressOffset>
<size>32</size>
<fields>
<field>
<name>SMC_NFCS0</name>
<description>SMC NAND Flash Chip Select 0 Assignment</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC_NFCS1</name>
<description>SMC NAND Flash Chip Select 1 Assignment</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC_NFCS2</name>
<description>SMC NAND Flash Chip Select 2 Assignment</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC_NFCS3</name>
<description>SMC NAND Flash Chip Select 3 Assignment</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDRAMEN</name>
<description>SDRAM Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0x01E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x4D4154</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0x01E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCAN0</name>
<version>11273N</version>
<description>Controller Area Network</description>
<groupName>MCAN</groupName>
<prependToName>MCAN_</prependToName>
<baseAddress>0x40030000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MCAN0_INT0</name>
<value>35</value>
</interrupt>
<interrupt>
<name>MCAN0_INT1</name>
<value>36</value>
</interrupt>
<registers>
<register>
<name>CREL</name>
<description>Core Release Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DAY</name>
<description>Timestamp Day</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MON</name>
<description>Timestamp Month</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>Timestamp Year</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SUBSTEP</name>
<description>Sub-step of Core Release</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STEP</name>
<description>Step of Core Release</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REL</name>
<description>Core Release</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENDN</name>
<description>Endian Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ETV</name>
<description>Endianness Test Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CUST</name>
<description>Customer Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSV</name>
<description>Customer-specific Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DBTP</name>
<description>Data Bit Timing and Prescaler Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>DSJW</name>
<description>Data (Re) Synchronization Jump Width</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DTSEG2</name>
<description>Data Time Segment After Sample Point</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG1</name>
<description>Data Time Segment Before Sample Point</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBRP</name>
<description>Data Bit Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TDC</name>
<description>Transmitter Delay Compensation</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TDCSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Transmitter Delay Compensation disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Transmitter Delay Compensation enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TEST</name>
<description>Test Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>LBCK</name>
<description>Loop Back Mode (read/write)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LBCKSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Reset value. Loop Back mode is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Loop Back mode is enabled (see Section 6.1.9).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Control of Transmit Pin (read/write)</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TXSelect</name>
<enumeratedValue>
<name>RESET</name>
<description>Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SAMPLE_POINT_MONITORING</name>
<description>Sample Point can be monitored at pin CANTX.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DOMINANT</name>
<description>Dominant ('0') level at pin CANTX.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RECESSIVE</name>
<description>Recessive ('1') at pin CANTX.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RX</name>
<description>Receive Pin (read-only)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RWD</name>
<description>RAM Watchdog Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>WDC</name>
<description>Watchdog Configuration (read/write)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WDV</name>
<description>Watchdog Value (read-only)</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCCR</name>
<description>CC Control Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>INIT</name>
<description>Initialization (read/write)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INITSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Initialization is started.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCE</name>
<description>Configuration Change Enable (read/write, write protection)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CCESelect</name>
<enumeratedValue>
<name>PROTECTED</name>
<description>The processor has no write access to the protected configuration registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONFIGURABLE</name>
<description>The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1').</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASM</name>
<description>Restricted Operation Mode (read/write, write protection against '1')</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ASMSelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal CAN operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESTRICTED</name>
<description>Restricted Operation mode active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSA</name>
<description>Clock Stop Acknowledge (read-only)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Clock Stop Request (read/write)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CSRSelect</name>
<enumeratedValue>
<name>NO_CLOCK_STOP</name>
<description>No clock stop is requested.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCK_STOP</name>
<description>Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MON</name>
<description>Bus Monitoring Mode (read/write, write protection against '1')</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MONSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Bus Monitoring mode is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Bus Monitoring mode is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAR</name>
<description>Disable Automatic Retransmission (read/write, write protection)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DARSelect</name>
<enumeratedValue>
<name>AUTO_RETX</name>
<description>Automatic retransmission of messages not transmitted successfully enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_AUTO_RETX</name>
<description>Automatic retransmission disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEST</name>
<description>Test Mode Enable (read/write, write protection against '1')</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TESTSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal operation, MCAN_TEST register holds reset values.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Test mode, write access to MCAN_TEST register enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDOE</name>
<description>CAN FD Operation Enable (read/write, write protection)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FDOESelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>FD operation disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>FD operation enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRSE</name>
<description>Bit Rate Switching Enable (read/write, write protection)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BRSESelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Bit rate switching for transmissions disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Bit rate switching for transmissions enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PXHD</name>
<description>Protocol Exception Event Handling (read/write, write protection)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFBI</name>
<description>Edge Filtering during Bus Integration (read/write, write protection)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXP</name>
<description>Transmit Pause (read/write, write protection)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NISO</name>
<description>Non-ISO Operation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NBTP</name>
<description>Nominal Bit Timing and Prescaler Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>NTSEG2</name>
<description>Nominal Time Segment After Sample Point</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NTSEG1</name>
<description>Nominal Time Segment Before Sample Point</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NBRP</name>
<description>Nominal Bit Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NSJW</name>
<description>Nominal (Re) Synchronization Jump Width</description>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSCC</name>
<description>Timestamp Counter Configuration Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<fields>
<field>
<name>TSS</name>
<description>Timestamp Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TSSSelect</name>
<enumeratedValue>
<name>ALWAYS_0</name>
<description>Timestamp counter value always 0x0000</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TCP_INC</name>
<description>Timestamp counter value incremented according to TCP</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXT_TIMESTAMP</name>
<description>External timestamp counter value used</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCP</name>
<description>Timestamp Counter Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSCV</name>
<description>Timestamp Counter Value Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<fields>
<field>
<name>TSC</name>
<description>Timestamp Counter (cleared on write)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOCC</name>
<description>Timeout Counter Configuration Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<fields>
<field>
<name>ETOC</name>
<description>Enable Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ETOCSelect</name>
<enumeratedValue>
<name>NO_TIMEOUT</name>
<description>Timeout Counter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TOS_CONTROLLED</name>
<description>Timeout Counter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOS</name>
<description>Timeout Select</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TOSSelect</name>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>Continuous operation</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_EV_TIMEOUT</name>
<description>Timeout controlled by Tx Event FIFO</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RX0_EV_TIMEOUT</name>
<description>Timeout controlled by Receive FIFO 0</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RX1_EV_TIMEOUT</name>
<description>Timeout controlled by Receive FIFO 1</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOP</name>
<description>Timeout Period</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOCV</name>
<description>Timeout Counter Value Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<fields>
<field>
<name>TOC</name>
<description>Timeout Counter (cleared on write)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECR</name>
<description>Error Counter Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TEC</name>
<description>Transmit Error Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>REC</name>
<description>Receive Error Counter</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RP</name>
<description>Receive Error Passive</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEL</name>
<description>CAN Error Logging (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<description>Protocol Status Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LEC</name>
<description>Last Error Code (set to 111 on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>LECSelect</name>
<enumeratedValue>
<name>NO_ERROR</name>
<description>No error occurred since LEC has been reset by successful reception or transmission.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STUFF_ERROR</name>
<description>More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FORM_ERROR</name>
<description>A fixed format part of a received frame has the wrong format.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_ERROR</name>
<description>The message transmitted by the MCAN was not acknowledged by another node.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT1_ERROR</name>
<description>During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT0_ERROR</name>
<description>During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_ERROR</name>
<description>The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACT</name>
<description>Activity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ACTSelect</name>
<enumeratedValue>
<name>SYNCHRONIZING</name>
<description>Node is synchronizing on CAN communication</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDLE</name>
<description>Node is neither receiver nor transmitter</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVER</name>
<description>Node is operating as receiver</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMITTER</name>
<description>Node is operating as transmitter</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLEC</name>
<description>Data Phase Last Error Code (set to 111 on read)</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RESI</name>
<description>ESI Flag of Last Received CAN FD Message (cleared on read)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBRS</name>
<description>BRS Flag of Last Received CAN FD Message (cleared on read)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFDF</name>
<description>Received a CAN FD Message (cleared on read)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXE</name>
<description>Protocol Exception Event (cleared on read)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCV</name>
<description>Transmitter Delay Compensation Value</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDCR</name>
<description>Transmit Delay Compensation Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<fields>
<field>
<name>TDCF</name>
<description>Transmitter Delay Compensation Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TDCO</name>
<description>Transmitter Delay Compensation Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IR</name>
<description>Interrupt Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<fields>
<field>
<name>RF0N</name>
<description>Receive FIFO 0 New Message</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0W</name>
<description>Receive FIFO 0 Watermark Reached</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0F</name>
<description>Receive FIFO 0 Full</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Receive FIFO 0 Message Lost</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1N</name>
<description>Receive FIFO 1 New Message</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1W</name>
<description>Receive FIFO 1 Watermark Reached</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1F</name>
<description>Receive FIFO 1 Full</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Receive FIFO 1 Message Lost</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPM</name>
<description>High Priority Message</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>Transmission Completed</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transmission Cancellation Finished</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFE</name>
<description>Tx FIFO Empty</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFN</name>
<description>Tx Event FIFO New Entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFW</name>
<description>Tx Event FIFO Watermark Reached</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFF</name>
<description>Tx Event FIFO Full</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element Lost</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSW</name>
<description>Timestamp Wraparound</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAF</name>
<description>Message RAM Access Failure</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOO</name>
<description>Timeout Occurred</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRX</name>
<description>Message stored to Dedicated Receive Buffer</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELO</name>
<description>Error Logging Overflow</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDI</name>
<description>Watchdog Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>Protocol Error in Arbitration Phase</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PED</name>
<description>Protocol Error in Data Phase</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARA</name>
<description>Access to Reserved Address</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IE</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<fields>
<field>
<name>RF0NE</name>
<description>Receive FIFO 0 New Message Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WE</name>
<description>Receive FIFO 0 Watermark Reached Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FE</name>
<description>Receive FIFO 0 Full Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LE</name>
<description>Receive FIFO 0 Message Lost Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NE</name>
<description>Receive FIFO 1 New Message Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WE</name>
<description>Receive FIFO 1 Watermark Reached Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FE</name>
<description>Receive FIFO 1 Full Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LE</name>
<description>Receive FIFO 1 Message Lost Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPME</name>
<description>High Priority Message Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCE</name>
<description>Transmission Completed Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFE</name>
<description>Transmission Cancellation Finished Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFEE</name>
<description>Tx FIFO Empty Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNE</name>
<description>Tx Event FIFO New Entry Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWE</name>
<description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFE</name>
<description>Tx Event FIFO Full Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLE</name>
<description>Tx Event FIFO Event Lost Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWE</name>
<description>Timestamp Wraparound Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFE</name>
<description>Message RAM Access Failure Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOE</name>
<description>Timeout Occurred Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXE</name>
<description>Message stored to Dedicated Receive Buffer Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOE</name>
<description>Error Logging Overflow Interrupt Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPE</name>
<description>Error Passive Interrupt Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWE</name>
<description>Warning Status Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOE</name>
<description>Bus_Off Status Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIE</name>
<description>Watchdog Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAE</name>
<description>Protocol Error in Arbitration Phase Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDE</name>
<description>Protocol Error in Data Phase Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAE</name>
<description>Access to Reserved Address Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ILS</name>
<description>Interrupt Line Select Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<fields>
<field>
<name>RF0NL</name>
<description>Receive FIFO 0 New Message Interrupt Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WL</name>
<description>Receive FIFO 0 Watermark Reached Interrupt Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FL</name>
<description>Receive FIFO 0 Full Interrupt Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LL</name>
<description>Receive FIFO 0 Message Lost Interrupt Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NL</name>
<description>Receive FIFO 1 New Message Interrupt Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WL</name>
<description>Receive FIFO 1 Watermark Reached Interrupt Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FL</name>
<description>Receive FIFO 1 Full Interrupt Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LL</name>
<description>Receive FIFO 1 Message Lost Interrupt Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPML</name>
<description>High Priority Message Interrupt Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCL</name>
<description>Transmission Completed Interrupt Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFL</name>
<description>Transmission Cancellation Finished Interrupt Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFEL</name>
<description>Tx FIFO Empty Interrupt Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNL</name>
<description>Tx Event FIFO New Entry Interrupt Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWL</name>
<description>Tx Event FIFO Watermark Reached Interrupt Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFL</name>
<description>Tx Event FIFO Full Interrupt Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLL</name>
<description>Tx Event FIFO Event Lost Interrupt Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWL</name>
<description>Timestamp Wraparound Interrupt Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFL</name>
<description>Message RAM Access Failure Interrupt Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOL</name>
<description>Timeout Occurred Interrupt Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXL</name>
<description>Message stored to Dedicated Receive Buffer Interrupt Line</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOL</name>
<description>Error Logging Overflow Interrupt Line</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPL</name>
<description>Error Passive Interrupt Line</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWL</name>
<description>Warning Status Interrupt Line</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOL</name>
<description>Bus_Off Status Interrupt Line</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIL</name>
<description>Watchdog Interrupt Line</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAL</name>
<description>Protocol Error in Arbitration Phase Line</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDL</name>
<description>Protocol Error in Data Phase Line</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAL</name>
<description>Access to Reserved Address Line</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ILE</name>
<description>Interrupt Line Enable Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<fields>
<field>
<name>EINT0</name>
<description>Enable Interrupt Line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EINT1</name>
<description>Enable Interrupt Line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GFC</name>
<description>Global Filter Configuration Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<fields>
<field>
<name>RRFE</name>
<description>Reject Remote Frames Extended</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RRFESelect</name>
<enumeratedValue>
<name>FILTER</name>
<description>Filter remote frames with 29-bit extended IDs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REJECT</name>
<description>Reject all remote frames with 29-bit extended IDs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RRFS</name>
<description>Reject Remote Frames Standard</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RRFSSelect</name>
<enumeratedValue>
<name>FILTER</name>
<description>Filter remote frames with 11-bit standard IDs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REJECT</name>
<description>Reject all remote frames with 11-bit standard IDs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ANFE</name>
<description>Accept Non-matching Frames Extended</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ANFESelect</name>
<enumeratedValue>
<name>RX_FIFO_0</name>
<description>Accept in Rx FIFO 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_FIFO_1</name>
<description>Accept in Rx FIFO 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ANFS</name>
<description>Accept Non-matching Frames Standard</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ANFSSelect</name>
<enumeratedValue>
<name>RX_FIFO_0</name>
<description>Accept in Rx FIFO 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_FIFO_1</name>
<description>Accept in Rx FIFO 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SIDFC</name>
<description>Standard ID Filter Configuration Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<fields>
<field>
<name>FLSSA</name>
<description>Filter List Standard Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSS</name>
<description>List Size Standard</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>XIDFC</name>
<description>Extended ID Filter Configuration Register</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<fields>
<field>
<name>FLESA</name>
<description>Filter List Extended Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSE</name>
<description>List Size Extended</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>XIDAM</name>
<description>Extended ID AND Mask Register</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<fields>
<field>
<name>EIDM</name>
<description>Extended ID Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPMS</name>
<description>High Priority Message Status Register</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>BIDX</name>
<description>Buffer Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MSI</name>
<description>Message Storage Indicator</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>MSISelect</name>
<enumeratedValue>
<name>NO_FIFO_SEL</name>
<description>No FIFO selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOST</name>
<description>FIFO message lost.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FIFO_0</name>
<description>Message stored in FIFO 0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FIFO_1</name>
<description>Message stored in FIFO 1.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIDX</name>
<description>Filter Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FLST</name>
<description>Filter List</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NDAT1</name>
<description>New Data 1 Register</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<fields>
<field>
<name>ND0</name>
<description>New Data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND1</name>
<description>New Data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND2</name>
<description>New Data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND3</name>
<description>New Data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND4</name>
<description>New Data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND5</name>
<description>New Data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND6</name>
<description>New Data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND7</name>
<description>New Data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND8</name>
<description>New Data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND9</name>
<description>New Data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND10</name>
<description>New Data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND11</name>
<description>New Data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND12</name>
<description>New Data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND13</name>
<description>New Data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND14</name>
<description>New Data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND15</name>
<description>New Data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND16</name>
<description>New Data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND17</name>
<description>New Data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND18</name>
<description>New Data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND19</name>
<description>New Data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND20</name>
<description>New Data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND21</name>
<description>New Data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND22</name>
<description>New Data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND23</name>
<description>New Data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND24</name>
<description>New Data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND25</name>
<description>New Data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND26</name>
<description>New Data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND27</name>
<description>New Data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND28</name>
<description>New Data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND29</name>
<description>New Data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND30</name>
<description>New Data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND31</name>
<description>New Data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NDAT2</name>
<description>New Data 2 Register</description>
<addressOffset>0x9C</addressOffset>
<size>32</size>
<fields>
<field>
<name>ND32</name>
<description>New Data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND33</name>
<description>New Data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND34</name>
<description>New Data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND35</name>
<description>New Data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND36</name>
<description>New Data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND37</name>
<description>New Data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND38</name>
<description>New Data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND39</name>
<description>New Data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND40</name>
<description>New Data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND41</name>
<description>New Data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND42</name>
<description>New Data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND43</name>
<description>New Data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND44</name>
<description>New Data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND45</name>
<description>New Data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND46</name>
<description>New Data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND47</name>
<description>New Data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND48</name>
<description>New Data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND49</name>
<description>New Data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND50</name>
<description>New Data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND51</name>
<description>New Data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND52</name>
<description>New Data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND53</name>
<description>New Data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND54</name>
<description>New Data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND55</name>
<description>New Data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND56</name>
<description>New Data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND57</name>
<description>New Data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND58</name>
<description>New Data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND59</name>
<description>New Data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND60</name>
<description>New Data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND61</name>
<description>New Data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND62</name>
<description>New Data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND63</name>
<description>New Data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF0C</name>
<description>Receive FIFO 0 Configuration Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<fields>
<field>
<name>F0SA</name>
<description>Receive FIFO 0 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F0S</name>
<description>Receive FIFO 0 Start Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0WM</name>
<description>Receive FIFO 0 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0OM</name>
<description>FIFO 0 Operation Mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF0S</name>
<description>Receive FIFO 0 Status Register</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>F0FL</name>
<description>Receive FIFO 0 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0GI</name>
<description>Receive FIFO 0 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0PI</name>
<description>Receive FIFO 0 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0F</name>
<description>Receive FIFO 0 Fill Level</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Receive FIFO 0 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF0A</name>
<description>Receive FIFO 0 Acknowledge Register</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<fields>
<field>
<name>F0AI</name>
<description>Receive FIFO 0 Acknowledge Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXBC</name>
<description>Receive Rx Buffer Configuration Register</description>
<addressOffset>0xAC</addressOffset>
<size>32</size>
<fields>
<field>
<name>RBSA</name>
<description>Receive Buffer Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF1C</name>
<description>Receive FIFO 1 Configuration Register</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<fields>
<field>
<name>F1SA</name>
<description>Receive FIFO 1 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F1S</name>
<description>Receive FIFO 1 Start Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1WM</name>
<description>Receive FIFO 1 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1OM</name>
<description>FIFO 1 Operation Mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF1S</name>
<description>Receive FIFO 1 Status Register</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>F1FL</name>
<description>Receive FIFO 1 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1GI</name>
<description>Receive FIFO 1 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F1PI</name>
<description>Receive FIFO 1 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F1F</name>
<description>Receive FIFO 1 Fill Level</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Receive FIFO 1 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMS</name>
<description>Debug Message Status</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DMSSelect</name>
<enumeratedValue>
<name>IDLE</name>
<description>Idle state, wait for reception of debug messages, DMA request is cleared.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MSG_A</name>
<description>Debug message A received.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MSG_AB</name>
<description>Debug messages A, B received.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MSG_ABC</name>
<description>Debug messages A, B, C received, DMA request is set.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RXF1A</name>
<description>Receive FIFO 1 Acknowledge Register</description>
<addressOffset>0xB8</addressOffset>
<size>32</size>
<fields>
<field>
<name>F1AI</name>
<description>Receive FIFO 1 Acknowledge Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXESC</name>
<description>Receive Buffer / FIFO Element Size Configuration Register</description>
<addressOffset>0xBC</addressOffset>
<size>32</size>
<fields>
<field>
<name>F0DS</name>
<description>Receive FIFO 0 Data Field Size</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>F0DSSelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8-byte data field</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_BYTE</name>
<description>12-byte data field</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16-byte data field</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_20_BYTE</name>
<description>20-byte data field</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_24_BYTE</name>
<description>24-byte data field</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32-byte data field</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_48_BYTE</name>
<description>48-byte data field</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64-byte data field</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>F1DS</name>
<description>Receive FIFO 1 Data Field Size</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>F1DSSelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8-byte data field</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_BYTE</name>
<description>12-byte data field</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16-byte data field</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_20_BYTE</name>
<description>20-byte data field</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_24_BYTE</name>
<description>24-byte data field</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32-byte data field</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_48_BYTE</name>
<description>48-byte data field</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64-byte data field</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RBDS</name>
<description>Receive Buffer Data Field Size</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>RBDSSelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8-byte data field</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_BYTE</name>
<description>12-byte data field</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16-byte data field</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_20_BYTE</name>
<description>20-byte data field</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_24_BYTE</name>
<description>24-byte data field</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32-byte data field</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_48_BYTE</name>
<description>48-byte data field</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64-byte data field</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TXBC</name>
<description>Transmit Buffer Configuration Register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<fields>
<field>
<name>TBSA</name>
<description>Tx Buffers Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>NDTB</name>
<description>Number of Dedicated Transmit Buffers</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQS</name>
<description>Transmit FIFO/Queue Size</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQM</name>
<description>Tx FIFO/Queue Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXFQS</name>
<description>Transmit FIFO/Queue Status Register</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TFFL</name>
<description>Tx FIFO Free Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFGI</name>
<description>Tx FIFO Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQPI</name>
<description>Tx FIFO/Queue Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQF</name>
<description>Tx FIFO/Queue Full</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXESC</name>
<description>Transmit Buffer Element Size Configuration Register</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<fields>
<field>
<name>TBDS</name>
<description>Tx Buffer Data Field Size</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TBDSSelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8-byte data field</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_BYTE</name>
<description>12-byte data field</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16-byte data field</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_20_BYTE</name>
<description>20-byte data field</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_24_BYTE</name>
<description>24-byte data field</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32-byte data field</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_48_BYTE</name>
<description>48-byte data field</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64-byte data field</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TXBRP</name>
<description>Transmit Buffer Request Pending Register</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TRP0</name>
<description>Transmission Request Pending for Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP1</name>
<description>Transmission Request Pending for Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP2</name>
<description>Transmission Request Pending for Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP3</name>
<description>Transmission Request Pending for Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP4</name>
<description>Transmission Request Pending for Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP5</name>
<description>Transmission Request Pending for Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP6</name>
<description>Transmission Request Pending for Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP7</name>
<description>Transmission Request Pending for Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP8</name>
<description>Transmission Request Pending for Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP9</name>
<description>Transmission Request Pending for Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP10</name>
<description>Transmission Request Pending for Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP11</name>
<description>Transmission Request Pending for Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP12</name>
<description>Transmission Request Pending for Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP13</name>
<description>Transmission Request Pending for Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP14</name>
<description>Transmission Request Pending for Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP15</name>
<description>Transmission Request Pending for Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP16</name>
<description>Transmission Request Pending for Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP17</name>
<description>Transmission Request Pending for Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP18</name>
<description>Transmission Request Pending for Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP19</name>
<description>Transmission Request Pending for Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP20</name>
<description>Transmission Request Pending for Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP21</name>
<description>Transmission Request Pending for Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP22</name>
<description>Transmission Request Pending for Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP23</name>
<description>Transmission Request Pending for Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP24</name>
<description>Transmission Request Pending for Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP25</name>
<description>Transmission Request Pending for Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP26</name>
<description>Transmission Request Pending for Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP27</name>
<description>Transmission Request Pending for Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP28</name>
<description>Transmission Request Pending for Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP29</name>
<description>Transmission Request Pending for Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP30</name>
<description>Transmission Request Pending for Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRP31</name>
<description>Transmission Request Pending for Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBAR</name>
<description>Transmit Buffer Add Request Register</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<fields>
<field>
<name>AR0</name>
<description>Add Request for Transmit Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR1</name>
<description>Add Request for Transmit Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR2</name>
<description>Add Request for Transmit Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR3</name>
<description>Add Request for Transmit Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR4</name>
<description>Add Request for Transmit Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR5</name>
<description>Add Request for Transmit Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR6</name>
<description>Add Request for Transmit Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR7</name>
<description>Add Request for Transmit Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR8</name>
<description>Add Request for Transmit Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR9</name>
<description>Add Request for Transmit Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR10</name>
<description>Add Request for Transmit Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR11</name>
<description>Add Request for Transmit Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR12</name>
<description>Add Request for Transmit Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR13</name>
<description>Add Request for Transmit Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR14</name>
<description>Add Request for Transmit Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR15</name>
<description>Add Request for Transmit Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR16</name>
<description>Add Request for Transmit Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR17</name>
<description>Add Request for Transmit Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR18</name>
<description>Add Request for Transmit Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR19</name>
<description>Add Request for Transmit Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR20</name>
<description>Add Request for Transmit Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR21</name>
<description>Add Request for Transmit Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR22</name>
<description>Add Request for Transmit Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR23</name>
<description>Add Request for Transmit Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR24</name>
<description>Add Request for Transmit Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR25</name>
<description>Add Request for Transmit Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR26</name>
<description>Add Request for Transmit Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR27</name>
<description>Add Request for Transmit Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR28</name>
<description>Add Request for Transmit Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR29</name>
<description>Add Request for Transmit Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR30</name>
<description>Add Request for Transmit Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AR31</name>
<description>Add Request for Transmit Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCR</name>
<description>Transmit Buffer Cancellation Request Register</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<fields>
<field>
<name>CR0</name>
<description>Cancellation Request for Transmit Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR1</name>
<description>Cancellation Request for Transmit Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR2</name>
<description>Cancellation Request for Transmit Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR3</name>
<description>Cancellation Request for Transmit Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR4</name>
<description>Cancellation Request for Transmit Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR5</name>
<description>Cancellation Request for Transmit Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR6</name>
<description>Cancellation Request for Transmit Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR7</name>
<description>Cancellation Request for Transmit Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR8</name>
<description>Cancellation Request for Transmit Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR9</name>
<description>Cancellation Request for Transmit Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR10</name>
<description>Cancellation Request for Transmit Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR11</name>
<description>Cancellation Request for Transmit Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR12</name>
<description>Cancellation Request for Transmit Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR13</name>
<description>Cancellation Request for Transmit Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR14</name>
<description>Cancellation Request for Transmit Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR15</name>
<description>Cancellation Request for Transmit Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR16</name>
<description>Cancellation Request for Transmit Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR17</name>
<description>Cancellation Request for Transmit Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR18</name>
<description>Cancellation Request for Transmit Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR19</name>
<description>Cancellation Request for Transmit Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR20</name>
<description>Cancellation Request for Transmit Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR21</name>
<description>Cancellation Request for Transmit Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR22</name>
<description>Cancellation Request for Transmit Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR23</name>
<description>Cancellation Request for Transmit Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR24</name>
<description>Cancellation Request for Transmit Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR25</name>
<description>Cancellation Request for Transmit Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR26</name>
<description>Cancellation Request for Transmit Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR27</name>
<description>Cancellation Request for Transmit Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR28</name>
<description>Cancellation Request for Transmit Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR29</name>
<description>Cancellation Request for Transmit Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR30</name>
<description>Cancellation Request for Transmit Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CR31</name>
<description>Cancellation Request for Transmit Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBTO</name>
<description>Transmit Buffer Transmission Occurred Register</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TO0</name>
<description>Transmission Occurred for Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO1</name>
<description>Transmission Occurred for Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO2</name>
<description>Transmission Occurred for Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO3</name>
<description>Transmission Occurred for Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO4</name>
<description>Transmission Occurred for Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO5</name>
<description>Transmission Occurred for Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO6</name>
<description>Transmission Occurred for Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO7</name>
<description>Transmission Occurred for Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO8</name>
<description>Transmission Occurred for Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO9</name>
<description>Transmission Occurred for Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO10</name>
<description>Transmission Occurred for Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO11</name>
<description>Transmission Occurred for Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO12</name>
<description>Transmission Occurred for Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO13</name>
<description>Transmission Occurred for Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO14</name>
<description>Transmission Occurred for Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO15</name>
<description>Transmission Occurred for Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO16</name>
<description>Transmission Occurred for Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO17</name>
<description>Transmission Occurred for Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO18</name>
<description>Transmission Occurred for Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO19</name>
<description>Transmission Occurred for Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO20</name>
<description>Transmission Occurred for Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO21</name>
<description>Transmission Occurred for Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO22</name>
<description>Transmission Occurred for Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO23</name>
<description>Transmission Occurred for Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO24</name>
<description>Transmission Occurred for Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO25</name>
<description>Transmission Occurred for Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO26</name>
<description>Transmission Occurred for Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO27</name>
<description>Transmission Occurred for Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO28</name>
<description>Transmission Occurred for Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO29</name>
<description>Transmission Occurred for Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO30</name>
<description>Transmission Occurred for Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO31</name>
<description>Transmission Occurred for Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCF</name>
<description>Transmit Buffer Cancellation Finished Register</description>
<addressOffset>0xDC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CF0</name>
<description>Cancellation Finished for Transmit Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF1</name>
<description>Cancellation Finished for Transmit Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF2</name>
<description>Cancellation Finished for Transmit Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF3</name>
<description>Cancellation Finished for Transmit Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF4</name>
<description>Cancellation Finished for Transmit Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF5</name>
<description>Cancellation Finished for Transmit Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF6</name>
<description>Cancellation Finished for Transmit Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF7</name>
<description>Cancellation Finished for Transmit Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF8</name>
<description>Cancellation Finished for Transmit Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF9</name>
<description>Cancellation Finished for Transmit Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF10</name>
<description>Cancellation Finished for Transmit Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF11</name>
<description>Cancellation Finished for Transmit Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF12</name>
<description>Cancellation Finished for Transmit Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF13</name>
<description>Cancellation Finished for Transmit Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF14</name>
<description>Cancellation Finished for Transmit Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF15</name>
<description>Cancellation Finished for Transmit Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF16</name>
<description>Cancellation Finished for Transmit Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF17</name>
<description>Cancellation Finished for Transmit Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF18</name>
<description>Cancellation Finished for Transmit Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF19</name>
<description>Cancellation Finished for Transmit Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF20</name>
<description>Cancellation Finished for Transmit Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF21</name>
<description>Cancellation Finished for Transmit Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF22</name>
<description>Cancellation Finished for Transmit Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF23</name>
<description>Cancellation Finished for Transmit Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF24</name>
<description>Cancellation Finished for Transmit Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF25</name>
<description>Cancellation Finished for Transmit Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF26</name>
<description>Cancellation Finished for Transmit Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF27</name>
<description>Cancellation Finished for Transmit Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF28</name>
<description>Cancellation Finished for Transmit Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF29</name>
<description>Cancellation Finished for Transmit Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF30</name>
<description>Cancellation Finished for Transmit Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CF31</name>
<description>Cancellation Finished for Transmit Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBTIE</name>
<description>Transmit Buffer Transmission Interrupt Enable Register</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<fields>
<field>
<name>TIE0</name>
<description>Transmission Interrupt Enable for Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE1</name>
<description>Transmission Interrupt Enable for Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE2</name>
<description>Transmission Interrupt Enable for Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE3</name>
<description>Transmission Interrupt Enable for Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE4</name>
<description>Transmission Interrupt Enable for Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE5</name>
<description>Transmission Interrupt Enable for Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE6</name>
<description>Transmission Interrupt Enable for Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE7</name>
<description>Transmission Interrupt Enable for Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE8</name>
<description>Transmission Interrupt Enable for Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE9</name>
<description>Transmission Interrupt Enable for Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE10</name>
<description>Transmission Interrupt Enable for Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE11</name>
<description>Transmission Interrupt Enable for Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE12</name>
<description>Transmission Interrupt Enable for Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE13</name>
<description>Transmission Interrupt Enable for Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE14</name>
<description>Transmission Interrupt Enable for Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE15</name>
<description>Transmission Interrupt Enable for Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE16</name>
<description>Transmission Interrupt Enable for Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE17</name>
<description>Transmission Interrupt Enable for Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE18</name>
<description>Transmission Interrupt Enable for Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE19</name>
<description>Transmission Interrupt Enable for Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE20</name>
<description>Transmission Interrupt Enable for Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE21</name>
<description>Transmission Interrupt Enable for Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE22</name>
<description>Transmission Interrupt Enable for Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE23</name>
<description>Transmission Interrupt Enable for Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE24</name>
<description>Transmission Interrupt Enable for Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE25</name>
<description>Transmission Interrupt Enable for Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE26</name>
<description>Transmission Interrupt Enable for Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE27</name>
<description>Transmission Interrupt Enable for Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE28</name>
<description>Transmission Interrupt Enable for Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE29</name>
<description>Transmission Interrupt Enable for Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE30</name>
<description>Transmission Interrupt Enable for Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE31</name>
<description>Transmission Interrupt Enable for Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCIE</name>
<description>Transmit Buffer Cancellation Finished Interrupt Enable Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>CFIE0</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE1</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE2</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE3</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE4</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE5</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE6</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE7</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE8</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE9</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE10</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE11</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE12</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE13</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE14</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE15</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE16</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE17</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE18</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE19</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE20</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE21</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE22</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE23</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE24</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE25</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE26</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE27</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE28</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE29</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE30</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFIE31</name>
<description>Cancellation Finished Interrupt Enable for Transmit Buffer 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXEFC</name>
<description>Transmit Event FIFO Configuration Register</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<fields>
<field>
<name>EFSA</name>
<description>Event FIFO Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>EFS</name>
<description>Event FIFO Size</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFWM</name>
<description>Event FIFO Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXEFS</name>
<description>Transmit Event FIFO Status Register</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>EFFL</name>
<description>Event FIFO Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFGI</name>
<description>Event FIFO Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EFPI</name>
<description>Event FIFO Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EFF</name>
<description>Event FIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXEFA</name>
<description>Transmit Event FIFO Acknowledge Register</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<fields>
<field>
<name>EFAI</name>
<description>Event FIFO Acknowledge Index</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="MCAN0">
<name>MCAN1</name>
<baseAddress>0x40034000</baseAddress>
<interrupt>
<name>MCAN1_INT0</name>
<value>37</value>
</interrupt>
<interrupt>
<name>MCAN1_INT1</name>
<value>38</value>
</interrupt>
</peripheral>
<peripheral>
<name>MLB</name>
<version>11287E</version>
<description>MediaLB</description>
<groupName>MLB</groupName>
<prependToName>MLB_</prependToName>
<baseAddress>0x40068000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3E0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MLB</name>
<value>53</value>
</interrupt>
<registers>
<register>
<name>MLBC0</name>
<description>MediaLB Control 0 Register</description>
<addressOffset>0x000</addressOffset>
<size>32</size>
<fields>
<field>
<name>MLBEN</name>
<description>MediaLB Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLBCLK</name>
<description>MLBCLK (MediaLB clock) Speed Select</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>MLBCLKSelect</name>
<enumeratedValue>
<name>_256_FS</name>
<description>256xFs (for MLBPEN = 0)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_512_FS</name>
<description>512xFs (for MLBPEN = 0)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024_FS</name>
<description>1024xFs (for MLBPEN = 0)</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ZERO</name>
<description>Must be Written to 0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLBLK</name>
<description>MediaLB Lock Status (read-only)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYRETRY</name>
<description>Asynchronous Tx Packet Retry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTLRETRY</name>
<description>Control Tx Packet Retry</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCNT</name>
<description>The number of frames per sub-buffer for synchronous channels</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>FCNTSelect</name>
<enumeratedValue>
<name>_1_FRAME</name>
<description>1 frame per sub-buffer (Operation is the same as Standard mode.)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_FRAMES</name>
<description>2 frames per sub-buffer</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_4_FRAMES</name>
<description>4 frames per sub-buffer</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_FRAMES</name>
<description>8 frames per sub-buffer</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_FRAMES</name>
<description>16 frames per sub-buffer</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_FRAMES</name>
<description>32 frames per sub-buffer</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_FRAMES</name>
<description>64 frames per sub-buffer</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MS0</name>
<description>MediaLB Channel Status 0 Register</description>
<addressOffset>0x00C</addressOffset>
<size>32</size>
<fields>
<field>
<name>MCS</name>
<description>MediaLB Channel Status [31:0] (cleared by writing a 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MS1</name>
<description>MediaLB Channel Status1 Register</description>
<addressOffset>0x014</addressOffset>
<size>32</size>
<fields>
<field>
<name>MCS</name>
<description>MediaLB Channel Status [63:32] (cleared by writing a 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSS</name>
<description>MediaLB System Status Register</description>
<addressOffset>0x020</addressOffset>
<size>32</size>
<fields>
<field>
<name>RSTSYSCMD</name>
<description>Reset System Command Detected in the System Quadlet (cleared by writing a 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LKSYSCMD</name>
<description>Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULKSYSCMD</name>
<description>Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSSYSCMD</name>
<description>Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWSYSCMD</name>
<description>Software System Command Detected in the System Quadlet (cleared by writing a 0)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SERVREQ</name>
<description>Service Request Enabled</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSD</name>
<description>MediaLB System Data Register</description>
<addressOffset>0x024</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>SD0</name>
<description>System Data (Byte 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD1</name>
<description>System Data (Byte 1)</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD2</name>
<description>System Data (Byte 2)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD3</name>
<description>System Data (Byte 3)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MIEN</name>
<description>MediaLB Interrupt Enable Register</description>
<addressOffset>0x02C</addressOffset>
<size>32</size>
<fields>
<field>
<name>ISOC_PE</name>
<description>Isochronous Rx Protocol Error Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISOC_BUFO</name>
<description>Isochronous Rx Buffer Overflow Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC_PE</name>
<description>Synchronous Protocol Error Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARX_DONE</name>
<description>Asynchronous Rx Done Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARX_PE</name>
<description>Asynchronous Rx Protocol Error Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARX_BREAK</name>
<description>Asynchronous Rx Break Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ATX_DONE</name>
<description>Asynchronous Tx Packet Done Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ATX_PE</name>
<description>Asynchronous Tx Protocol Error Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ATX_BREAK</name>
<description>Asynchronous Tx Break Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRX_DONE</name>
<description>Control Rx Packet Done Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRX_PE</name>
<description>Control Rx Protocol Error Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRX_BREAK</name>
<description>Control Rx Break Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTX_DONE</name>
<description>Control Tx Packet Done Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTX_PE</name>
<description>Control Tx Protocol Error Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTX_BREAK</name>
<description>Control Tx Break Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MLBC1</name>
<description>MediaLB Control 1 Register</description>
<addressOffset>0x03C</addressOffset>
<size>32</size>
<fields>
<field>
<name>LOCK</name>
<description>MediaLB Lock Error Status (cleared by writing a 0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKM</name>
<description>MediaLB Clock Missing Status (cleared by writing a 0)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NDA</name>
<description>Node Device Address</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTL</name>
<description>HBI Control Register</description>
<addressOffset>0x080</addressOffset>
<size>32</size>
<fields>
<field>
<name>RST0</name>
<description>Address Generation Unit 0 Software Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST1</name>
<description>Address Generation Unit 1 Software Reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>HBI Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>HCMR[%s]</name>
<description>HBI Channel Mask 0 Register 0</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHM</name>
<description>Bitwise Channel Mask Bit [31:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>HCER[%s]</name>
<description>HBI Channel Error 0 Register 0</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CERR</name>
<description>Bitwise Channel Error Bit [31:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>HCBR[%s]</name>
<description>HBI Channel Busy 0 Register 0</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CHB</name>
<description>Bitwise Channel Busy Bit [31:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>MDAT[%s]</name>
<description>MIF Data 0 Register 0</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATA</name>
<description>CRT or DBR Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>MDWE[%s]</name>
<description>MIF Data Write Enable 0 Register 0</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<fields>
<field>
<name>MASK</name>
<description>Bitwise Write Enable for CTR Data - bits[31:0]</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCTL</name>
<description>MIF Control Register</description>
<addressOffset>0x0E0</addressOffset>
<size>32</size>
<fields>
<field>
<name>XCMP</name>
<description>Transfer Complete (Write 0 to Clear)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MADR</name>
<description>MIF Address Register</description>
<addressOffset>0x0E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>CTR or DBR Address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>TB</name>
<description>Target Location Bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TBSelect</name>
<enumeratedValue>
<name>CTR</name>
<description>Selects CTR</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DBR</name>
<description>Selects DBR</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WNR</name>
<description>Write-Not-Read Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACTL</name>
<description>AHB Control Register</description>
<addressOffset>0x3C0</addressOffset>
<size>32</size>
<fields>
<field>
<name>SCE</name>
<description>Software Clear Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMX</name>
<description>AHB Interrupt Mux Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_MODE</name>
<description>DMA Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPB</name>
<description>DMA Packet Buffering Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MPBSelect</name>
<enumeratedValue>
<name>SINGLE_PACKET</name>
<description>Single-packet mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MULTIPLE_PACKET</name>
<description>Multiple-packet mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>ACSR[%s]</name>
<description>AHB Channel Status 0 Register 0</description>
<addressOffset>0x3D0</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHS</name>
<description>Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>ACMR[%s]</name>
<description>AHB Channel Mask 0 Register 0</description>
<addressOffset>0x3D8</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHM</name>
<description>Bitwise Channel Mask Bits 31 to 0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PIOA</name>
<version>11004V</version>
<description>Parallel Input/Output Controller</description>
<groupName>PIO</groupName>
<prependToName>PIO_</prependToName>
<baseAddress>0x400E0E00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x168</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIOA</name>
<value>10</value>
</interrupt>
<registers>
<register>
<name>PER</name>
<description>PIO Enable Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>PIO Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>PIO Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>PIO Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>PIO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>PIO Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>PIO Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>PIO Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>PIO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>PIO Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>PIO Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>PIO Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>PIO Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>PIO Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>PIO Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>PIO Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>PIO Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>PIO Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>PIO Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>PIO Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>PIO Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>PIO Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>PIO Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>PIO Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>PIO Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>PIO Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>PIO Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>PIO Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>PIO Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>PIO Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>PIO Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>PIO Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>PIO Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDR</name>
<description>PIO Disable Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>PIO Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>PIO Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>PIO Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>PIO Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>PIO Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>PIO Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>PIO Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>PIO Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>PIO Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>PIO Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>PIO Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>PIO Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>PIO Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>PIO Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>PIO Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>PIO Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>PIO Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>PIO Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>PIO Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>PIO Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>PIO Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>PIO Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>PIO Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>PIO Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>PIO Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>PIO Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>PIO Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>PIO Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>PIO Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>PIO Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>PIO Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>PIO Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<description>PIO Status Register</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>PIO Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>PIO Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>PIO Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>PIO Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>PIO Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>PIO Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>PIO Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>PIO Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>PIO Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>PIO Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>PIO Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>PIO Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>PIO Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>PIO Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>PIO Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>PIO Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>PIO Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>PIO Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>PIO Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>PIO Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>PIO Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>PIO Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>PIO Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>PIO Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>PIO Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>PIO Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>PIO Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>PIO Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>PIO Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>PIO Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>PIO Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>PIO Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OER</name>
<description>Output Enable Register</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<description>Output Disable Register</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Output Status Register</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFER</name>
<description>Glitch Input Filter Enable Register</description>
<addressOffset>0x0020</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Filter Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Filter Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Filter Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Filter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Filter Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Filter Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Filter Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Filter Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Filter Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Filter Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Filter Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Filter Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Filter Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Filter Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Filter Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Filter Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Filter Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Filter Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Filter Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Filter Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Filter Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Filter Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Filter Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Filter Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Filter Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Filter Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Filter Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Filter Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Filter Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFDR</name>
<description>Glitch Input Filter Disable Register</description>
<addressOffset>0x0024</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Filter Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Filter Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Filter Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Filter Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Filter Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Filter Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Filter Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Filter Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Filter Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Filter Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Filter Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Filter Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Filter Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Filter Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Filter Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Filter Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Filter Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Filter Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Filter Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Filter Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Filter Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Filter Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Filter Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Filter Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Filter Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Filter Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Filter Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Filter Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Filter Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Filter Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Filter Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Filter Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFSR</name>
<description>Glitch Input Filter Status Register</description>
<addressOffset>0x0028</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Filter Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Filter Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Filter Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Filter Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Filter Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Filter Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Filter Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Filter Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Filter Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Filter Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Filter Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Filter Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Filter Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Filter Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Filter Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Filter Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Filter Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Filter Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Filter Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Filter Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Filter Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Filter Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Filter Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Filter Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Filter Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Filter Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Filter Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Filter Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Filter Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Filter Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Filter Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Filter Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SODR</name>
<description>Set Output Data Register</description>
<addressOffset>0x0030</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Set Output Data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Set Output Data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Set Output Data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Set Output Data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Set Output Data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Set Output Data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Set Output Data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Set Output Data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Set Output Data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Set Output Data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Set Output Data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Set Output Data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Set Output Data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Set Output Data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Set Output Data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Set Output Data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Set Output Data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Set Output Data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Set Output Data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Set Output Data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Set Output Data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Set Output Data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Set Output Data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Set Output Data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Set Output Data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Set Output Data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Set Output Data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Set Output Data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Set Output Data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Set Output Data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Set Output Data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Set Output Data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CODR</name>
<description>Clear Output Data Register</description>
<addressOffset>0x0034</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Clear Output Data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Clear Output Data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Clear Output Data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Clear Output Data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Clear Output Data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Clear Output Data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Clear Output Data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Clear Output Data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Clear Output Data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Clear Output Data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Clear Output Data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Clear Output Data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Clear Output Data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Clear Output Data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Clear Output Data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Clear Output Data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Clear Output Data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Clear Output Data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Clear Output Data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Clear Output Data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Clear Output Data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Clear Output Data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Clear Output Data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Clear Output Data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Clear Output Data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Clear Output Data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Clear Output Data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Clear Output Data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Clear Output Data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Clear Output Data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Clear Output Data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Clear Output Data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODSR</name>
<description>Output Data Status Register</description>
<addressOffset>0x0038</addressOffset>
<size>32</size>
<fields>
<field>
<name>P0</name>
<description>Output Data Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Data Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Data Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Data Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Data Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Data Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Data Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Data Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Data Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Data Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Data Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Data Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Data Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Data Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Data Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Data Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Data Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Data Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Data Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Data Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Data Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Data Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Data Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Data Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Data Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Data Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Data Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Data Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Data Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Data Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Data Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Data Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDSR</name>
<description>Pin Data Status Register</description>
<addressOffset>0x003C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Data Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Data Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Data Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Data Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Data Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Data Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Data Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Data Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Data Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Data Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Data Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Data Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Data Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Data Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Data Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Data Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Data Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Data Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Data Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Data Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Data Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Data Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Data Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Data Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Data Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Data Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Data Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Data Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Data Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Data Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Data Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Data Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x0040</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Change Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x0044</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Change Interrupt Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x0048</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Change Interrupt Mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x004C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Input Change Interrupt Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Input Change Interrupt Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Input Change Interrupt Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Input Change Interrupt Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Input Change Interrupt Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Input Change Interrupt Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Input Change Interrupt Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Input Change Interrupt Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Input Change Interrupt Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Input Change Interrupt Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Input Change Interrupt Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Input Change Interrupt Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Input Change Interrupt Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Input Change Interrupt Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Input Change Interrupt Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Input Change Interrupt Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Input Change Interrupt Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Input Change Interrupt Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Input Change Interrupt Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Input Change Interrupt Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Input Change Interrupt Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Input Change Interrupt Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Input Change Interrupt Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Input Change Interrupt Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Input Change Interrupt Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Input Change Interrupt Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Input Change Interrupt Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Input Change Interrupt Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Input Change Interrupt Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Input Change Interrupt Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Input Change Interrupt Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Input Change Interrupt Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDER</name>
<description>Multi-driver Enable Register</description>
<addressOffset>0x0050</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Multi-drive Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Multi-drive Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Multi-drive Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Multi-drive Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Multi-drive Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Multi-drive Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Multi-drive Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Multi-drive Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Multi-drive Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Multi-drive Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Multi-drive Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Multi-drive Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Multi-drive Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Multi-drive Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Multi-drive Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Multi-drive Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Multi-drive Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Multi-drive Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Multi-drive Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Multi-drive Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Multi-drive Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Multi-drive Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Multi-drive Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Multi-drive Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Multi-drive Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Multi-drive Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Multi-drive Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Multi-drive Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Multi-drive Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Multi-drive Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Multi-drive Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Multi-drive Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDDR</name>
<description>Multi-driver Disable Register</description>
<addressOffset>0x0054</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Multi-drive Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Multi-drive Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Multi-drive Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Multi-drive Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Multi-drive Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Multi-drive Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Multi-drive Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Multi-drive Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Multi-drive Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Multi-drive Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Multi-drive Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Multi-drive Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Multi-drive Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Multi-drive Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Multi-drive Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Multi-drive Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Multi-drive Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Multi-drive Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Multi-drive Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Multi-drive Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Multi-drive Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Multi-drive Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Multi-drive Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Multi-drive Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Multi-drive Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Multi-drive Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Multi-drive Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Multi-drive Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Multi-drive Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Multi-drive Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Multi-drive Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Multi-drive Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDSR</name>
<description>Multi-driver Status Register</description>
<addressOffset>0x0058</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Multi-drive Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Multi-drive Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Multi-drive Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Multi-drive Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Multi-drive Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Multi-drive Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Multi-drive Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Multi-drive Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Multi-drive Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Multi-drive Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Multi-drive Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Multi-drive Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Multi-drive Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Multi-drive Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Multi-drive Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Multi-drive Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Multi-drive Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Multi-drive Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Multi-drive Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Multi-drive Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Multi-drive Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Multi-drive Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Multi-drive Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Multi-drive Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Multi-drive Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Multi-drive Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Multi-drive Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Multi-drive Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Multi-drive Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Multi-drive Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Multi-drive Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Multi-drive Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUDR</name>
<description>Pull-up Disable Register</description>
<addressOffset>0x0060</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Up Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Up Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Up Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Up Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Up Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Up Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Up Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Up Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Up Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Up Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Up Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Up Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Up Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Up Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Up Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Up Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Up Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Up Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Up Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Up Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Up Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Up Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Up Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Up Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Up Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Up Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Up Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Up Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Up Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Up Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Up Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Up Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUER</name>
<description>Pull-up Enable Register</description>
<addressOffset>0x0064</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Up Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Up Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Up Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Up Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Up Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Up Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Up Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Up Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Up Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Up Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Up Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Up Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Up Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Up Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Up Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Up Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Up Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Up Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Up Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Up Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Up Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Up Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Up Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Up Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Up Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Up Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Up Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Up Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Up Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Up Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Up Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Up Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUSR</name>
<description>Pad Pull-up Status Register</description>
<addressOffset>0x0068</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Up Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Up Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Up Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Up Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Up Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Up Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Up Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Up Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Up Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Up Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Up Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Up Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Up Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Up Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Up Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Up Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Up Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Up Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Up Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Up Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Up Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Up Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Up Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Up Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Up Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Up Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Up Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Up Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Up Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Up Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Up Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Up Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>ABCDSR[%s]</name>
<description>Peripheral ABCD Select Register 0</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<fields>
<field>
<name>P0</name>
<description>Peripheral Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Peripheral Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Peripheral Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Peripheral Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Peripheral Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Peripheral Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Peripheral Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Peripheral Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Peripheral Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Peripheral Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Peripheral Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Peripheral Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Peripheral Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Peripheral Select</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Peripheral Select</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Peripheral Select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Peripheral Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Peripheral Select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Peripheral Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Peripheral Select</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Peripheral Select</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Peripheral Select</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Peripheral Select</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Peripheral Select</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Peripheral Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Peripheral Select</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Peripheral Select</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Peripheral Select</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Peripheral Select</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Peripheral Select</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Peripheral Select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Peripheral Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFSCDR</name>
<description>Input Filter Slow Clock Disable Register</description>
<addressOffset>0x0080</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Peripheral Clock Glitch Filtering Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFSCER</name>
<description>Input Filter Slow Clock Enable Register</description>
<addressOffset>0x0084</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Slow Clock Debouncing Filtering Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFSCSR</name>
<description>Input Filter Slow Clock Status Register</description>
<addressOffset>0x0088</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Glitch or Debouncing Filter Selection Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCDR</name>
<description>Slow Clock Divider Debouncing Register</description>
<addressOffset>0x008C</addressOffset>
<size>32</size>
<fields>
<field>
<name>DIV</name>
<description>Slow Clock Divider Selection for Debouncing</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>PPDDR</name>
<description>Pad Pull-down Disable Register</description>
<addressOffset>0x0090</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Down Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Down Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Down Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Down Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Down Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Down Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Down Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Down Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Down Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Down Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Down Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Down Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Down Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Down Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Down Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Down Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Down Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Down Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Down Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Down Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Down Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Down Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Down Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Down Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Down Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Down Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Down Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Down Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Down Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Down Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Down Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Down Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PPDER</name>
<description>Pad Pull-down Enable Register</description>
<addressOffset>0x0094</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Down Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Down Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Down Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Down Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Down Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Down Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Down Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Down Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Down Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Down Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Down Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Down Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Down Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Down Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Down Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Down Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Down Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Down Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Down Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Down Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Down Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Down Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Down Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Down Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Down Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Down Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Down Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Down Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Down Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Down Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Down Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Down Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PPDSR</name>
<description>Pad Pull-down Status Register</description>
<addressOffset>0x0098</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Pull-Down Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Pull-Down Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Pull-Down Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Pull-Down Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Pull-Down Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Pull-Down Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Pull-Down Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Pull-Down Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Pull-Down Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Pull-Down Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Pull-Down Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Pull-Down Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Pull-Down Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Pull-Down Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Pull-Down Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Pull-Down Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Pull-Down Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Pull-Down Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Pull-Down Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Pull-Down Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Pull-Down Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Pull-Down Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Pull-Down Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Pull-Down Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Pull-Down Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Pull-Down Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Pull-Down Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Pull-Down Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Pull-Down Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Pull-Down Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Pull-Down Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Pull-Down Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OWER</name>
<description>Output Write Enable</description>
<addressOffset>0x00A0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Write Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Write Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Write Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Write Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Write Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Write Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Write Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Write Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Write Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Write Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Write Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Write Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Write Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Write Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Write Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Write Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Write Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Write Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Write Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Write Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Write Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Write Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Write Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Write Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Write Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Write Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Write Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Write Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Write Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Write Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Write Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OWDR</name>
<description>Output Write Disable</description>
<addressOffset>0x00A4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Write Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Write Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Write Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Write Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Write Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Write Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Write Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Write Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Write Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Write Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Write Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Write Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Write Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Write Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Write Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Write Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Write Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Write Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Write Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Write Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Write Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Write Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Write Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Write Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Write Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Write Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Write Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Write Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Write Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Write Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Write Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Write Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OWSR</name>
<description>Output Write Status Register</description>
<addressOffset>0x00A8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Output Write Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Output Write Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Output Write Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Output Write Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Output Write Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Output Write Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Output Write Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Output Write Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Output Write Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Output Write Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Output Write Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Output Write Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Output Write Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Output Write Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Output Write Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Output Write Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Output Write Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Output Write Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Output Write Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Output Write Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Output Write Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Output Write Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Output Write Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Output Write Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Output Write Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Output Write Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Output Write Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Output Write Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Output Write Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Output Write Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Output Write Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Output Write Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIMER</name>
<description>Additional Interrupt Modes Enable Register</description>
<addressOffset>0x00B0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Additional Interrupt Modes Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIMDR</name>
<description>Additional Interrupt Modes Disable Register</description>
<addressOffset>0x00B4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Additional Interrupt Modes Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIMMR</name>
<description>Additional Interrupt Modes Mask Register</description>
<addressOffset>0x00B8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>IO Line Index</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>IO Line Index</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>IO Line Index</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>IO Line Index</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>IO Line Index</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>IO Line Index</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>IO Line Index</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>IO Line Index</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>IO Line Index</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>IO Line Index</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>IO Line Index</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>IO Line Index</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>IO Line Index</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>IO Line Index</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>IO Line Index</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>IO Line Index</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>IO Line Index</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>IO Line Index</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>IO Line Index</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>IO Line Index</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>IO Line Index</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>IO Line Index</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>IO Line Index</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>IO Line Index</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>IO Line Index</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>IO Line Index</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>IO Line Index</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>IO Line Index</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>IO Line Index</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>IO Line Index</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>IO Line Index</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>IO Line Index</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESR</name>
<description>Edge Select Register</description>
<addressOffset>0x00C0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Edge Interrupt Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Edge Interrupt Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Edge Interrupt Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Edge Interrupt Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Edge Interrupt Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Edge Interrupt Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Edge Interrupt Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Edge Interrupt Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Edge Interrupt Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Edge Interrupt Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Edge Interrupt Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Edge Interrupt Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Edge Interrupt Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Edge Interrupt Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Edge Interrupt Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Edge Interrupt Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Edge Interrupt Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Edge Interrupt Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Edge Interrupt Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Edge Interrupt Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Edge Interrupt Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Edge Interrupt Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Edge Interrupt Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Edge Interrupt Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Edge Interrupt Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Edge Interrupt Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Edge Interrupt Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Edge Interrupt Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Edge Interrupt Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Edge Interrupt Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Edge Interrupt Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Edge Interrupt Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSR</name>
<description>Level Select Register</description>
<addressOffset>0x00C4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Level Interrupt Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Level Interrupt Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Level Interrupt Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Level Interrupt Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Level Interrupt Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Level Interrupt Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Level Interrupt Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Level Interrupt Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Level Interrupt Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Level Interrupt Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Level Interrupt Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Level Interrupt Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Level Interrupt Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Level Interrupt Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Level Interrupt Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Level Interrupt Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Level Interrupt Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Level Interrupt Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Level Interrupt Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Level Interrupt Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Level Interrupt Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Level Interrupt Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Level Interrupt Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Level Interrupt Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Level Interrupt Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Level Interrupt Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Level Interrupt Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Level Interrupt Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Level Interrupt Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Level Interrupt Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Level Interrupt Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Level Interrupt Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ELSR</name>
<description>Edge/Level Status Register</description>
<addressOffset>0x00C8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FELLSR</name>
<description>Falling Edge/Low-Level Select Register</description>
<addressOffset>0x00D0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Falling Edge/Low-Level Interrupt Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>REHLSR</name>
<description>Rising Edge/High-Level Select Register</description>
<addressOffset>0x00D4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>P0</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Rising Edge/High-Level Interrupt Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FRLHSR</name>
<description>Fall/Rise - Low/High Status Register</description>
<addressOffset>0x00D8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Edge/Level Interrupt Source Selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOCKSR</name>
<description>Lock Status</description>
<addressOffset>0x00E0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>P0</name>
<description>Lock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1</name>
<description>Lock Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2</name>
<description>Lock Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3</name>
<description>Lock Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4</name>
<description>Lock Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5</name>
<description>Lock Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6</name>
<description>Lock Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7</name>
<description>Lock Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8</name>
<description>Lock Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9</name>
<description>Lock Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10</name>
<description>Lock Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11</name>
<description>Lock Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12</name>
<description>Lock Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13</name>
<description>Lock Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14</name>
<description>Lock Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15</name>
<description>Lock Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16</name>
<description>Lock Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17</name>
<description>Lock Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18</name>
<description>Lock Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19</name>
<description>Lock Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20</name>
<description>Lock Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21</name>
<description>Lock Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22</name>
<description>Lock Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23</name>
<description>Lock Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24</name>
<description>Lock Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25</name>
<description>Lock Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26</name>
<description>Lock Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27</name>
<description>Lock Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28</name>
<description>Lock Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29</name>
<description>Lock Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30</name>
<description>Lock Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P31</name>
<description>Lock Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0x00E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x50494F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0x00E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCHMITT</name>
<description>Schmitt Trigger Register</description>
<addressOffset>0x0100</addressOffset>
<size>32</size>
<fields>
<field>
<name>SCHMITT0</name>
<description>Schmitt Trigger Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT1</name>
<description>Schmitt Trigger Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT2</name>
<description>Schmitt Trigger Control</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT3</name>
<description>Schmitt Trigger Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT4</name>
<description>Schmitt Trigger Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT5</name>
<description>Schmitt Trigger Control</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT6</name>
<description>Schmitt Trigger Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT7</name>
<description>Schmitt Trigger Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT8</name>
<description>Schmitt Trigger Control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT9</name>
<description>Schmitt Trigger Control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT10</name>
<description>Schmitt Trigger Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT11</name>
<description>Schmitt Trigger Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT12</name>
<description>Schmitt Trigger Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT13</name>
<description>Schmitt Trigger Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT14</name>
<description>Schmitt Trigger Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT15</name>
<description>Schmitt Trigger Control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT16</name>
<description>Schmitt Trigger Control</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT17</name>
<description>Schmitt Trigger Control</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT18</name>
<description>Schmitt Trigger Control</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT19</name>
<description>Schmitt Trigger Control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT20</name>
<description>Schmitt Trigger Control</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT21</name>
<description>Schmitt Trigger Control</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT22</name>
<description>Schmitt Trigger Control</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT23</name>
<description>Schmitt Trigger Control</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT24</name>
<description>Schmitt Trigger Control</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT25</name>
<description>Schmitt Trigger Control</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT26</name>
<description>Schmitt Trigger Control</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT27</name>
<description>Schmitt Trigger Control</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT28</name>
<description>Schmitt Trigger Control</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT29</name>
<description>Schmitt Trigger Control</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT30</name>
<description>Schmitt Trigger Control</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCHMITT31</name>
<description>Schmitt Trigger Control</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DRIVER</name>
<description>I/O Drive Register</description>
<addressOffset>0x0118</addressOffset>
<size>32</size>
<fields>
<field>
<name>LINE0</name>
<description>Drive of PIO Line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE0Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE1</name>
<description>Drive of PIO Line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE1Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE2</name>
<description>Drive of PIO Line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE2Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE3</name>
<description>Drive of PIO Line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE3Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE4</name>
<description>Drive of PIO Line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE4Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE5</name>
<description>Drive of PIO Line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE5Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE6</name>
<description>Drive of PIO Line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE6Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE7</name>
<description>Drive of PIO Line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE7Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE8</name>
<description>Drive of PIO Line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE8Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE9</name>
<description>Drive of PIO Line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE9Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE10</name>
<description>Drive of PIO Line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE10Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE11</name>
<description>Drive of PIO Line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE11Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE12</name>
<description>Drive of PIO Line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE12Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE13</name>
<description>Drive of PIO Line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE13Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE14</name>
<description>Drive of PIO Line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE14Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE15</name>
<description>Drive of PIO Line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE15Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE16</name>
<description>Drive of PIO Line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE16Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE17</name>
<description>Drive of PIO Line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE17Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE18</name>
<description>Drive of PIO Line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE18Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE19</name>
<description>Drive of PIO Line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE19Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE20</name>
<description>Drive of PIO Line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE20Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE21</name>
<description>Drive of PIO Line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE21Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE22</name>
<description>Drive of PIO Line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE22Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE23</name>
<description>Drive of PIO Line 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE23Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE24</name>
<description>Drive of PIO Line 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE24Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE25</name>
<description>Drive of PIO Line 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE25Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE26</name>
<description>Drive of PIO Line 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE26Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE27</name>
<description>Drive of PIO Line 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE27Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE28</name>
<description>Drive of PIO Line 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE28Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE29</name>
<description>Drive of PIO Line 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE29Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE30</name>
<description>Drive of PIO Line 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE30Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINE31</name>
<description>Drive of PIO Line 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LINE31Select</name>
<enumeratedValue>
<name>LOW_DRIVE</name>
<description>Lowest drive</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_DRIVE</name>
<description>Highest drive</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCMR</name>
<description>Parallel Capture Mode Register</description>
<addressOffset>0x0150</addressOffset>
<size>32</size>
<fields>
<field>
<name>PCEN</name>
<description>Parallel Capture Mode Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Parallel Capture Mode Data Size</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DSIZESelect</name>
<enumeratedValue>
<name>BYTE</name>
<description>The reception data in the PIO_PCRHR is a byte (8-bit)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALFWORD</name>
<description>The reception data in the PIO_PCRHR is a half-word (16-bit)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WORD</name>
<description>The reception data in the PIO_PCRHR is a word (32-bit)</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALWYS</name>
<description>Parallel Capture Mode Always Sampling</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALFS</name>
<description>Parallel Capture Mode Half Sampling</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRSTS</name>
<description>Parallel Capture Mode First Sample</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCIER</name>
<description>Parallel Capture Interrupt Enable Register</description>
<addressOffset>0x0154</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DRDY</name>
<description>Parallel Capture Mode Data Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Parallel Capture Mode Overrun Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENDRX</name>
<description>End of Reception Transfer Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBUFF</name>
<description>Reception Buffer Full Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCIDR</name>
<description>Parallel Capture Interrupt Disable Register</description>
<addressOffset>0x0158</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DRDY</name>
<description>Parallel Capture Mode Data Ready Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Parallel Capture Mode Overrun Error Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENDRX</name>
<description>End of Reception Transfer Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBUFF</name>
<description>Reception Buffer Full Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCIMR</name>
<description>Parallel Capture Interrupt Mask Register</description>
<addressOffset>0x015C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DRDY</name>
<description>Parallel Capture Mode Data Ready Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Parallel Capture Mode Overrun Error Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENDRX</name>
<description>End of Reception Transfer Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBUFF</name>
<description>Reception Buffer Full Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCISR</name>
<description>Parallel Capture Interrupt Status Register</description>
<addressOffset>0x0160</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DRDY</name>
<description>Parallel Capture Mode Data Ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Parallel Capture Mode Overrun Error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCRHR</name>
<description>Parallel Capture Reception Holding Register</description>
<addressOffset>0x0164</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDATA</name>
<description>Parallel Capture Mode Reception Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="PIOA">
<name>PIOB</name>
<baseAddress>0x400E1000</baseAddress>
<interrupt>
<name>PIOB</name>
<value>11</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PIOA">
<name>PIOD</name>
<baseAddress>0x400E1400</baseAddress>
<interrupt>
<name>PIOD</name>
<value>16</value>
</interrupt>
</peripheral>
<peripheral>
<name>PMC</name>
<version>44006P</version>
<description>Power Management Controller</description>
<groupName>PMC</groupName>
<prependToName>PMC_</prependToName>
<baseAddress>0x400E0600</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x148</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PMC</name>
<value>5</value>
</interrupt>
<registers>
<register>
<name>SCER</name>
<description>System Clock Enable Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>USBCLK</name>
<description>Enable USB FS Clock</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK0</name>
<description>Programmable Clock 0 Output Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK1</name>
<description>Programmable Clock 1 Output Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK2</name>
<description>Programmable Clock 2 Output Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK3</name>
<description>Programmable Clock 3 Output Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK4</name>
<description>Programmable Clock 4 Output Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK5</name>
<description>Programmable Clock 5 Output Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK6</name>
<description>Programmable Clock 6 Output Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK7</name>
<description>Programmable Clock 7 Output Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCDR</name>
<description>System Clock Disable Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>USBCLK</name>
<description>Disable USB FS Clock</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK0</name>
<description>Programmable Clock 0 Output Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK1</name>
<description>Programmable Clock 1 Output Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK2</name>
<description>Programmable Clock 2 Output Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK3</name>
<description>Programmable Clock 3 Output Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK4</name>
<description>Programmable Clock 4 Output Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK5</name>
<description>Programmable Clock 5 Output Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK6</name>
<description>Programmable Clock 6 Output Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK7</name>
<description>Programmable Clock 7 Output Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCSR</name>
<description>System Clock Status Register</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>HCLKS</name>
<description>HCLK Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBCLK</name>
<description>USB FS Clock Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK0</name>
<description>Programmable Clock 0 Output Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK1</name>
<description>Programmable Clock 1 Output Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK2</name>
<description>Programmable Clock 2 Output Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK3</name>
<description>Programmable Clock 3 Output Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK4</name>
<description>Programmable Clock 4 Output Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK5</name>
<description>Programmable Clock 5 Output Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK6</name>
<description>Programmable Clock 6 Output Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCK7</name>
<description>Programmable Clock 7 Output Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCER0</name>
<description>Peripheral Clock Enable Register 0</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral Clock 7 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral Clock 8 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral Clock 10 Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral Clock 11 Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral Clock 13 Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral Clock 14 Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral Clock 15 Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral Clock 16 Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral Clock 18 Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral Clock 19 Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral Clock 20 Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral Clock 21 Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral Clock 22 Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral Clock 23 Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral Clock 24 Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral Clock 25 Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral Clock 26 Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral Clock 27 Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral Clock 28 Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral Clock 29 Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral Clock 30 Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral Clock 31 Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDR0</name>
<description>Peripheral Clock Disable Register 0</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral Clock 7 Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral Clock 8 Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral Clock 10 Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral Clock 11 Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral Clock 13 Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral Clock 14 Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral Clock 15 Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral Clock 16 Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral Clock 18 Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral Clock 19 Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral Clock 20 Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral Clock 21 Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral Clock 22 Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral Clock 23 Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral Clock 24 Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral Clock 25 Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral Clock 26 Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral Clock 27 Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral Clock 28 Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral Clock 29 Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral Clock 30 Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral Clock 31 Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCSR0</name>
<description>Peripheral Clock Status Register 0</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral Clock 7 Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral Clock 8 Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral Clock 10 Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral Clock 11 Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral Clock 13 Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral Clock 14 Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral Clock 15 Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral Clock 16 Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral Clock 18 Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral Clock 19 Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral Clock 20 Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral Clock 21 Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral Clock 22 Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral Clock 23 Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral Clock 24 Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral Clock 25 Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral Clock 26 Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral Clock 27 Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral Clock 28 Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral Clock 29 Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral Clock 30 Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral Clock 31 Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKGR_UCKR</name>
<description>UTMI Clock Register</description>
<addressOffset>0x001C</addressOffset>
<size>32</size>
<fields>
<field>
<name>UPLLEN</name>
<description>UTMI PLL Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPLLCOUNT</name>
<description>UTMI PLL Start-up Time</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKGR_MOR</name>
<description>Main Oscillator Register</description>
<addressOffset>0x0020</addressOffset>
<size>32</size>
<fields>
<field>
<name>MOSCXTEN</name>
<description>Main Crystal Oscillator Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCXTBY</name>
<description>Main Crystal Oscillator Bypass</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITMODE</name>
<description>Wait Mode Command (Write-only)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCEN</name>
<description>Main RC Oscillator Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCF</name>
<description>Main RC Oscillator Frequency Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>MOSCRCFSelect</name>
<enumeratedValue>
<name>_4_MHz</name>
<description>The RC oscillator frequency is at 4 MHz</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_MHz</name>
<description>The RC oscillator frequency is at 8 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_MHz</name>
<description>The RC oscillator frequency is at 12 MHz</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MOSCXTST</name>
<description>Main Crystal Oscillator Startup Time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Write Access Password</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
<value>0x37</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MOSCSEL</name>
<description>Main Clock Oscillator Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDEN</name>
<description>Clock Failure Detector Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XT32KFME</name>
<description>32.768 kHz Crystal Oscillator Frequency Monitoring Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKGR_MCFR</name>
<description>Main Clock Frequency Register</description>
<addressOffset>0x0024</addressOffset>
<size>32</size>
<fields>
<field>
<name>MAINF</name>
<description>Main Clock Frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>MAINFRDY</name>
<description>Main Clock Frequency Measure Ready</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCMEAS</name>
<description>RC Oscillator Frequency Measure (write-only)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCSS</name>
<description>Counter Clock Source Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKGR_PLLAR</name>
<description>PLLA Register</description>
<addressOffset>0x0028</addressOffset>
<size>32</size>
<fields>
<field>
<name>DIVA</name>
<description>PLLA Front End Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>DIVASelect</name>
<enumeratedValue>
<name>_0</name>
<description>Divider output is 0 and PLLA is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS</name>
<description>Divider is bypassed (divide by 1) and PLLA is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLACOUNT</name>
<description>PLLA Counter</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MULA</name>
<description>PLLA Multiplier</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>ONE</name>
<description>Must Be Set to 1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCKR</name>
<description>Master Clock Register</description>
<addressOffset>0x0030</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSS</name>
<description>Master Clock Source Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CSSSelect</name>
<enumeratedValue>
<name>SLOW_CLK</name>
<description>Slow Clock is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>Main Clock is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PLLA_CLK</name>
<description>PLLA Clock is selected</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UPLL_CLK</name>
<description>Divided UPLL Clock is selected</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRES</name>
<description>Processor Clock Prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>PRESSelect</name>
<enumeratedValue>
<name>CLK_1</name>
<description>Selected clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_2</name>
<description>Selected clock divided by 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_4</name>
<description>Selected clock divided by 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_8</name>
<description>Selected clock divided by 8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_16</name>
<description>Selected clock divided by 16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_32</name>
<description>Selected clock divided by 32</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_64</name>
<description>Selected clock divided by 64</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_3</name>
<description>Selected clock divided by 3</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIV</name>
<description>Master Clock Division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>MDIVSelect</name>
<enumeratedValue>
<name>EQ_PCK</name>
<description>Master Clock is Prescaler Output Clock divided by 1.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PCK_DIV2</name>
<description>Master Clock is Prescaler Output Clock divided by 2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PCK_DIV4</name>
<description>Master Clock is Prescaler Output Clock divided by 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>PCK_DIV3</name>
<description>Master Clock is Prescaler Output Clock divided by 3.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UPLLDIV2</name>
<description>UPLL Divider by 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>USB</name>
<description>USB Clock Register</description>
<addressOffset>0x0038</addressOffset>
<size>32</size>
<fields>
<field>
<name>USBS</name>
<description>USB Input Clock Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBDIV</name>
<description>Divider for USB_48M</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>PCK[%s]</name>
<description>Programmable Clock Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSS</name>
<description>Programmable Clock Source Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CSSSelect</name>
<enumeratedValue>
<name>SLOW_CLK</name>
<description>SLCK is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>MAINCK is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PLLA_CLK</name>
<description>PLLACK is selected</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UPLL_CLK</name>
<description>UPLLCKDIV is selected</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK</name>
<description>MCK is selected</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRES</name>
<description>Programmable Clock Prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x0060</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>MOSCXTS</name>
<description>Main Crystal Oscillator Status Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKA</name>
<description>PLLA Lock Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKRDY</name>
<description>Master Clock Ready Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKU</name>
<description>UTMI PLL Lock Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY0</name>
<description>Programmable Clock Ready 0 Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY1</name>
<description>Programmable Clock Ready 1 Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY2</name>
<description>Programmable Clock Ready 2 Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY3</name>
<description>Programmable Clock Ready 3 Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY4</name>
<description>Programmable Clock Ready 4 Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY5</name>
<description>Programmable Clock Ready 5 Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY6</name>
<description>Programmable Clock Ready 6 Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY7</name>
<description>Programmable Clock Ready 7 Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCSELS</name>
<description>Main Clock Source Oscillator Selection Status Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCS</name>
<description>Main RC Oscillator Status Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDEV</name>
<description>Clock Failure Detector Event Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XT32KERR</name>
<description>32.768 kHz Crystal Oscillator Error Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x0064</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>MOSCXTS</name>
<description>Main Crystal Oscillator Status Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKA</name>
<description>PLLA Lock Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKRDY</name>
<description>Master Clock Ready Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKU</name>
<description>UTMI PLL Lock Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY0</name>
<description>Programmable Clock Ready 0 Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY1</name>
<description>Programmable Clock Ready 1 Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY2</name>
<description>Programmable Clock Ready 2 Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY3</name>
<description>Programmable Clock Ready 3 Interrupt Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY4</name>
<description>Programmable Clock Ready 4 Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY5</name>
<description>Programmable Clock Ready 5 Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY6</name>
<description>Programmable Clock Ready 6 Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY7</name>
<description>Programmable Clock Ready 7 Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCSELS</name>
<description>Main Clock Source Oscillator Selection Status Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCS</name>
<description>Main RC Status Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDEV</name>
<description>Clock Failure Detector Event Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XT32KERR</name>
<description>32.768 kHz Crystal Oscillator Error Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x0068</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MOSCXTS</name>
<description>Main Crystal Oscillator Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKA</name>
<description>PLLA Lock Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKRDY</name>
<description>Master Clock Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKU</name>
<description>UTMI PLL Lock Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCSELS</name>
<description>Slow Clock Source Oscillator Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY0</name>
<description>Programmable Clock Ready 0 Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY1</name>
<description>Programmable Clock Ready 1 Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY2</name>
<description>Programmable Clock Ready 2 Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY3</name>
<description>Programmable Clock Ready 3 Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY4</name>
<description>Programmable Clock Ready 4 Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY5</name>
<description>Programmable Clock Ready 5 Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY6</name>
<description>Programmable Clock Ready 6 Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY7</name>
<description>Programmable Clock Ready 7 Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCSELS</name>
<description>Main Clock Source Oscillator Selection Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCS</name>
<description>Main RC Oscillator Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDEV</name>
<description>Clock Failure Detector Event</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDS</name>
<description>Clock Failure Detector Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FOS</name>
<description>Clock Failure Detector Fault Output Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XT32KERR</name>
<description>Slow Crystal Oscillator Error</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x006C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MOSCXTS</name>
<description>Main Crystal Oscillator Status Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKA</name>
<description>PLLA Lock Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKRDY</name>
<description>Master Clock Ready Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKU</name>
<description>UTMI PLL Lock Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY0</name>
<description>Programmable Clock Ready 0 Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY1</name>
<description>Programmable Clock Ready 1 Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY2</name>
<description>Programmable Clock Ready 2 Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY3</name>
<description>Programmable Clock Ready 3 Interrupt Mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY4</name>
<description>Programmable Clock Ready 4 Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY5</name>
<description>Programmable Clock Ready 5 Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY6</name>
<description>Programmable Clock Ready 6 Interrupt Mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKRDY7</name>
<description>Programmable Clock Ready 7 Interrupt Mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCSELS</name>
<description>Main Clock Source Oscillator Selection Status Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOSCRCS</name>
<description>Main RC Status Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFDEV</name>
<description>Clock Failure Detector Event Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XT32KERR</name>
<description>32.768 kHz Crystal Oscillator Error Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FSMR</name>
<description>Fast Startup Mode Register</description>
<addressOffset>0x0070</addressOffset>
<size>32</size>
<fields>
<field>
<name>FSTT0</name>
<description>Fast Startup Input Enable 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT1</name>
<description>Fast Startup Input Enable 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT2</name>
<description>Fast Startup Input Enable 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT3</name>
<description>Fast Startup Input Enable 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT4</name>
<description>Fast Startup Input Enable 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT5</name>
<description>Fast Startup Input Enable 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT6</name>
<description>Fast Startup Input Enable 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT7</name>
<description>Fast Startup Input Enable 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT8</name>
<description>Fast Startup Input Enable 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT9</name>
<description>Fast Startup Input Enable 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT10</name>
<description>Fast Startup Input Enable 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT11</name>
<description>Fast Startup Input Enable 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT12</name>
<description>Fast Startup Input Enable 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT13</name>
<description>Fast Startup Input Enable 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT14</name>
<description>Fast Startup Input Enable 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTT15</name>
<description>Fast Startup Input Enable 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTTAL</name>
<description>RTT Alarm Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCAL</name>
<description>RTC Alarm Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBAL</name>
<description>USB Alarm Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPM</name>
<description>Low-power Mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLPM</name>
<description>Flash Low-power Mode</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>FLPMSelect</name>
<enumeratedValue>
<name>FLASH_STANDBY</name>
<description>Flash is in Standby Mode when system enters Wait Mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FLASH_DEEP_POWERDOWN</name>
<description>Flash is in Deep-power-down mode when system enters Wait Mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FLASH_IDLE</name>
<description>Idle mode</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLPM</name>
<description>Force Flash Low-power Mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FSPR</name>
<description>Fast Startup Polarity Register</description>
<addressOffset>0x0074</addressOffset>
<size>32</size>
<fields>
<field>
<name>FSTP0</name>
<description>Fast Startup Input Polarity 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP1</name>
<description>Fast Startup Input Polarity 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP2</name>
<description>Fast Startup Input Polarity 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP3</name>
<description>Fast Startup Input Polarity 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP4</name>
<description>Fast Startup Input Polarity 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP5</name>
<description>Fast Startup Input Polarity 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP6</name>
<description>Fast Startup Input Polarity 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP7</name>
<description>Fast Startup Input Polarity 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP8</name>
<description>Fast Startup Input Polarity 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP9</name>
<description>Fast Startup Input Polarity 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP10</name>
<description>Fast Startup Input Polarity 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP11</name>
<description>Fast Startup Input Polarity 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP12</name>
<description>Fast Startup Input Polarity 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP13</name>
<description>Fast Startup Input Polarity 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP14</name>
<description>Fast Startup Input Polarity 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTP15</name>
<description>Fast Startup Input Polarity 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FOCR</name>
<description>Fault Output Clear Register</description>
<addressOffset>0x0078</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>FOCLR</name>
<description>Fault Output Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0x00E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
<value>0x504D43</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0x00E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCER1</name>
<description>Peripheral Clock Enable Register 1</description>
<addressOffset>0x0100</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral Clock 32 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral Clock 33 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral Clock 34 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral Clock 35 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral Clock 37 Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral Clock 39 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral Clock 40 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral Clock 41 Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral Clock 43 Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral Clock 44 Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral Clock 45 Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral Clock 46 Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral Clock 47 Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral Clock 48 Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral Clock 49 Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral Clock 50 Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral Clock 51 Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral Clock 52 Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral Clock 53 Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral Clock 56 Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral Clock 57 Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral Clock 58 Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral Clock 59 Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral Clock 60 Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCDR1</name>
<description>Peripheral Clock Disable Register 1</description>
<addressOffset>0x0104</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral Clock 32 Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral Clock 33 Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral Clock 34 Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral Clock 35 Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral Clock 37 Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral Clock 39 Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral Clock 40 Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral Clock 41 Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral Clock 43 Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral Clock 44 Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral Clock 45 Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral Clock 46 Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral Clock 47 Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral Clock 48 Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral Clock 49 Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral Clock 50 Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral Clock 51 Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral Clock 52 Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral Clock 53 Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral Clock 56 Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral Clock 57 Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral Clock 58 Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral Clock 59 Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral Clock 60 Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCSR1</name>
<description>Peripheral Clock Status Register 1</description>
<addressOffset>0x0108</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral Clock 32 Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral Clock 33 Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral Clock 34 Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral Clock 35 Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral Clock 37 Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral Clock 39 Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral Clock 40 Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral Clock 41 Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral Clock 43 Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral Clock 44 Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral Clock 45 Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral Clock 46 Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral Clock 47 Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral Clock 48 Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral Clock 49 Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral Clock 50 Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral Clock 51 Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral Clock 52 Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral Clock 53 Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral Clock 56 Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral Clock 57 Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral Clock 58 Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral Clock 59 Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral Clock 60 Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCR</name>
<description>Peripheral Control Register</description>
<addressOffset>0x010C</addressOffset>
<size>32</size>
<fields>
<field>
<name>PID</name>
<description>Peripheral ID</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>GCLKCSS</name>
<description>Generic Clock Source Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>GCLKCSSSelect</name>
<enumeratedValue>
<name>SLOW_CLK</name>
<description>Slow clock is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>Main clock is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PLLA_CLK</name>
<description>PLLACK is selected</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UPLL_CLK</name>
<description>UPLL Clock is selected</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_CLK</name>
<description>Master Clock is selected</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Command</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCLKDIV</name>
<description>Generic Clock Division Ratio</description>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EN</name>
<description>Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCLKEN</name>
<description>Generic Clock Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OCR</name>
<description>Oscillator Calibration Register</description>
<addressOffset>0x0110</addressOffset>
<size>32</size>
<fields>
<field>
<name>CAL4</name>
<description>Main RC Oscillator Calibration Bits for 4 MHz</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SEL4</name>
<description>Selection of Main RC Oscillator Calibration Bits for 4 MHz</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL8</name>
<description>Main RC Oscillator Calibration Bits for 8 MHz</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SEL8</name>
<description>Selection of Main RC Oscillator Calibration Bits for 8 MHz</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL12</name>
<description>Main RC Oscillator Calibration Bits for 12 MHz</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SEL12</name>
<description>Selection of Main RC Oscillator Calibration Bits for 12 MHz</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_ER0</name>
<description>SleepWalking Enable Register 0</description>
<addressOffset>0x0114</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral 7 SleepWalking Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral 8 SleepWalking Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral 10 SleepWalking Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral 11 SleepWalking Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral 13 SleepWalking Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral 14 SleepWalking Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral 15 SleepWalking Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral 16 SleepWalking Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral 18 SleepWalking Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral 19 SleepWalking Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral 20 SleepWalking Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral 21 SleepWalking Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral 22 SleepWalking Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral 23 SleepWalking Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral 24 SleepWalking Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral 25 SleepWalking Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral 26 SleepWalking Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral 27 SleepWalking Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral 28 SleepWalking Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral 29 SleepWalking Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral 30 SleepWalking Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral 31 SleepWalking Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_DR0</name>
<description>SleepWalking Disable Register 0</description>
<addressOffset>0x0118</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral 7 SleepWalking Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral 8 SleepWalking Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral 10 SleepWalking Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral 11 SleepWalking Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral 13 SleepWalking Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral 14 SleepWalking Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral 15 SleepWalking Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral 16 SleepWalking Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral 18 SleepWalking Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral 19 SleepWalking Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral 20 SleepWalking Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral 21 SleepWalking Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral 22 SleepWalking Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral 23 SleepWalking Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral 24 SleepWalking Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral 25 SleepWalking Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral 26 SleepWalking Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral 27 SleepWalking Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral 28 SleepWalking Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral 29 SleepWalking Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral 30 SleepWalking Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral 31 SleepWalking Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_SR0</name>
<description>SleepWalking Status Register 0</description>
<addressOffset>0x011C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral 7 SleepWalking Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral 8 SleepWalking Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral 10 SleepWalking Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral 11 SleepWalking Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral 13 SleepWalking Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral 14 SleepWalking Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral 15 SleepWalking Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral 16 SleepWalking Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral 18 SleepWalking Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral 19 SleepWalking Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral 20 SleepWalking Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral 21 SleepWalking Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral 22 SleepWalking Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral 23 SleepWalking Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral 24 SleepWalking Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral 25 SleepWalking Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral 26 SleepWalking Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral 27 SleepWalking Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral 28 SleepWalking Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral 29 SleepWalking Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral 30 SleepWalking Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral 31 SleepWalking Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_ASR0</name>
<description>SleepWalking Activity Status Register 0</description>
<addressOffset>0x0120</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID7</name>
<description>Peripheral 7 Activity Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID8</name>
<description>Peripheral 8 Activity Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID10</name>
<description>Peripheral 10 Activity Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID11</name>
<description>Peripheral 11 Activity Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID13</name>
<description>Peripheral 13 Activity Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID14</name>
<description>Peripheral 14 Activity Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID15</name>
<description>Peripheral 15 Activity Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID16</name>
<description>Peripheral 16 Activity Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID18</name>
<description>Peripheral 18 Activity Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID19</name>
<description>Peripheral 19 Activity Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID20</name>
<description>Peripheral 20 Activity Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID21</name>
<description>Peripheral 21 Activity Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID22</name>
<description>Peripheral 22 Activity Status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID23</name>
<description>Peripheral 23 Activity Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID24</name>
<description>Peripheral 24 Activity Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID25</name>
<description>Peripheral 25 Activity Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID26</name>
<description>Peripheral 26 Activity Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID27</name>
<description>Peripheral 27 Activity Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID28</name>
<description>Peripheral 28 Activity Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID29</name>
<description>Peripheral 29 Activity Status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID30</name>
<description>Peripheral 30 Activity Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID31</name>
<description>Peripheral 31 Activity Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMMR</name>
<description>PLL Maximum Multiplier Value Register</description>
<addressOffset>0x0130</addressOffset>
<size>32</size>
<fields>
<field>
<name>PLLA_MMAX</name>
<description>PLLA Maximum Allowed Multiplier Value</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_ER1</name>
<description>SleepWalking Enable Register 1</description>
<addressOffset>0x0134</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral 32 SleepWalking Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral 33 SleepWalking Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral 34 SleepWalking Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral 35 SleepWalking Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral 37 SleepWalking Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral 39 SleepWalking Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral 40 SleepWalking Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral 41 SleepWalking Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral 43 SleepWalking Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral 44 SleepWalking Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral 45 SleepWalking Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral 46 SleepWalking Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral 47 SleepWalking Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral 48 SleepWalking Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral 49 SleepWalking Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral 50 SleepWalking Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral 51 SleepWalking Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral 52 SleepWalking Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral 53 SleepWalking Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral 56 SleepWalking Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral 57 SleepWalking Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral 58 SleepWalking Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral 59 SleepWalking Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral 60 SleepWalking Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_DR1</name>
<description>SleepWalking Disable Register 1</description>
<addressOffset>0x0138</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral 32 SleepWalking Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral 33 SleepWalking Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral 34 SleepWalking Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral 35 SleepWalking Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral 37 SleepWalking Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral 39 SleepWalking Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral 40 SleepWalking Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral 41 SleepWalking Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral 43 SleepWalking Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral 44 SleepWalking Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral 45 SleepWalking Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral 46 SleepWalking Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral 47 SleepWalking Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral 48 SleepWalking Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral 49 SleepWalking Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral 50 SleepWalking Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral 51 SleepWalking Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral 52 SleepWalking Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral 53 SleepWalking Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral 56 SleepWalking Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral 57 SleepWalking Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral 58 SleepWalking Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral 59 SleepWalking Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral 60 SleepWalking Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_SR1</name>
<description>SleepWalking Status Register 1</description>
<addressOffset>0x013C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral 32 SleepWalking Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral 33 SleepWalking Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral 34 SleepWalking Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral 35 SleepWalking Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral 37 SleepWalking Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral 39 SleepWalking Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral 40 SleepWalking Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral 41 SleepWalking Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral 43 SleepWalking Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral 44 SleepWalking Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral 45 SleepWalking Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral 46 SleepWalking Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral 47 SleepWalking Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral 48 SleepWalking Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral 49 SleepWalking Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral 50 SleepWalking Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral 51 SleepWalking Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral 52 SleepWalking Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral 53 SleepWalking Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral 56 SleepWalking Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral 57 SleepWalking Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral 58 SleepWalking Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral 59 SleepWalking Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral 60 SleepWalking Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_ASR1</name>
<description>SleepWalking Activity Status Register 1</description>
<addressOffset>0x0140</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>PID32</name>
<description>Peripheral 32 Activity Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID33</name>
<description>Peripheral 33 Activity Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID34</name>
<description>Peripheral 34 Activity Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID35</name>
<description>Peripheral 35 Activity Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID37</name>
<description>Peripheral 37 Activity Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID39</name>
<description>Peripheral 39 Activity Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID40</name>
<description>Peripheral 40 Activity Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID41</name>
<description>Peripheral 41 Activity Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID43</name>
<description>Peripheral 43 Activity Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID44</name>
<description>Peripheral 44 Activity Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID45</name>
<description>Peripheral 45 Activity Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID46</name>
<description>Peripheral 46 Activity Status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID47</name>
<description>Peripheral 47 Activity Status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID48</name>
<description>Peripheral 48 Activity Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID49</name>
<description>Peripheral 49 Activity Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID50</name>
<description>Peripheral 50 Activity Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID51</name>
<description>Peripheral 51 Activity Status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID52</name>
<description>Peripheral 52 Activity Status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID53</name>
<description>Peripheral 53 Activity Status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID56</name>
<description>Peripheral 56 Activity Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID57</name>
<description>Peripheral 57 Activity Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID58</name>
<description>Peripheral 58 Activity Status</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID59</name>
<description>Peripheral 59 Activity Status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID60</name>
<description>Peripheral 60 Activity Status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPWK_AIPR</name>
<description>SleepWalking Activity In Progress Register</description>
<addressOffset>0x0144</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>AIP</name>
<description>Activity In Progress</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWM0</name>
<version>6343Y</version>
<description>Pulse Width Modulation Controller</description>
<groupName>PWM</groupName>
<prependToName>PWM_</prependToName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x464</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PWM0</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>CLK</name>
<description>PWM Clock Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>DIVA</name>
<description>CLKA Divide Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>DIVASelect</name>
<enumeratedValue>
<name>CLKA_POFF</name>
<description>CLKA clock is turned off</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PREA</name>
<description>CLKA clock is clock selected by PREA</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PREA</name>
<description>CLKA Source Clock Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>PREASelect</name>
<enumeratedValue>
<name>CLK</name>
<description>Peripheral clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV2</name>
<description>Peripheral clock/2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV4</name>
<description>Peripheral clock/4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV8</name>
<description>Peripheral clock/8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV16</name>
<description>Peripheral clock/16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV32</name>
<description>Peripheral clock/32</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV64</name>
<description>Peripheral clock/64</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV128</name>
<description>Peripheral clock/128</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV256</name>
<description>Peripheral clock/256</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV512</name>
<description>Peripheral clock/512</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV1024</name>
<description>Peripheral clock/1024</description>
<value>0xA</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVB</name>
<description>CLKB Divide Factor</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>DIVBSelect</name>
<enumeratedValue>
<name>CLKB_POFF</name>
<description>CLKB clock is turned off</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PREB</name>
<description>CLKB clock is clock selected by PREB</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PREB</name>
<description>CLKB Source Clock Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>PREBSelect</name>
<enumeratedValue>
<name>CLK</name>
<description>Peripheral clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV2</name>
<description>Peripheral clock/2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV4</name>
<description>Peripheral clock/4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV8</name>
<description>Peripheral clock/8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV16</name>
<description>Peripheral clock/16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV32</name>
<description>Peripheral clock/32</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV64</name>
<description>Peripheral clock/64</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV128</name>
<description>Peripheral clock/128</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV256</name>
<description>Peripheral clock/256</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV512</name>
<description>Peripheral clock/512</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_DIV1024</name>
<description>Peripheral clock/1024</description>
<value>0xA</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ENA</name>
<description>PWM Enable Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Channel ID</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Channel ID</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Channel ID</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Channel ID</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIS</name>
<description>PWM Disable Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Channel ID</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Channel ID</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Channel ID</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Channel ID</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>PWM Status Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Channel ID</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Channel ID</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Channel ID</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Channel ID</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER1</name>
<description>PWM Interrupt Enable Register 1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Counter Event on Channel 0 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Counter Event on Channel 1 Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Counter Event on Channel 2 Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Counter Event on Channel 3 Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID0</name>
<description>Fault Protection Trigger on Channel 0 Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID1</name>
<description>Fault Protection Trigger on Channel 1 Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID2</name>
<description>Fault Protection Trigger on Channel 2 Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID3</name>
<description>Fault Protection Trigger on Channel 3 Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR1</name>
<description>PWM Interrupt Disable Register 1</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Counter Event on Channel 0 Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Counter Event on Channel 1 Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Counter Event on Channel 2 Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Counter Event on Channel 3 Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID0</name>
<description>Fault Protection Trigger on Channel 0 Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID1</name>
<description>Fault Protection Trigger on Channel 1 Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID2</name>
<description>Fault Protection Trigger on Channel 2 Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID3</name>
<description>Fault Protection Trigger on Channel 3 Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR1</name>
<description>PWM Interrupt Mask Register 1</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Counter Event on Channel 0 Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Counter Event on Channel 1 Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Counter Event on Channel 2 Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Counter Event on Channel 3 Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID0</name>
<description>Fault Protection Trigger on Channel 0 Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID1</name>
<description>Fault Protection Trigger on Channel 1 Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID2</name>
<description>Fault Protection Trigger on Channel 2 Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID3</name>
<description>Fault Protection Trigger on Channel 3 Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR1</name>
<description>PWM Interrupt Status Register 1</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CHID0</name>
<description>Counter Event on Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID1</name>
<description>Counter Event on Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID2</name>
<description>Counter Event on Channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHID3</name>
<description>Counter Event on Channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID0</name>
<description>Fault Protection Trigger on Channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID1</name>
<description>Fault Protection Trigger on Channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID2</name>
<description>Fault Protection Trigger on Channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCHID3</name>
<description>Fault Protection Trigger on Channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCM</name>
<description>PWM Sync Channels Mode Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<fields>
<field>
<name>SYNC0</name>
<description>Synchronous Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC1</name>
<description>Synchronous Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC2</name>
<description>Synchronous Channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC3</name>
<description>Synchronous Channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDM</name>
<description>Synchronous Channels Update Mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>UPDMSelect</name>
<enumeratedValue>
<name>MODE0</name>
<description>Manual write of double buffer registers and manual update of synchronous channels</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Manual write of double buffer registers and automatic update of synchronous channels</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PTRM</name>
<description>DMA Controller Transfer Request Mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTRCS</name>
<description>DMA Controller Transfer Request Comparison Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<description>PWM DMA Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DMADUTY</name>
<description>Duty-Cycle Holding Register for DMA Access</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCUC</name>
<description>PWM Sync Channels Update Control Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<fields>
<field>
<name>UPDULOCK</name>
<description>Synchronous Channels Update Unlock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCUP</name>
<description>PWM Sync Channels Update Period Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<fields>
<field>
<name>UPR</name>
<description>Update Period</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>UPRCNT</name>
<description>Update Period Counter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCUPUPD</name>
<description>PWM Sync Channels Update Period Update Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>UPRUPD</name>
<description>Update Period Update</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER2</name>
<description>PWM Interrupt Enable Register 2</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>WRDY</name>
<description>Write Ready for Synchronous Channels Update Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Synchronous Channels Update Underrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM0</name>
<description>Comparison 0 Match Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM1</name>
<description>Comparison 1 Match Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM2</name>
<description>Comparison 2 Match Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM3</name>
<description>Comparison 3 Match Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM4</name>
<description>Comparison 4 Match Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM5</name>
<description>Comparison 5 Match Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM6</name>
<description>Comparison 6 Match Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM7</name>
<description>Comparison 7 Match Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU0</name>
<description>Comparison 0 Update Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU1</name>
<description>Comparison 1 Update Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU2</name>
<description>Comparison 2 Update Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU3</name>
<description>Comparison 3 Update Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU4</name>
<description>Comparison 4 Update Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU5</name>
<description>Comparison 5 Update Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU6</name>
<description>Comparison 6 Update Interrupt Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU7</name>
<description>Comparison 7 Update Interrupt Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR2</name>
<description>PWM Interrupt Disable Register 2</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>WRDY</name>
<description>Write Ready for Synchronous Channels Update Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Synchronous Channels Update Underrun Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM0</name>
<description>Comparison 0 Match Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM1</name>
<description>Comparison 1 Match Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM2</name>
<description>Comparison 2 Match Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM3</name>
<description>Comparison 3 Match Interrupt Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM4</name>
<description>Comparison 4 Match Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM5</name>
<description>Comparison 5 Match Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM6</name>
<description>Comparison 6 Match Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM7</name>
<description>Comparison 7 Match Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU0</name>
<description>Comparison 0 Update Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU1</name>
<description>Comparison 1 Update Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU2</name>
<description>Comparison 2 Update Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU3</name>
<description>Comparison 3 Update Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU4</name>
<description>Comparison 4 Update Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU5</name>
<description>Comparison 5 Update Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU6</name>
<description>Comparison 6 Update Interrupt Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU7</name>
<description>Comparison 7 Update Interrupt Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR2</name>
<description>PWM Interrupt Mask Register 2</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WRDY</name>
<description>Write Ready for Synchronous Channels Update Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Synchronous Channels Update Underrun Error Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM0</name>
<description>Comparison 0 Match Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM1</name>
<description>Comparison 1 Match Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM2</name>
<description>Comparison 2 Match Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM3</name>
<description>Comparison 3 Match Interrupt Mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM4</name>
<description>Comparison 4 Match Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM5</name>
<description>Comparison 5 Match Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM6</name>
<description>Comparison 6 Match Interrupt Mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM7</name>
<description>Comparison 7 Match Interrupt Mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU0</name>
<description>Comparison 0 Update Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU1</name>
<description>Comparison 1 Update Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU2</name>
<description>Comparison 2 Update Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU3</name>
<description>Comparison 3 Update Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU4</name>
<description>Comparison 4 Update Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU5</name>
<description>Comparison 5 Update Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU6</name>
<description>Comparison 6 Update Interrupt Mask</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU7</name>
<description>Comparison 7 Update Interrupt Mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR2</name>
<description>PWM Interrupt Status Register 2</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WRDY</name>
<description>Write Ready for Synchronous Channels Update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Synchronous Channels Update Underrun Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM0</name>
<description>Comparison 0 Match</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM1</name>
<description>Comparison 1 Match</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM2</name>
<description>Comparison 2 Match</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM3</name>
<description>Comparison 3 Match</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM4</name>
<description>Comparison 4 Match</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM5</name>
<description>Comparison 5 Match</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM6</name>
<description>Comparison 6 Match</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM7</name>
<description>Comparison 7 Match</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU0</name>
<description>Comparison 0 Update</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU1</name>
<description>Comparison 1 Update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU2</name>
<description>Comparison 2 Update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU3</name>
<description>Comparison 3 Update</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU4</name>
<description>Comparison 4 Update</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU5</name>
<description>Comparison 5 Update</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU6</name>
<description>Comparison 6 Update</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPU7</name>
<description>Comparison 7 Update</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OOV</name>
<description>PWM Output Override Value Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<fields>
<field>
<name>OOVH0</name>
<description>Output Override Value for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVH1</name>
<description>Output Override Value for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVH2</name>
<description>Output Override Value for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVH3</name>
<description>Output Override Value for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVL0</name>
<description>Output Override Value for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVL1</name>
<description>Output Override Value for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVL2</name>
<description>Output Override Value for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OOVL3</name>
<description>Output Override Value for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OS</name>
<description>PWM Output Selection Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<fields>
<field>
<name>OSH0</name>
<description>Output Selection for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSH1</name>
<description>Output Selection for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSH2</name>
<description>Output Selection for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSH3</name>
<description>Output Selection for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSL0</name>
<description>Output Selection for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSL1</name>
<description>Output Selection for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSL2</name>
<description>Output Selection for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSL3</name>
<description>Output Selection for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSS</name>
<description>PWM Output Selection Set Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>OSSH0</name>
<description>Output Selection Set for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSH1</name>
<description>Output Selection Set for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSH2</name>
<description>Output Selection Set for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSH3</name>
<description>Output Selection Set for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSL0</name>
<description>Output Selection Set for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSL1</name>
<description>Output Selection Set for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSL2</name>
<description>Output Selection Set for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSL3</name>
<description>Output Selection Set for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSC</name>
<description>PWM Output Selection Clear Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>OSCH0</name>
<description>Output Selection Clear for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCH1</name>
<description>Output Selection Clear for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCH2</name>
<description>Output Selection Clear for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCH3</name>
<description>Output Selection Clear for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCL0</name>
<description>Output Selection Clear for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCL1</name>
<description>Output Selection Clear for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCL2</name>
<description>Output Selection Clear for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCL3</name>
<description>Output Selection Clear for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSSUPD</name>
<description>PWM Output Selection Set Update Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>OSSUPH0</name>
<description>Output Selection Set for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPH1</name>
<description>Output Selection Set for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPH2</name>
<description>Output Selection Set for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPH3</name>
<description>Output Selection Set for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPL0</name>
<description>Output Selection Set for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPL1</name>
<description>Output Selection Set for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPL2</name>
<description>Output Selection Set for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSUPL3</name>
<description>Output Selection Set for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSCUPD</name>
<description>PWM Output Selection Clear Update Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>OSCUPH0</name>
<description>Output Selection Clear for PWMH output of the channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPH1</name>
<description>Output Selection Clear for PWMH output of the channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPH2</name>
<description>Output Selection Clear for PWMH output of the channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPH3</name>
<description>Output Selection Clear for PWMH output of the channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPL0</name>
<description>Output Selection Clear for PWML output of the channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPL1</name>
<description>Output Selection Clear for PWML output of the channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPL2</name>
<description>Output Selection Clear for PWML output of the channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCUPL3</name>
<description>Output Selection Clear for PWML output of the channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FMR</name>
<description>PWM Fault Mode Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<fields>
<field>
<name>FPOL</name>
<description>Fault Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FMOD</name>
<description>Fault Activation Mode</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FFIL</name>
<description>Fault Filtering</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FSR</name>
<description>PWM Fault Status Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>FIV</name>
<description>Fault Input Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FS</name>
<description>Fault Status</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<description>PWM Fault Clear Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>FCLR</name>
<description>Fault Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPV1</name>
<description>PWM Fault Protection Value Register 1</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<fields>
<field>
<name>FPVH0</name>
<description>Fault Protection Value for PWMH output on channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVH1</name>
<description>Fault Protection Value for PWMH output on channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVH2</name>
<description>Fault Protection Value for PWMH output on channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVH3</name>
<description>Fault Protection Value for PWMH output on channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVL0</name>
<description>Fault Protection Value for PWML output on channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVL1</name>
<description>Fault Protection Value for PWML output on channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVL2</name>
<description>Fault Protection Value for PWML output on channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPVL3</name>
<description>Fault Protection Value for PWML output on channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPE</name>
<description>PWM Fault Protection Enable Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<fields>
<field>
<name>FPE0</name>
<description>Fault Protection Enable for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FPE1</name>
<description>Fault Protection Enable for channel 1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FPE2</name>
<description>Fault Protection Enable for channel 2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FPE3</name>
<description>Fault Protection Enable for channel 3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>4</dimIncrement>
<name>ELMR[%s]</name>
<description>PWM Event Line 0 Mode Register 0</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CSEL0</name>
<description>Comparison 0 Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL1</name>
<description>Comparison 1 Selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL2</name>
<description>Comparison 2 Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL3</name>
<description>Comparison 3 Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL4</name>
<description>Comparison 4 Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL5</name>
<description>Comparison 5 Selection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL6</name>
<description>Comparison 6 Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSEL7</name>
<description>Comparison 7 Selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SSPR</name>
<description>PWM Spread Spectrum Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<fields>
<field>
<name>SPRD</name>
<description>Spread Spectrum Limit Value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SPRDM</name>
<description>Spread Spectrum Counter Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SSPUP</name>
<description>PWM Spread Spectrum Update Register</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SPRDUP</name>
<description>Spread Spectrum Limit Value Update</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMMR</name>
<description>PWM Stepper Motor Mode Register</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<fields>
<field>
<name>GCEN0</name>
<description>Gray Count ENable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCEN1</name>
<description>Gray Count ENable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DOWN0</name>
<description>DOWN Count</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DOWN1</name>
<description>DOWN Count</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPV2</name>
<description>PWM Fault Protection Value 2 Register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<fields>
<field>
<name>FPZH0</name>
<description>Fault Protection to Hi-Z for PWMH output on channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZH1</name>
<description>Fault Protection to Hi-Z for PWMH output on channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZH2</name>
<description>Fault Protection to Hi-Z for PWMH output on channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZH3</name>
<description>Fault Protection to Hi-Z for PWMH output on channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZL0</name>
<description>Fault Protection to Hi-Z for PWML output on channel 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZL1</name>
<description>Fault Protection to Hi-Z for PWML output on channel 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZL2</name>
<description>Fault Protection to Hi-Z for PWML output on channel 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPZL3</name>
<description>Fault Protection to Hi-Z for PWML output on channel 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPCR</name>
<description>PWM Write Protection Control Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>WPCMD</name>
<description>Write Protection Command</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>WPCMDSelect</name>
<enumeratedValue>
<name>DISABLE_SW_PROT</name>
<description>Disables the software write protection of the register groups of which the bit WPRGx is at '1'.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_SW_PROT</name>
<description>Enables the software write protection of the register groups of which the bit WPRGx is at '1'.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_HW_PROT</name>
<description>Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPRG0</name>
<description>Write Protection Register Group 0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPRG1</name>
<description>Write Protection Register Group 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPRG2</name>
<description>Write Protection Register Group 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPRG3</name>
<description>Write Protection Register Group 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPRG4</name>
<description>Write Protection Register Group 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPRG5</name>
<description>Write Protection Register Group 5</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0</description>
<value>0x50574D</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>PWM Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPSWS0</name>
<description>Write Protect SW Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSWS1</name>
<description>Write Protect SW Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSWS2</name>
<description>Write Protect SW Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSWS3</name>
<description>Write Protect SW Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSWS4</name>
<description>Write Protect SW Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPSWS5</name>
<description>Write Protect SW Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVS</name>
<description>Write Protect Violation Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS0</name>
<description>Write Protect HW Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS1</name>
<description>Write Protect HW Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS2</name>
<description>Write Protect HW Status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS3</name>
<description>Write Protect HW Status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS4</name>
<description>Write Protect HW Status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPHWS5</name>
<description>Write Protect HW Status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protect Violation Source</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>8</dim>
<dimIncrement>16</dimIncrement>
<name>PWM_CMP[%s]</name>
<description>PWM Comparison 0 Value Register</description>
<addressOffset>0x130</addressOffset>
<register>
<name>CMPV</name>
<description>PWM Comparison 0 Value Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>CV</name>
<description>Comparison x Value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>CVM</name>
<description>Comparison x Value Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CVMSelect</name>
<enumeratedValue>
<name>COMPARE_AT_INCREMENT</name>
<description>Compare when counter is incrementing</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COMPARE_AT_DECREMENT</name>
<description>Compare when counter is decrementing</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CMPVUPD</name>
<description>PWM Comparison 0 Value Update Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CVUPD</name>
<description>Comparison x Value Update</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>CVMUPD</name>
<description>Comparison x Value Mode Update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMPM</name>
<description>PWM Comparison 0 Mode Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>CEN</name>
<description>Comparison x Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR</name>
<description>Comparison x Trigger</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CPR</name>
<description>Comparison x Period</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CPRCNT</name>
<description>Comparison x Period Counter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CUPR</name>
<description>Comparison x Update Period</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CUPRCNT</name>
<description>Comparison x Update Period Counter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMPMUPD</name>
<description>PWM Comparison 0 Mode Update Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CENUPD</name>
<description>Comparison x Enable Update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRUPD</name>
<description>Comparison x Trigger Update</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CPRUPD</name>
<description>Comparison x Period Update</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CUPRUPD</name>
<description>Comparison x Update Period Update</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</cluster>
<cluster>
<dim>4</dim>
<dimIncrement>32</dimIncrement>
<name>PWM_CH_NUM[%s]</name>
<description>PWM Channel Mode Register</description>
<addressOffset>0x200</addressOffset>
<register>
<name>CMR</name>
<description>PWM Channel Mode Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>CPRE</name>
<description>Channel Pre-scaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>CPRESelect</name>
<enumeratedValue>
<name>MCK</name>
<description>Peripheral clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_2</name>
<description>Peripheral clock/2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_4</name>
<description>Peripheral clock/4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_8</name>
<description>Peripheral clock/8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_16</name>
<description>Peripheral clock/16</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_32</name>
<description>Peripheral clock/32</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_64</name>
<description>Peripheral clock/64</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_128</name>
<description>Peripheral clock/128</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_256</name>
<description>Peripheral clock/256</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_512</name>
<description>Peripheral clock/512</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>MCK_DIV_1024</name>
<description>Peripheral clock/1024</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKA</name>
<description>Clock A</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKB</name>
<description>Clock B</description>
<value>0xC</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALG</name>
<description>Channel Alignment</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CALGSelect</name>
<enumeratedValue>
<name>LEFT_ALIGNED</name>
<description>Left aligned</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED</name>
<description>Center aligned</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Channel Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CPOLSelect</name>
<enumeratedValue>
<name>LOW_POLARITY</name>
<description>Waveform starts at low level</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_POLARITY</name>
<description>Waveform starts at high level</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CES</name>
<description>Counter Event Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CESSelect</name>
<enumeratedValue>
<name>SINGLE_EVENT</name>
<description>At the end of PWM period</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DOUBLE_EVENT</name>
<description>At half of PWM period AND at the end of PWM period</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UPDS</name>
<description>Update Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UPDSSelect</name>
<enumeratedValue>
<name>UPDATE_AT_PERIOD</name>
<description>At the next end of PWM period</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_AT_HALF_PERIOD</name>
<description>At the next end of Half PWM period</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPOLI</name>
<description>Disabled Polarity Inverted</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCTS</name>
<description>Timer Counter Trigger Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTE</name>
<description>Dead-Time Generator Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTHI</name>
<description>Dead-Time PWMHx Output Inverted</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTLI</name>
<description>Dead-Time PWMLx Output Inverted</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PPM</name>
<description>Push-Pull Mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDTY</name>
<description>PWM Channel Duty Cycle Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>CDTY</name>
<description>Channel Duty-Cycle</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDTYUPD</name>
<description>PWM Channel Duty Cycle Update Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CDTYUPD</name>
<description>Channel Duty-Cycle Update</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPRD</name>
<description>PWM Channel Period Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CPRD</name>
<description>Channel Period</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPRDUPD</name>
<description>PWM Channel Period Update Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CPRDUPD</name>
<description>Channel Period Update</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCNT</name>
<description>PWM Channel Counter Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CNT</name>
<description>Channel Counter Register</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT</name>
<description>PWM Channel Dead Time Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>DTH</name>
<description>Dead-Time Value for PWMHx Output</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DTL</name>
<description>Dead-Time Value for PWMLx Output</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTUPD</name>
<description>PWM Channel Dead Time Update Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DTHUPD</name>
<description>Dead-Time Value Update for PWMHx Output</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DTLUPD</name>
<description>Dead-Time Value Update for PWMLx Output</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>CMUPD0</name>
<description>PWM Channel Mode Update Register (ch_num = 0)</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CPOLUP</name>
<description>Channel Polarity Update</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOLINVUP</name>
<description>Channel Polarity Inversion Update</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMUPD1</name>
<description>PWM Channel Mode Update Register (ch_num = 1)</description>
<addressOffset>0x420</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CPOLUP</name>
<description>Channel Polarity Update</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOLINVUP</name>
<description>Channel Polarity Inversion Update</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ETRG1</name>
<description>PWM External Trigger Register (trg_num = 1)</description>
<addressOffset>0x42C</addressOffset>
<size>32</size>
<fields>
<field>
<name>MAXCNT</name>
<description>Maximum Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>TRGMODE</name>
<description>External Trigger Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TRGMODESelect</name>
<enumeratedValue>
<name>OFF</name>
<description>External trigger is not enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>External PWM Reset Mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>External PWM Start Mode</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Cycle-by-cycle Duty Mode</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGEDGE</name>
<description>Edge Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRGEDGESelect</name>
<enumeratedValue>
<name>FALLING_ZERO</name>
<description>TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_ONE</name>
<description>TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGFILT</name>
<description>Filtered input</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGSRC</name>
<description>Trigger Source</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFEN</name>
<description>Recoverable Fault Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LEBR1</name>
<description>PWM Leading-Edge Blanking Register (trg_num = 1)</description>
<addressOffset>0x430</addressOffset>
<size>32</size>
<fields>
<field>
<name>LEBDELAY</name>
<description>Leading-Edge Blanking Delay for TRGINx</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PWMLFEN</name>
<description>PWML Falling Edge Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMLREN</name>
<description>PWML Rising Edge Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMHFEN</name>
<description>PWMH Falling Edge Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMHREN</name>
<description>PWMH Rising Edge Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMUPD2</name>
<description>PWM Channel Mode Update Register (ch_num = 2)</description>
<addressOffset>0x440</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CPOLUP</name>
<description>Channel Polarity Update</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOLINVUP</name>
<description>Channel Polarity Inversion Update</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ETRG2</name>
<description>PWM External Trigger Register (trg_num = 2)</description>
<addressOffset>0x44C</addressOffset>
<size>32</size>
<fields>
<field>
<name>MAXCNT</name>
<description>Maximum Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>TRGMODE</name>
<description>External Trigger Mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TRGMODESelect</name>
<enumeratedValue>
<name>OFF</name>
<description>External trigger is not enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>External PWM Reset Mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>External PWM Start Mode</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Cycle-by-cycle Duty Mode</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGEDGE</name>
<description>Edge Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TRGEDGESelect</name>
<enumeratedValue>
<name>FALLING_ZERO</name>
<description>TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_ONE</name>
<description>TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGFILT</name>
<description>Filtered input</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGSRC</name>
<description>Trigger Source</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFEN</name>
<description>Recoverable Fault Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LEBR2</name>
<description>PWM Leading-Edge Blanking Register (trg_num = 2)</description>
<addressOffset>0x450</addressOffset>
<size>32</size>
<fields>
<field>
<name>LEBDELAY</name>
<description>Leading-Edge Blanking Delay for TRGINx</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PWMLFEN</name>
<description>PWML Falling Edge Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMLREN</name>
<description>PWML Rising Edge Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMHFEN</name>
<description>PWMH Falling Edge Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWMHREN</name>
<description>PWMH Rising Edge Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMUPD3</name>
<description>PWM Channel Mode Update Register (ch_num = 3)</description>
<addressOffset>0x460</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CPOLUP</name>
<description>Channel Polarity Update</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOLINVUP</name>
<description>Channel Polarity Inversion Update</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM1</name>
<baseAddress>0x4005C000</baseAddress>
<interrupt>
<name>PWM1</name>
<value>60</value>
</interrupt>
</peripheral>
<peripheral>
<name>QSPI</name>
<version>11171J</version>
<description>Quad Serial Peripheral Interface</description>
<groupName>QSPI</groupName>
<prependToName>QSPI_</prependToName>
<baseAddress>0x4007C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>QSPI</name>
<value>43</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>QSPIEN</name>
<description>QSPI Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QSPIDIS</name>
<description>QSPI Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>QSPI Software Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LASTXFER</name>
<description>Last Transfer</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>SMM</name>
<description>Serial Memory Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMMSelect</name>
<enumeratedValue>
<name>SPI</name>
<description>The QSPI is in SPI mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MEMORY</name>
<description>The QSPI is in Serial Memory mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LLB</name>
<description>Local Loopback Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LLBSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Local loopback path disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Local loopback path enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRBT</name>
<description>Wait Data Read Before Transfer</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WDRBTSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSMODE</name>
<description>Chip Select Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CSMODESelect</name>
<enumeratedValue>
<name>NOT_RELOADED</name>
<description>The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LASTXFER</name>
<description>The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEMATICALLY</name>
<description>The chip select is deasserted systematically after each transfer.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBBITS</name>
<description>Number Of Bits Per Transfer</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>NBBITSSelect</name>
<enumeratedValue>
<name>_8_BIT</name>
<description>8 bits for transfer</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BIT</name>
<description>16 bits for transfer</description>
<value>0x8</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLYBCT</name>
<description>Delay Between Consecutive Transfers</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DLYCS</name>
<description>Minimum Inactive QCS Delay</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<description>Receive Data Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RD</name>
<description>Receive Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<description>Transmit Data Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TD</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full (cleared by reading SPI_RDR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty (cleared by writing SPI_TDR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty (cleared by writing SPI_TDR)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Status (cleared on read)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Chip Select Rise (cleared on read)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chip Select Status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INSTRE</name>
<description>Instruction End Status (cleared on read)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QSPIENS</name>
<description>QSPI Enable Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Chip Select Rise Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chip Select Status Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INSTRE</name>
<description>Instruction End Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Chip Select Rise Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chip Select Status Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INSTRE</name>
<description>Instruction End Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Chip Select Rise Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chip Select Status Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INSTRE</name>
<description>Instruction End Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>Serial Clock Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<fields>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCBR</name>
<description>Serial Clock Baud Rate</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DLYBS</name>
<description>Delay Before QSCK</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IAR</name>
<description>Instruction Address Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDR</name>
<description>Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>Instruction Code Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<fields>
<field>
<name>INST</name>
<description>Instruction Code</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>OPT</name>
<description>Option Code</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFR</name>
<description>Instruction Frame Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<fields>
<field>
<name>WIDTH</name>
<description>Width of Instruction Code, Address, Option Code and Data</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>WIDTHSelect</name>
<enumeratedValue>
<name>SINGLE_BIT_SPI</name>
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_OUTPUT</name>
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>QUAD_OUTPUT</name>
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_IO</name>
<description>Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>QUAD_IO</name>
<description>Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_CMD</name>
<description>Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>QUAD_CMD</name>
<description>Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INSTEN</name>
<description>Instruction Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDREN</name>
<description>Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTEN</name>
<description>Option Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAEN</name>
<description>Data Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTL</name>
<description>Option Code Length</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>OPTLSelect</name>
<enumeratedValue>
<name>OPTION_1BIT</name>
<description>The option code is 1 bit long.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPTION_2BIT</name>
<description>The option code is 2 bits long.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OPTION_4BIT</name>
<description>The option code is 4 bits long.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>OPTION_8BIT</name>
<description>The option code is 8 bits long.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADDRL</name>
<description>Address Length</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ADDRLSelect</name>
<enumeratedValue>
<name>_24_BIT</name>
<description>The address is 24 bits long.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BIT</name>
<description>The address is 32 bits long.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFRTYP</name>
<description>Data Transfer Type</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TFRTYPSelect</name>
<enumeratedValue>
<name>TRSFR_READ</name>
<description>Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRSFR_READ_MEMORY</name>
<description>Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRSFR_WRITE</name>
<description>Write transfer into the serial memory.Scrambling is not performed.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRSFR_WRITE_MEMORY</name>
<description>Write data transfer into the serial memory.If enabled, scrambling is performed.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRM</name>
<description>Continuous Read Mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CRMSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The Continuous Read mode is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The Continuous Read mode is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBDUM</name>
<description>Number Of Dummy Cycles</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMR</name>
<description>Scrambling Mode Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<fields>
<field>
<name>SCREN</name>
<description>Scrambling/Unscrambling Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SCRENSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The scrambling/unscrambling is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The scrambling/unscrambling is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RVDIS</name>
<description>Scrambling/Unscrambling Random Value Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SKR</name>
<description>Scrambling Key Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>USRK</name>
<description>User Scrambling Key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
<value>0x515350</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RSTC</name>
<version>11009N</version>
<description>Reset Controller</description>
<groupName>RSTC</groupName>
<prependToName>RSTC_</prependToName>
<baseAddress>0x400E1800</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RSTC</name>
<value>1</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>PROCRST</name>
<description>Processor Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTRST</name>
<description>External Reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KEY</name>
<description>System Reset Key</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0xA5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>URSTS</name>
<description>User Reset Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTTYP</name>
<description>Reset Type</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>RSTTYPSelect</name>
<enumeratedValue>
<name>GENERAL_RST</name>
<description>First power-up reset</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BACKUP_RST</name>
<description>Return from Backup Mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WDT_RST</name>
<description>Watchdog fault occurred</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SOFT_RST</name>
<description>Processor reset required by the software</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_RST</name>
<description>NRST pin detected low</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NRSTL</name>
<description>NRST Pin Level</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRCMP</name>
<description>Software Reset Command in Progress</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>URSTEN</name>
<description>User Reset Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URSTIEN</name>
<description>User Reset Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERSTL</name>
<description>External Reset Length</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Write Access Password</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
<value>0xA5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RSWDT</name>
<version>11110G</version>
<description>Reinforced Safety Watchdog Timer</description>
<groupName>RSWDT</groupName>
<prependToName>RSWDT_</prependToName>
<baseAddress>0x400E1900</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RSWDT</name>
<value>63</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>WDRSTT</name>
<description>Watchdog Restart</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Password</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0xC4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>WDV</name>
<description>Watchdog Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WDFIEN</name>
<description>Watchdog Fault Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDRSTEN</name>
<description>Watchdog Reset Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDDIS</name>
<description>Watchdog Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALLONES</name>
<description>Must Always Be Written with 0xFFF</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WDDBGHLT</name>
<description>Watchdog Debug Halt</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIDLEHLT</name>
<description>Watchdog Idle Halt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WDUNF</name>
<description>Watchdog Underflow</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<version>6056ZB</version>
<description>Real-time Clock</description>
<groupName>RTC</groupName>
<prependToName>RTC_</prependToName>
<baseAddress>0x400E1860</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x30</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC</name>
<value>2</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>UPDTIM</name>
<description>Update Request Time Register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDCAL</name>
<description>Update Request Calendar Register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVSEL</name>
<description>Time Event Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TIMEVSELSelect</name>
<enumeratedValue>
<name>MINUTE</name>
<description>Minute change</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HOUR</name>
<description>Hour change</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MIDNIGHT</name>
<description>Every day at midnight</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NOON</name>
<description>Every day at noon</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALEVSEL</name>
<description>Calendar Event Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CALEVSELSelect</name>
<enumeratedValue>
<name>WEEK</name>
<description>Week change (every Monday at time 00:00:00)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MONTH</name>
<description>Month change (every 01 of each month at time 00:00:00)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>YEAR</name>
<description>Year change (every January 1 at time 00:00:00)</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>HRMOD</name>
<description>12-/24-hour Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERSIAN</name>
<description>PERSIAN Calendar</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NEGPPM</name>
<description>NEGative PPM Correction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CORRECTION</name>
<description>Slow Clock Correction</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HIGHPPM</name>
<description>HIGH PPM Correction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT0</name>
<description>RTCOUT0 OutputSource Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>OUT0Select</name>
<enumeratedValue>
<name>NO_WAVE</name>
<description>No waveform, stuck at '0'</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ1HZ</name>
<description>1 Hz square wave</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ32HZ</name>
<description>32 Hz square wave</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ64HZ</name>
<description>64 Hz square wave</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ512HZ</name>
<description>512 Hz square wave</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ALARM_TOGGLE</name>
<description>Output toggles when alarm flag rises</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>ALARM_FLAG</name>
<description>Output is a copy of the alarm flag</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>PROG_PULSE</name>
<description>Duty cycle programmable pulse</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUT1</name>
<description>RTCOUT1 Output Source Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>OUT1Select</name>
<enumeratedValue>
<name>NO_WAVE</name>
<description>No waveform, stuck at '0'</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ1HZ</name>
<description>1 Hz square wave</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ32HZ</name>
<description>32 Hz square wave</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ64HZ</name>
<description>64 Hz square wave</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FREQ512HZ</name>
<description>512 Hz square wave</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ALARM_TOGGLE</name>
<description>Output toggles when alarm flag rises</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>ALARM_FLAG</name>
<description>Output is a copy of the alarm flag</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>PROG_PULSE</name>
<description>Duty cycle programmable pulse</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THIGH</name>
<description>High Duration of the Output Pulse</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>THIGHSelect</name>
<enumeratedValue>
<name>H_31MS</name>
<description>31.2 ms</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>H_16MS</name>
<description>15.6 ms</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>H_4MS</name>
<description>3.91 ms</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>H_976US</name>
<description>976 us</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>H_488US</name>
<description>488 us</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>H_122US</name>
<description>122 us</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>H_30US</name>
<description>30.5 us</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>H_15US</name>
<description>15.2 us</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPERIOD</name>
<description>Period of the Output Pulse</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TPERIODSelect</name>
<enumeratedValue>
<name>P_1S</name>
<description>1 second</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>P_500MS</name>
<description>500 ms</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>P_250MS</name>
<description>250 ms</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>P_125MS</name>
<description>125 ms</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMR</name>
<description>Time Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>SEC</name>
<description>Current Second</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>MIN</name>
<description>Current Minute</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HOUR</name>
<description>Current Hour</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>AMPM</name>
<description>Ante Meridiem Post Meridiem Indicator</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALR</name>
<description>Calendar Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CENT</name>
<description>Current Century</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>Current Year</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MONTH</name>
<description>Current Month</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DAY</name>
<description>Current Day in Current Week</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DATE</name>
<description>Current Day in Current Month</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMALR</name>
<description>Time Alarm Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>SEC</name>
<description>Second Alarm</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SECEN</name>
<description>Second Alarm Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MIN</name>
<description>Minute Alarm</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>MINEN</name>
<description>Minute Alarm Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOUR</name>
<description>Hour Alarm</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>AMPM</name>
<description>AM/PM Indicator</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOUREN</name>
<description>Hour Alarm Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALALR</name>
<description>Calendar Alarm Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>MONTH</name>
<description>Month Alarm</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>MTHEN</name>
<description>Month Alarm Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATE</name>
<description>Date Alarm</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>DATEEN</name>
<description>Date Alarm Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ACKUPD</name>
<description>Acknowledge for Update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ACKUPDSelect</name>
<enumeratedValue>
<name>FREERUN</name>
<description>Time and calendar registers cannot be updated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE</name>
<description>Time and calendar registers can be updated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARM</name>
<description>Alarm Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ALARMSelect</name>
<enumeratedValue>
<name>NO_ALARMEVENT</name>
<description>No alarm matching condition occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ALARMEVENT</name>
<description>An alarm matching condition has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEC</name>
<description>Second Event</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SECSelect</name>
<enumeratedValue>
<name>NO_SECEVENT</name>
<description>No second event has occurred since the last clear.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SECEVENT</name>
<description>At least one second event has occurred since the last clear.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMEV</name>
<description>Time Event</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TIMEVSelect</name>
<enumeratedValue>
<name>NO_TIMEVENT</name>
<description>No time event has occurred since the last clear.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMEVENT</name>
<description>At least one time event has occurred since the last clear.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALEV</name>
<description>Calendar Event</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CALEVSelect</name>
<enumeratedValue>
<name>NO_CALEVENT</name>
<description>No calendar event has occurred since the last clear.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CALEVENT</name>
<description>At least one calendar event has occurred since the last clear.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDERR</name>
<description>Time and/or Date Free Running Error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TDERRSelect</name>
<enumeratedValue>
<name>CORRECT</name>
<description>The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ERR_TIMEDATE</name>
<description>The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCCR</name>
<description>Status Clear Command Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ACKCLR</name>
<description>Acknowledge Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRCLR</name>
<description>Alarm Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECCLR</name>
<description>Second Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCLR</name>
<description>Time Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALCLR</name>
<description>Calendar Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDERRCLR</name>
<description>Time and/or Date Free Running Error Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ACKEN</name>
<description>Acknowledge Update Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALREN</name>
<description>Alarm Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECEN</name>
<description>Second Event Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEN</name>
<description>Time Event Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALEN</name>
<description>Calendar Event Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDERREN</name>
<description>Time and/or Date Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ACKDIS</name>
<description>Acknowledge Update Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRDIS</name>
<description>Alarm Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECDIS</name>
<description>Second Event Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDIS</name>
<description>Time Event Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALDIS</name>
<description>Calendar Event Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDERRDIS</name>
<description>Time and/or Date Error Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ACK</name>
<description>Acknowledge Update Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALR</name>
<description>Alarm Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEC</name>
<description>Second Event Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM</name>
<description>Time Event Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL</name>
<description>Calendar Event Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDERR</name>
<description>Time and/or Date Error Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VER</name>
<description>Valid Entry Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NVTIM</name>
<description>Non-valid Time</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NVCAL</name>
<description>Non-valid Calendar</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NVTIMALR</name>
<description>Non-valid Time Alarm</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NVCALALR</name>
<description>Non-valid Calendar Alarm</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTT</name>
<version>6081M</version>
<description>Real-time Timer</description>
<groupName>RTT</groupName>
<prependToName>RTT_</prependToName>
<baseAddress>0x400E1830</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTT</name>
<value>3</value>
</interrupt>
<registers>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>RTPRES</name>
<description>Real-time Timer Prescaler Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ALMIEN</name>
<description>Alarm Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTTINCIEN</name>
<description>Real-time Timer Increment Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTTRST</name>
<description>Real-time Timer Restart</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTTDIS</name>
<description>Real-time Timer Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC1HZ</name>
<description>Real-Time Clock 1Hz Clock Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AR</name>
<description>Alarm Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>ALMV</name>
<description>Alarm Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>VR</name>
<description>Value Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CRTV</name>
<description>Current Real-time Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ALMS</name>
<description>Real-time Alarm Status (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTTINC</name>
<description>Prescaler Roll-over Status (cleared on read)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<version>6088ZM</version>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI_</prependToName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SPIEN</name>
<description>SPI Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPIDIS</name>
<description>SPI Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>SPI Software Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REQCLR</name>
<description>Request to Clear the Comparison Trigger</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LASTXFER</name>
<description>Last Transfer</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>MSTR</name>
<description>Master/Slave Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MSTRSelect</name>
<enumeratedValue>
<name>MASTER</name>
<description>Master</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PS</name>
<description>Peripheral Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCSDEC</name>
<description>Chip Select Decode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODFDIS</name>
<description>Mode Fault Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDRBT</name>
<description>Wait Data Read Before Transfer</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LLB</name>
<description>Local Loopback Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCS</name>
<description>Peripheral Chip Select</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>PCSSelect</name>
<enumeratedValue>
<name>NPCS0</name>
<description>NPCS0 as Chip Select</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS1</name>
<description>NPCS1 as Chip Select</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS2</name>
<description>NPCS2 as Chip Select</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS3</name>
<description>NPCS3 as Chip Select</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLYBCS</name>
<description>Delay Between Chip Selects</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<description>Receive Data Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RD</name>
<description>Receive Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PCS</name>
<description>Peripheral Chip Select</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<description>Transmit Data Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TD</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PCS</name>
<description>Peripheral Chip Select</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>PCSSelect</name>
<enumeratedValue>
<name>NPCS0</name>
<description>NPCS0 as Chip Select</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS1</name>
<description>NPCS1 as Chip Select</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS2</name>
<description>NPCS2 as Chip Select</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>NPCS3</name>
<description>NPCS3 as Chip Select</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LASTXFER</name>
<description>Last Transfer</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full (cleared by reading SPI_RDR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty (cleared by writing SPI_TDR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODF</name>
<description>Mode Fault Error (cleared on read)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Status (cleared on read)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSR</name>
<description>NSS Rising (cleared on read)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty (cleared by writing SPI_TDR)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDES</name>
<description>Underrun Error Status (Slave mode only) (cleared on read)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPIENS</name>
<description>SPI Enable Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>SPI Transmit Data Register Empty Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODF</name>
<description>Mode Fault Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSR</name>
<description>NSS Rising Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDES</name>
<description>Underrun Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>SPI Transmit Data Register Empty Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODF</name>
<description>Mode Fault Error Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSR</name>
<description>NSS Rising Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDES</name>
<description>Underrun Error Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRE</name>
<description>SPI Transmit Data Register Empty Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODF</name>
<description>Mode Fault Error Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRES</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSR</name>
<description>NSS Rising Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmission Registers Empty Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDES</name>
<description>Underrun Error Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>CSR[%s]</name>
<description>Chip Select Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CPOLSelect</name>
<enumeratedValue>
<name>IDLE_LOW</name>
<description>Clock is low when inactive (CPOL=0)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDLE_HIGH</name>
<description>Clock is high when inactive (CPOL=1)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NCPHA</name>
<description>Clock Phase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NCPHASelect</name>
<enumeratedValue>
<name>VALID_LEADING_EDGE</name>
<description>Data is valid on clock leading edge (NCPHA=1)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>VALID_TRAILING_EDGE</name>
<description>Data is valid on clock trailing edge (NCPHA=0)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSNAAT</name>
<description>Chip Select Not Active After Transfer (Ignored if CSAAT = 1)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSAAT</name>
<description>Chip Select Active After Transfer</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BITS</name>
<description>Bits Per Transfer</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>BITSSelect</name>
<enumeratedValue>
<name>_8_BIT</name>
<description>8 bits for transfer</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_9_BIT</name>
<description>9 bits for transfer</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_10_BIT</name>
<description>10 bits for transfer</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_11_BIT</name>
<description>11 bits for transfer</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_12_BIT</name>
<description>12 bits for transfer</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_13_BIT</name>
<description>13 bits for transfer</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_14_BIT</name>
<description>14 bits for transfer</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_15_BIT</name>
<description>15 bits for transfer</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BIT</name>
<description>16 bits for transfer</description>
<value>0x8</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCBR</name>
<description>Serial Clock Bit Rate</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DLYBS</name>
<description>Delay Before SPCK</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DLYBCT</name>
<description>Delay Between Consecutive Transfers</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x535049</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SSC</name>
<version>6078Q</version>
<description>Synchronous Serial Controller</description>
<groupName>SSC</groupName>
<prependToName>SSC_</prependToName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SSC</name>
<value>22</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXEN</name>
<description>Receive Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receive Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmit Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmit Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMR</name>
<description>Clock Mode Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<fields>
<field>
<name>DIV</name>
<description>Clock Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCMR</name>
<description>Receive Clock Mode Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>CKS</name>
<description>Receive Clock Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CKSSelect</name>
<enumeratedValue>
<name>MCK</name>
<description>Divided Clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TK</name>
<description>TK Clock signal</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RK</name>
<description>RK pin</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKO</name>
<description>Receive Clock Output Mode Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CKOSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None, RK pin is an input</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>Continuous Receive Clock, RK pin is an output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER</name>
<description>Receive Clock only during data transfers, RK pin is an output</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKI</name>
<description>Receive Clock Inversion</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKG</name>
<description>Receive Clock Gating Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CKGSelect</name>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN_RF_LOW</name>
<description>Receive Clock enabled only if RF Low</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EN_RF_HIGH</name>
<description>Receive Clock enabled only if RF High</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Receive Start Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>STARTSelect</name>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT</name>
<description>Transmit start</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_LOW</name>
<description>Detection of a low level on RF signal</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_HIGH</name>
<description>Detection of a high level on RF signal</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_FALLING</name>
<description>Detection of a falling edge on RF signal</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_RISING</name>
<description>Detection of a rising edge on RF signal</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_LEVEL</name>
<description>Detection of any level change on RF signal</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>RF_EDGE</name>
<description>Detection of any edge on RF signal</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>CMP_0</name>
<description>Compare 0</description>
<value>0x8</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOP</name>
<description>Receive Stop Selection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STTDLY</name>
<description>Receive Start Delay</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PERIOD</name>
<description>Receive Period Divider Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RFMR</name>
<description>Receive Frame Mode Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATLEN</name>
<description>Data Length</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>LOOP</name>
<description>Loop Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATNB</name>
<description>Data Number per Frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FSLEN</name>
<description>Receive Frame Sync Length</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FSOS</name>
<description>Receive Frame Sync Output Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>FSOSSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None, RF pin is an input</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEGATIVE</name>
<description>Negative Pulse, RF pin is an output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE</name>
<description>Positive Pulse, RF pin is an output</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW</name>
<description>Driven Low during data transfer, RF pin is an output</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Driven High during data transfer, RF pin is an output</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLING</name>
<description>Toggling at each start of data transfer, RF pin is an output</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSEDGE</name>
<description>Frame Sync Edge Detection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FSEDGESelect</name>
<enumeratedValue>
<name>POSITIVE</name>
<description>Positive Edge Detection</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEGATIVE</name>
<description>Negative Edge Detection</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLEN_EXT</name>
<description>FSLEN Field Extension</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TCMR</name>
<description>Transmit Clock Mode Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>CKS</name>
<description>Transmit Clock Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CKSSelect</name>
<enumeratedValue>
<name>MCK</name>
<description>Divided Clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RK</name>
<description>RK Clock signal</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TK</name>
<description>TK pin</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKO</name>
<description>Transmit Clock Output Mode Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CKOSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None, TK pin is an input</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>Continuous Transmit Clock, TK pin is an output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER</name>
<description>Transmit Clock only during data transfers, TK pin is an output</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKI</name>
<description>Transmit Clock Inversion</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKG</name>
<description>Transmit Clock Gating Selection</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CKGSelect</name>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN_TF_LOW</name>
<description>Transmit Clock enabled only if TF Low</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EN_TF_HIGH</name>
<description>Transmit Clock enabled only if TF High</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Transmit Start Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>STARTSelect</name>
<enumeratedValue>
<name>CONTINUOUS</name>
<description>Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVE</name>
<description>Receive start</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_LOW</name>
<description>Detection of a low level on TF signal</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_HIGH</name>
<description>Detection of a high level on TF signal</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_FALLING</name>
<description>Detection of a falling edge on TF signal</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_RISING</name>
<description>Detection of a rising edge on TF signal</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_LEVEL</name>
<description>Detection of any level change on TF signal</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>TF_EDGE</name>
<description>Detection of any edge on TF signal</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STTDLY</name>
<description>Transmit Start Delay</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PERIOD</name>
<description>Transmit Period Divider Selection</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TFMR</name>
<description>Transmit Frame Mode Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATLEN</name>
<description>Data Length</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DATDEF</name>
<description>Data Default Value</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATNB</name>
<description>Data Number per Frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FSLEN</name>
<description>Transmit Frame Sync Length</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FSOS</name>
<description>Transmit Frame Sync Output Selection</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>FSOSSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None, TF pin is an input</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEGATIVE</name>
<description>Negative Pulse, TF pin is an output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE</name>
<description>Positive Pulse, TF pin is an output</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW</name>
<description>Driven Low during data transfer</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Driven High during data transfer</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLING</name>
<description>Toggling at each start of data transfer</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSDEN</name>
<description>Frame Sync Data Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSEDGE</name>
<description>Frame Sync Edge Detection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FSEDGESelect</name>
<enumeratedValue>
<name>POSITIVE</name>
<description>Positive Edge Detection</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEGATIVE</name>
<description>Negative Edge Detection</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLEN_EXT</name>
<description>FSLEN Field Extension</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>RHR</name>
<description>Receive Holding Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDAT</name>
<description>Receive Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmit Holding Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TDAT</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSHR</name>
<description>Receive Sync. Holding Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RSDAT</name>
<description>Receive Synchronization Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSHR</name>
<description>Transmit Sync. Holding Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<fields>
<field>
<name>TSDAT</name>
<description>Transmit Synchronization Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RC0R</name>
<description>Receive Compare 0 Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<fields>
<field>
<name>CP0</name>
<description>Receive Compare Data 0</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RC1R</name>
<description>Receive Compare 1 Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CP1</name>
<description>Receive Compare Data 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXRDY</name>
<description>Transmit Ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit Empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUN</name>
<description>Receive Overrun</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP0</name>
<description>Compare 0</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP1</name>
<description>Compare 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSYN</name>
<description>Transmit Sync</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSYN</name>
<description>Receive Sync</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmit Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receive Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit Empty Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Ready Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUN</name>
<description>Receive Overrun Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP0</name>
<description>Compare 0 Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP1</name>
<description>Compare 1 Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSYN</name>
<description>Tx Sync Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSYN</name>
<description>Rx Sync Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit Empty Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Ready Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUN</name>
<description>Receive Overrun Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP0</name>
<description>Compare 0 Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP1</name>
<description>Compare 1 Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSYN</name>
<description>Tx Sync Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSYN</name>
<description>Rx Sync Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXRDY</name>
<description>Transmit Ready Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit Empty Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Ready Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUN</name>
<description>Receive Overrun Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP0</name>
<description>Compare 0 Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CP1</name>
<description>Compare 1 Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSYN</name>
<description>Tx Sync Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSYN</name>
<description>Rx Sync Interrupt Mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x535343</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protect Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SUPC</name>
<version>6452ZE</version>
<description>Supply Controller</description>
<groupName>SUPC</groupName>
<prependToName>SUPC_</prependToName>
<baseAddress>0x400E1810</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xD8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SUPC</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Supply Controller Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>VROFF</name>
<description>Voltage Regulator Off</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>VROFFSelect</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP_VREG</name>
<description>If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XTALSEL</name>
<description>Crystal Oscillator Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>XTALSELSelect</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRYSTAL_SEL</name>
<description>If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEY</name>
<description>Password</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0xA5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMMR</name>
<description>Supply Controller Supply Monitor Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>SMTH</name>
<description>Supply Monitor Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SMSMPL</name>
<description>Supply Monitor Sampling Period</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>SMSMPLSelect</name>
<enumeratedValue>
<name>SMD</name>
<description>Supply Monitor disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CSM</name>
<description>Continuous Supply Monitor</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_32SLCK</name>
<description>Supply Monitor enabled one SLCK period every 32 SLCK periods</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_256SLCK</name>
<description>Supply Monitor enabled one SLCK period every 256 SLCK periods</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_2048SLCK</name>
<description>Supply Monitor enabled one SLCK period every 2,048 SLCK periods</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMRSTEN</name>
<description>Supply Monitor Reset Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMRSTENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMIEN</name>
<description>Supply Monitor Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMIENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The SUPC interrupt signal is not affected when a supply monitor detection occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The SUPC interrupt signal is asserted when a supply monitor detection occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Supply Controller Mode Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>BODRSTEN</name>
<description>Brownout Detector Reset Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BODRSTENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The core reset signal vddcore_nreset is not affected when a brownout detection occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODDIS</name>
<description>Brownout Detector Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BODDISSelect</name>
<enumeratedValue>
<name>ENABLE</name>
<description>The core brownout detector is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLE</name>
<description>The core brownout detector is disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONREG</name>
<description>Voltage Regulator Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ONREGSelect</name>
<enumeratedValue>
<name>ONREG_UNUSED</name>
<description>Internal voltage regulator is not used (external power supply is used).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONREG_USED</name>
<description>Internal voltage regulator is used.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKUPRETON</name>
<description>SRAM On In Backup Mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSCBYPASS</name>
<description>Oscillator Bypass</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>OSCBYPASSSelect</name>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS</name>
<description>The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEY</name>
<description>Password Key</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0xA5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WUMR</name>
<description>Supply Controller Wake-up Mode Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>SMEN</name>
<description>Supply Monitor Wake-up Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The supply monitor detection has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The supply monitor detection forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTTEN</name>
<description>Real-time Timer Wake-up Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RTTENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The RTT alarm signal has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The RTT alarm signal forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCEN</name>
<description>Real-time Clock Wake-up Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RTCENSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The RTC alarm signal has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The RTC alarm signal forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBCEN0</name>
<description>Low-power Debouncer Enable WKUP0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LPDBCEN0Select</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The WKUP0 input pin is not connected to the low-power debouncer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBCEN1</name>
<description>Low-power Debouncer Enable WKUP1</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LPDBCEN1Select</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>The WKUP1 input pin is not connected to the low-power debouncer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBCCLR</name>
<description>Low-power Debouncer Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LPDBCCLRSelect</name>
<enumeratedValue>
<name>NOT_ENABLE</name>
<description>A low-power debounce event does not create an immediate clear on the first half of GPBR registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPDBC</name>
<description>Wake-up Inputs Debouncer Period</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>WKUPDBCSelect</name>
<enumeratedValue>
<name>IMMEDIATE</name>
<description>Immediate, no debouncing, detected active at least on one Slow Clock edge.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_SLCK</name>
<description>WKUPx shall be in its active state for at least 3 SLCK periods</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_SLCK</name>
<description>WKUPx shall be in its active state for at least 32 SLCK periods</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_512_SLCK</name>
<description>WKUPx shall be in its active state for at least 512 SLCK periods</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_4096_SLCK</name>
<description>WKUPx shall be in its active state for at least 4,096 SLCK periods</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_32768_SLCK</name>
<description>WKUPx shall be in its active state for at least 32,768 SLCK periods</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBC</name>
<description>Low-power Debouncer Period</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>LPDBCSelect</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable the low-power debouncers.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_RTCOUT</name>
<description>WKUP0/1 in active state for at least 2 RTCOUTx clock periods</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_RTCOUT</name>
<description>WKUP0/1 in active state for at least 3 RTCOUTx clock periods</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_4_RTCOUT</name>
<description>WKUP0/1 in active state for at least 4 RTCOUTx clock periods</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_5_RTCOUT</name>
<description>WKUP0/1 in active state for at least 5 RTCOUTx clock periods</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_6_RTCOUT</name>
<description>WKUP0/1 in active state for at least 6 RTCOUTx clock periods</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_7_RTCOUT</name>
<description>WKUP0/1 in active state for at least 7 RTCOUTx clock periods</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_RTCOUT</name>
<description>WKUP0/1 in active state for at least 8 RTCOUTx clock periods</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WUIR</name>
<description>Supply Controller Wake-up Inputs Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>WKUPEN0</name>
<description>Wake-up Input Enable 0 to 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN0Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN1</name>
<description>Wake-up Input Enable 0 to 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN1Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN2</name>
<description>Wake-up Input Enable 0 to 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN2Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN3</name>
<description>Wake-up Input Enable 0 to 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN3Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN4</name>
<description>Wake-up Input Enable 0 to 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN4Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN5</name>
<description>Wake-up Input Enable 0 to 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN5Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN6</name>
<description>Wake-up Input Enable 0 to 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN6Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN7</name>
<description>Wake-up Input Enable 0 to 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN7Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN8</name>
<description>Wake-up Input Enable 0 to 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN8Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN9</name>
<description>Wake-up Input Enable 0 to 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN9Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN10</name>
<description>Wake-up Input Enable 0 to 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN10Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN11</name>
<description>Wake-up Input Enable 0 to 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN11Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN12</name>
<description>Wake-up Input Enable 0 to 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN12Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPEN13</name>
<description>Wake-up Input Enable 0 to 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPEN13Select</name>
<enumeratedValue>
<name>DISABLE</name>
<description>The corresponding wake-up input has no wake-up effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>The corresponding wake-up input is enabled for a wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT0</name>
<description>Wake-up Input Type 0 to 0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT0Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT1</name>
<description>Wake-up Input Type 0 to 1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT1Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT2</name>
<description>Wake-up Input Type 0 to 2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT2Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT3</name>
<description>Wake-up Input Type 0 to 3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT3Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT4</name>
<description>Wake-up Input Type 0 to 4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT4Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT5</name>
<description>Wake-up Input Type 0 to 5</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT5Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT6</name>
<description>Wake-up Input Type 0 to 6</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT6Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT7</name>
<description>Wake-up Input Type 0 to 7</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT7Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT8</name>
<description>Wake-up Input Type 0 to 8</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT8Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT9</name>
<description>Wake-up Input Type 0 to 9</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT9Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT10</name>
<description>Wake-up Input Type 0 to 10</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT10Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT11</name>
<description>Wake-up Input Type 0 to 11</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT11Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT12</name>
<description>Wake-up Input Type 0 to 12</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT12Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPT13</name>
<description>Wake-up Input Type 0 to 13</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPT13Select</name>
<enumeratedValue>
<name>LOW</name>
<description>A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Supply Controller Status Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WKUPS</name>
<description>WKUP Wake-up Status (cleared on read)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPSSelect</name>
<enumeratedValue>
<name>NO</name>
<description>No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMWS</name>
<description>Supply Monitor Detection Wake-up Status (cleared on read)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMWSSelect</name>
<enumeratedValue>
<name>NO</name>
<description>No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODRSTS</name>
<description>Brownout Detector Reset Status (cleared on read)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BODRSTSSelect</name>
<enumeratedValue>
<name>NO</name>
<description>No core brownout rising edge event has been detected since the last read of the SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMRSTS</name>
<description>Supply Monitor Reset Status (cleared on read)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMRSTSSelect</name>
<enumeratedValue>
<name>NO</name>
<description>No supply monitor detection has generated a core reset since the last read of the SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMS</name>
<description>Supply Monitor Status (cleared on read)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMSSelect</name>
<enumeratedValue>
<name>NO</name>
<description>No supply monitor detection since the last read of SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one supply monitor detection since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOS</name>
<description>Supply Monitor Output Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SMOSSelect</name>
<enumeratedValue>
<name>HIGH</name>
<description>The supply monitor detected VDDIO higher than its threshold at its last measurement.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW</name>
<description>The supply monitor detected VDDIO lower than its threshold at its last measurement.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCSEL</name>
<description>32-kHz Oscillator Selection Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>OSCSELSelect</name>
<enumeratedValue>
<name>RC</name>
<description>The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRYST</name>
<description>The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBCS0</name>
<description>Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LPDBCS0Select</name>
<enumeratedValue>
<name>NO</name>
<description>No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPDBCS1</name>
<description>Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LPDBCS1Select</name>
<enumeratedValue>
<name>NO</name>
<description>No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PRESENT</name>
<description>At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS0</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS0Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS1</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS1Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS2</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS2Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS3</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS3Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS4</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS4Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS5</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS5Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS6</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS6Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS7</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS7Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS8</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS8Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS9</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS9Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS10</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS10Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS11</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS11Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS12</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS12Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKUPIS13</name>
<description>WKUPx Input Status (cleared on read)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WKUPIS13Select</name>
<enumeratedValue>
<name>DIS</name>
<description>The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EN</name>
<description>The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSC_WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
<value>0x525443</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TC0</name>
<version>6082ZL</version>
<description>Timer Counter</description>
<groupName>TC</groupName>
<prependToName>TC_</prependToName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TC0</name>
<value>23</value>
</interrupt>
<interrupt>
<name>TC1</name>
<value>24</value>
</interrupt>
<interrupt>
<name>TC2</name>
<value>25</value>
</interrupt>
<registers>
<cluster>
<dim>3</dim>
<dimIncrement>64</dimIncrement>
<name>TC_CHANNEL[%s]</name>
<description>Channel Control Register (channel = 0)</description>
<addressOffset>0x0</addressOffset>
<register>
<name>CCR</name>
<description>Channel Control Register (channel = 0)</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>CLKEN</name>
<description>Counter Clock Enable Command</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKDIS</name>
<description>Counter Clock Disable Command</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRG</name>
<description>Software Trigger Command</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMR_CAPTURE_MODE</name>
<description>Channel Mode Register (channel = 0)</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>TCCLKS</name>
<description>Clock Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TCCLKSSelect</name>
<enumeratedValue>
<name>TIMER_CLOCK1</name>
<description>Clock selected: internal PCK6 clock signal (from PMC)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK2</name>
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK3</name>
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK4</name>
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK5</name>
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>XC0</name>
<description>Clock selected: XC0</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>XC1</name>
<description>Clock selected: XC1</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>XC2</name>
<description>Clock selected: XC2</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKI</name>
<description>Clock Invert</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURST</name>
<description>Burst Signal Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BURSTSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>The clock is not gated by an external signal.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>XC0</name>
<description>XC0 is ANDed with the selected clock.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>XC1</name>
<description>XC1 is ANDed with the selected clock.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>XC2</name>
<description>XC2 is ANDed with the selected clock.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDBSTOP</name>
<description>Counter Clock Stopped with RB Loading</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDBDIS</name>
<description>Counter Clock Disable with RB Loading</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRGEDG</name>
<description>External Trigger Edge Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ETRGEDGSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>The clock is not gated by an external signal.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Each edge</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABETRG</name>
<description>TIOAx or TIOBx External Trigger Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCTRG</name>
<description>RC Compare Trigger Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVE</name>
<description>Waveform Mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRA</name>
<description>RA Loading Edge Selection</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>LDRASelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge of TIOAx</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge of TIOAx</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Each edge of TIOAx</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDRB</name>
<description>RB Loading Edge Selection</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>LDRBSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge of TIOAx</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge of TIOAx</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Each edge of TIOAx</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBSMPLR</name>
<description>Loading Edge Subsampling Ratio</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>SBSMPLRSelect</name>
<enumeratedValue>
<name>ONE</name>
<description>Load a Capture Register each selected edge</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>Load a Capture Register every 2 selected edges</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOURTH</name>
<description>Load a Capture Register every 4 selected edges</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>EIGHTH</name>
<description>Load a Capture Register every 8 selected edges</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SIXTEENTH</name>
<description>Load a Capture Register every 16 selected edges</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CMR_WAVEFORM_MODE</name>
<description>Channel Mode Register (channel = 0)</description>
<alternateRegister>CMR_CAPTURE_MODE</alternateRegister>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>TCCLKS</name>
<description>Clock Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>TCCLKSSelect</name>
<enumeratedValue>
<name>TIMER_CLOCK1</name>
<description>Clock selected: internal PCK6 clock signal (from PMC)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK2</name>
<description>Clock selected: internal MCK/8 clock signal (from PMC)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK3</name>
<description>Clock selected: internal MCK/32 clock signal (from PMC)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK4</name>
<description>Clock selected: internal MCK/128 clock signal (from PMC)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLOCK5</name>
<description>Clock selected: internal SLCK clock signal (from PMC)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>XC0</name>
<description>Clock selected: XC0</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>XC1</name>
<description>Clock selected: XC1</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>XC2</name>
<description>Clock selected: XC2</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKI</name>
<description>Clock Invert</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURST</name>
<description>Burst Signal Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BURSTSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>The clock is not gated by an external signal.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>XC0</name>
<description>XC0 is ANDed with the selected clock.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>XC1</name>
<description>XC1 is ANDed with the selected clock.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>XC2</name>
<description>XC2 is ANDed with the selected clock.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCSTOP</name>
<description>Counter Clock Stopped with RC Compare</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCDIS</name>
<description>Counter Clock Disable with RC Loading</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EEVTEDG</name>
<description>External Event Edge Selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>EEVTEDGSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Each edges</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EEVT</name>
<description>External Event Selection</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>EEVTSelect</name>
<enumeratedValue>
<name>TIOB</name>
<description>TIOB</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>XC0</name>
<description>XC0</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>XC1</name>
<description>XC1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>XC2</name>
<description>XC2</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENETRG</name>
<description>External Event Trigger Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVSEL</name>
<description>Waveform Selection</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>WAVSELSelect</name>
<enumeratedValue>
<name>UP</name>
<description>UP mode without automatic trigger on RC Compare</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDOWN</name>
<description>UPDOWN mode without automatic trigger on RC Compare</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_RC</name>
<description>UP mode with automatic trigger on RC Compare</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDOWN_RC</name>
<description>UPDOWN mode with automatic trigger on RC Compare</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAVE</name>
<description>Waveform Mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACPA</name>
<description>RA Compare Effect on TIOAx</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ACPASelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACPC</name>
<description>RC Compare Effect on TIOAx</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ACPCSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AEEVT</name>
<description>External Event Effect on TIOAx</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>AEEVTSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASWTRG</name>
<description>Software Trigger Effect on TIOAx</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ASWTRGSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCPB</name>
<description>RB Compare Effect on TIOBx</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BCPBSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCPC</name>
<description>RC Compare Effect on TIOBx</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BCPCSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BEEVT</name>
<description>External Event Effect on TIOBx</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BEEVTSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSWTRG</name>
<description>Software Trigger Effect on TIOBx</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>BSWTRGSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>NONE</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>SET</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>CLEAR</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>TOGGLE</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMMR</name>
<description>Stepper Motor Mode Register (channel = 0)</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>GCEN</name>
<description>Gray Count Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DOWN</name>
<description>Down Count</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAB</name>
<description>Register AB (channel = 0)</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RAB</name>
<description>Register A or Register B</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CV</name>
<description>Counter Value (channel = 0)</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>CV</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>Register A (channel = 0)</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>RA</name>
<description>Register A</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RB</name>
<description>Register B (channel = 0)</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>RB</name>
<description>Register B</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RC</name>
<description>Register C (channel = 0)</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>RC</name>
<description>Register C</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register (channel = 0)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>COVFS</name>
<description>Counter Overflow Status (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOVRS</name>
<description>Load Overrun Status (cleared on read)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPAS</name>
<description>RA Compare Status (cleared on read)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPBS</name>
<description>RB Compare Status (cleared on read)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCS</name>
<description>RC Compare Status (cleared on read)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRAS</name>
<description>RA Loading Status (cleared on read)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRBS</name>
<description>RB Loading Status (cleared on read)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRGS</name>
<description>External Trigger Status (cleared on read)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSTA</name>
<description>Clock Enabling Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTIOA</name>
<description>TIOAx Mirror</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTIOB</name>
<description>TIOBx Mirror</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register (channel = 0)</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>COVFS</name>
<description>Counter Overflow</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOVRS</name>
<description>Load Overrun</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPAS</name>
<description>RA Compare</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPBS</name>
<description>RB Compare</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCS</name>
<description>RC Compare</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRAS</name>
<description>RA Loading</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRBS</name>
<description>RB Loading</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRGS</name>
<description>External Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register (channel = 0)</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>COVFS</name>
<description>Counter Overflow</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOVRS</name>
<description>Load Overrun</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPAS</name>
<description>RA Compare</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPBS</name>
<description>RB Compare</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCS</name>
<description>RC Compare</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRAS</name>
<description>RA Loading</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRBS</name>
<description>RB Loading</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRGS</name>
<description>External Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register (channel = 0)</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>COVFS</name>
<description>Counter Overflow</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOVRS</name>
<description>Load Overrun</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPAS</name>
<description>RA Compare</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPBS</name>
<description>RB Compare</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPCS</name>
<description>RC Compare</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRAS</name>
<description>RA Loading</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDRBS</name>
<description>RB Loading</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRGS</name>
<description>External Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>Extended Mode Register (channel = 0)</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>TRIGSRCA</name>
<description>Trigger Source for Input A</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TRIGSRCASelect</name>
<enumeratedValue>
<name>EXTERNAL_TIOAx</name>
<description>The trigger/capture input A is driven by external pin TIOAx</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWMx</name>
<description>The trigger/capture input A is driven internally by PWMx</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGSRCB</name>
<description>Trigger Source for Input B</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TRIGSRCBSelect</name>
<enumeratedValue>
<name>EXTERNAL_TIOBx</name>
<description>The trigger/capture input B is driven by external pin TIOBx</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWMx</name>
<description>For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NODIVCLK</name>
<description>No Divided Clock</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>BCR</name>
<description>Block Control Register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SYNC</name>
<description>Synchro Command</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BMR</name>
<description>Block Mode Register</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<fields>
<field>
<name>TC0XC0S</name>
<description>External Clock Signal 0 Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TC0XC0SSelect</name>
<enumeratedValue>
<name>TCLK0</name>
<description>Signal connected to XC0: TCLK0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA1</name>
<description>Signal connected to XC0: TIOA1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA2</name>
<description>Signal connected to XC0: TIOA2</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC1XC1S</name>
<description>External Clock Signal 1 Selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TC1XC1SSelect</name>
<enumeratedValue>
<name>TCLK1</name>
<description>Signal connected to XC1: TCLK1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA0</name>
<description>Signal connected to XC1: TIOA0</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA2</name>
<description>Signal connected to XC1: TIOA2</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC2XC2S</name>
<description>External Clock Signal 2 Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TC2XC2SSelect</name>
<enumeratedValue>
<name>TCLK2</name>
<description>Signal connected to XC2: TCLK2</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA0</name>
<description>Signal connected to XC2: TIOA0</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIOA1</name>
<description>Signal connected to XC2: TIOA1</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QDEN</name>
<description>Quadrature Decoder Enabled</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POSEN</name>
<description>Position Enabled</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPEEDEN</name>
<description>Speed Enabled</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QDTRANS</name>
<description>Quadrature Decoding Transparent</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EDGPHA</name>
<description>Edge on PHA Count Mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVA</name>
<description>Inverted PHA</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVB</name>
<description>Inverted PHB</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVIDX</name>
<description>Inverted Index</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap PHA and PHB</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDXPHB</name>
<description>Index Pin is PHB Pin</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOC</name>
<description>AutoCorrection of missing pulses</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MAXFILT</name>
<description>Maximum Filter</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MAXCMP</name>
<description>Maximum Consecutive Missing Pulses</description>
<bitOffset>26</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>QIER</name>
<description>QDEC Interrupt Enable Register</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>IDX</name>
<description>Index</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRCHG</name>
<description>Direction Change</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QERR</name>
<description>Quadrature Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPE</name>
<description>Consecutive Missing Pulse Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>QIDR</name>
<description>QDEC Interrupt Disable Register</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>IDX</name>
<description>Index</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRCHG</name>
<description>Direction Change</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QERR</name>
<description>Quadrature Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPE</name>
<description>Consecutive Missing Pulse Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>QIMR</name>
<description>QDEC Interrupt Mask Register</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>IDX</name>
<description>Index</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRCHG</name>
<description>Direction Change</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QERR</name>
<description>Quadrature Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPE</name>
<description>Consecutive Missing Pulse Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>QISR</name>
<description>QDEC Interrupt Status Register</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>IDX</name>
<description>Index</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRCHG</name>
<description>Direction Change</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QERR</name>
<description>Quadrature Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPE</name>
<description>Consecutive Missing Pulse Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FMR</name>
<description>Fault Mode Register</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<fields>
<field>
<name>ENCF0</name>
<description>Enable Compare Fault Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENCF1</name>
<description>Enable Compare Fault Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.</description>
<value>0x54494D</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TC0">
<name>TC1</name>
<baseAddress>0x40010000</baseAddress>
<interrupt>
<name>TC3</name>
<value>26</value>
</interrupt>
<interrupt>
<name>TC4</name>
<value>27</value>
</interrupt>
<interrupt>
<name>TC5</name>
<value>28</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TC0">
<name>TC2</name>
<baseAddress>0x40014000</baseAddress>
<interrupt>
<name>TC6</name>
<value>47</value>
</interrupt>
<interrupt>
<name>TC7</name>
<value>48</value>
</interrupt>
<interrupt>
<name>TC8</name>
<value>49</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TC0">
<name>TC3</name>
<baseAddress>0x40054000</baseAddress>
<interrupt>
<name>TC9</name>
<value>50</value>
</interrupt>
<interrupt>
<name>TC10</name>
<value>51</value>
</interrupt>
<interrupt>
<name>TC11</name>
<value>52</value>
</interrupt>
</peripheral>
<peripheral>
<name>TRNG</name>
<version>6334G</version>
<description>True Random Number Generator</description>
<groupName>TRNG</groupName>
<prependToName>TRNG_</prependToName>
<baseAddress>0x40070000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x54</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TRNG</name>
<value>57</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the TRNG to Provide Random Values</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Security Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0x524E47</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<description>Interrupt Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DATRDY</name>
<description>Data Ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODATA</name>
<description>Output Data Register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ODATA</name>
<description>Output Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TWIHS0</name>
<version>11210Z</version>
<description>Two-wire Interface High Speed</description>
<groupName>TWIHS</groupName>
<prependToName>TWIHS_</prependToName>
<baseAddress>0x40018000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TWIHS0</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>START</name>
<description>Send a START Condition</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>Send a STOP Condition</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSEN</name>
<description>TWIHS Master Mode Enabled</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSDIS</name>
<description>TWIHS Master Mode Disabled</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVEN</name>
<description>TWIHS Slave Mode Enabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVDIS</name>
<description>TWIHS Slave Mode Disabled</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QUICK</name>
<description>SMBus Quick Command</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>Software Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSEN</name>
<description>TWIHS High-Speed Mode Enabled</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSDIS</name>
<description>TWIHS High-Speed Mode Disabled</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBEN</name>
<description>SMBus Mode Enabled</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDIS</name>
<description>SMBus Mode Disabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>Packet Error Checking Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECDIS</name>
<description>Packet Error Checking Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECRQ</name>
<description>PEC Request</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLEAR</name>
<description>Bus CLEAR Command</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACMEN</name>
<description>Alternative Command Mode Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACMDIS</name>
<description>Alternative Command Mode Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THRCLR</name>
<description>Transmit Holding Register Clear</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCKCLR</name>
<description>Lock Clear</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFODIS</name>
<description>FIFO Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMR</name>
<description>Master Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>IADRSZ</name>
<description>Internal Device Address Size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>IADRSZSelect</name>
<enumeratedValue>
<name>NONE</name>
<description>No internal device address</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BYTE</name>
<description>One-byte internal device address</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BYTE</name>
<description>Two-byte internal device address</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BYTE</name>
<description>Three-byte internal device address</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MREAD</name>
<description>Master Read Direction</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DADR</name>
<description>Device Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMR</name>
<description>Slave Mode Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>NACKEN</name>
<description>Slave Receiver Data Phase NACK enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMDA</name>
<description>SMBus Default Address</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMHH</name>
<description>SMBus Host Header</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCLWSDIS</name>
<description>Clock Wait State Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK</name>
<description>Slave Address Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SADR</name>
<description>Slave Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SADR1EN</name>
<description>Slave Address 1 Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADR2EN</name>
<description>Slave Address 2 Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADR3EN</name>
<description>Slave Address 3 Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAMEN</name>
<description>Data Matching Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IADR</name>
<description>Internal Address Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>IADR</name>
<description>Internal Address</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWGR</name>
<description>Clock Waveform Generator Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>CLDIV</name>
<description>Clock Low Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CHDIV</name>
<description>Clock High Divider</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CKDIV</name>
<description>Clock Divider</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>HOLD</name>
<description>TWD Hold Time Versus TWCK Falling</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXCOMP</name>
<description>Transmission Completed (cleared by writing TWIHS_THR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Holding Register Ready (cleared by reading TWIHS_RHR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Holding Register Ready (cleared by writing TWIHS_THR)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVREAD</name>
<description>Slave Read</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVACC</name>
<description>Slave Access</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GACC</name>
<description>General Call Access (cleared on read)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error (cleared on read)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error (cleared on read)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Not Acknowledged (cleared on read)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLST</name>
<description>Arbitration Lost (cleared on read)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCLWS</name>
<description>Clock Wait State</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSACC</name>
<description>End Of Slave Access (cleared on read)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCACK</name>
<description>Master Code Acknowledge (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUT</name>
<description>Timeout Error (cleared on read)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECERR</name>
<description>PEC Error (cleared on read)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDAM</name>
<description>SMBus Default Address Match (cleared on read)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHHM</name>
<description>SMBus Host Header Address Match (cleared on read)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL</name>
<description>SCL Line Value</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDA</name>
<description>SDA Line Value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXCOMP</name>
<description>Transmission Completed Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Holding Register Ready Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Holding Register Ready Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVACC</name>
<description>Slave Access Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GACC</name>
<description>General Call Access Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Not Acknowledge Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLST</name>
<description>Arbitration Lost Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_WS</name>
<description>Clock Wait State Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSACC</name>
<description>End Of Slave Access Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCACK</name>
<description>Master Code Acknowledge Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUT</name>
<description>Timeout Error Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECERR</name>
<description>PEC Error Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDAM</name>
<description>SMBus Default Address Match Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHHM</name>
<description>SMBus Host Header Address Match Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXCOMP</name>
<description>Transmission Completed Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Holding Register Ready Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Holding Register Ready Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVACC</name>
<description>Slave Access Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GACC</name>
<description>General Call Access Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Not Acknowledge Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLST</name>
<description>Arbitration Lost Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_WS</name>
<description>Clock Wait State Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSACC</name>
<description>End Of Slave Access Interrupt Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCACK</name>
<description>Master Code Acknowledge Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUT</name>
<description>Timeout Error Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECERR</name>
<description>PEC Error Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDAM</name>
<description>SMBus Default Address Match Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHHM</name>
<description>SMBus Host Header Address Match Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXCOMP</name>
<description>Transmission Completed Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRDY</name>
<description>Receive Holding Register Ready Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmit Holding Register Ready Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVACC</name>
<description>Slave Access Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GACC</name>
<description>General Call Access Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error Interrupt Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Not Acknowledge Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLST</name>
<description>Arbitration Lost Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_WS</name>
<description>Clock Wait State Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSACC</name>
<description>End Of Slave Access Interrupt Mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCACK</name>
<description>Master Code Acknowledge Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUT</name>
<description>Timeout Error Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECERR</name>
<description>PEC Error Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDAM</name>
<description>SMBus Default Address Match Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHHM</name>
<description>SMBus Host Header Address Match Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RHR</name>
<description>Receive Holding Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXDATA</name>
<description>Master or Slave Receive Holding Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmit Holding Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXDATA</name>
<description>Master or Slave Transmit Holding Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMBTR</name>
<description>SMBus Timing Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<fields>
<field>
<name>PRESC</name>
<description>SMBus Clock Prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TLOWS</name>
<description>Slave Clock Stretch Maximum Cycles</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TLOWM</name>
<description>Master Clock Stretch Maximum Cycles</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>THMAX</name>
<description>Clock High Maximum Cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FILTR</name>
<description>Filter Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<fields>
<field>
<name>FILT</name>
<description>RX Digital Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PADFEN</name>
<description>PAD Filter Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PADFCFG</name>
<description>PAD Filter Config</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THRES</name>
<description>Digital Filter Threshold</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWMR</name>
<description>SleepWalking Matching Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<fields>
<field>
<name>SADR1</name>
<description>Slave Address 1</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SADR2</name>
<description>Slave Address 2</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SADR3</name>
<description>Slave Address 3</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>DATAM</name>
<description>Data Match</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0</description>
<value>0x545749</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TWIHS0">
<name>TWIHS1</name>
<baseAddress>0x4001C000</baseAddress>
<interrupt>
<name>TWIHS1</name>
<value>20</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TWIHS0">
<name>TWIHS2</name>
<baseAddress>0x40060000</baseAddress>
<interrupt>
<name>TWIHS2</name>
<value>41</value>
</interrupt>
</peripheral>
<peripheral>
<name>UART0</name>
<version>6418R</version>
<description>Universal Asynchronous Receiver Transmitter</description>
<groupName>UART</groupName>
<prependToName>UART_</prependToName>
<baseAddress>0x400E0800</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RSTRX</name>
<description>Reset Receiver</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTTX</name>
<description>Reset Transmitter</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receiver Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receiver Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmitter Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTSTA</name>
<description>Reset Status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REQCLR</name>
<description>Request Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<fields>
<field>
<name>FILTER</name>
<description>Receiver Digital Filter</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FILTERSelect</name>
<enumeratedValue>
<name>DISABLED</name>
<description>UART does not filter the receive line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PAR</name>
<description>Parity Type</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>PARSelect</name>
<enumeratedValue>
<name>EVEN</name>
<description>Even Parity</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ODD</name>
<description>Odd Parity</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Space: parity forced to 0</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Mark: parity forced to 1</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>NO</name>
<description>No parity</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRSRCCK</name>
<description>Baud Rate Source Clock</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BRSRCCKSelect</name>
<enumeratedValue>
<name>PERIPH_CLK</name>
<description>The baud rate is driven by the peripheral clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PMC_PCK</name>
<description>The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHMODE</name>
<description>Channel Mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CHMODESelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTOMATIC</name>
<description>Automatic echo</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCAL_LOOPBACK</name>
<description>Local loopback</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REMOTE_LOOPBACK</name>
<description>Remote loopback</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Enable RXRDY Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Enable TXRDY Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Enable Overrun Error Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Enable Framing Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Enable Parity Error Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Enable TXEMPTY Interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP</name>
<description>Enable Comparison Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Disable RXRDY Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Disable TXRDY Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Disable Overrun Error Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Disable Framing Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Disable Parity Error Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Disable TXEMPTY Interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP</name>
<description>Disable Comparison Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Mask RXRDY Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Disable TXRDY Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Mask Overrun Error Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Mask Framing Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Mask Parity Error Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Mask TXEMPTY Interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP</name>
<description>Mask Comparison Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmitter Empty</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP</name>
<description>Comparison Match</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RHR</name>
<description>Receive Holding Register</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXCHR</name>
<description>Received Character</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmit Holding Register</description>
<addressOffset>0x001C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXCHR</name>
<description>Character to be Transmitted</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRGR</name>
<description>Baud Rate Generator Register</description>
<addressOffset>0x0020</addressOffset>
<size>32</size>
<fields>
<field>
<name>CD</name>
<description>Clock Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMPR</name>
<description>Comparison Register</description>
<addressOffset>0x0024</addressOffset>
<size>32</size>
<fields>
<field>
<name>VAL1</name>
<description>First Comparison Value for Received Character</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMPMODE</name>
<description>Comparison Mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CMPMODESelect</name>
<enumeratedValue>
<name>FLAG_ONLY</name>
<description>Any character is received and comparison function drives CMP flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONDITION</name>
<description>Comparison condition must be met to start reception.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPPAR</name>
<description>Compare Parity</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VAL2</name>
<description>Second Comparison Value for Received Character</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0x00E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.Always reads as 0.</description>
<value>0x554152</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="UART0">
<name>UART1</name>
<baseAddress>0x400E0A00</baseAddress>
<interrupt>
<name>UART1</name>
<value>8</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="UART0">
<name>UART2</name>
<baseAddress>0x400E1A00</baseAddress>
<interrupt>
<name>UART2</name>
<value>44</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="UART0">
<name>UART3</name>
<baseAddress>0x400E1C00</baseAddress>
<interrupt>
<name>UART3</name>
<value>45</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="UART0">
<name>UART4</name>
<baseAddress>0x400E1E00</baseAddress>
<interrupt>
<name>UART4</name>
<value>46</value>
</interrupt>
</peripheral>
<peripheral>
<name>USART0</name>
<version>6089ZW</version>
<description>Universal Synchronous Asynchronous Receiver Transmitter</description>
<groupName>USART</groupName>
<prependToName>USART_</prependToName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xEC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART0</name>
<value>13</value>
</interrupt>
<registers>
<register>
<name>US_CR_USART_MODE</name>
<description>Control Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RSTRX</name>
<description>Reset Receiver</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTTX</name>
<description>Reset Transmitter</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receiver Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receiver Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmitter Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTSTA</name>
<description>Reset Status Bits</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STTBRK</name>
<description>Start Break</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STPBRK</name>
<description>Stop Break</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STTTO</name>
<description>Clear TIMEOUT Flag and Start Timeout After Next Character Received</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENDA</name>
<description>Send Address</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIT</name>
<description>Reset Iterations</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTNACK</name>
<description>Reset Non Acknowledge</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETTO</name>
<description>Start Timeout Immediately</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTREN</name>
<description>Data Terminal Ready Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRDIS</name>
<description>Data Terminal Ready Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSEN</name>
<description>Request to Send Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSDIS</name>
<description>Request to Send Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CR_SPI_MODE</name>
<description>Control Register</description>
<alternateRegister>US_CR_USART_MODE</alternateRegister>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RSTRX</name>
<description>Reset Receiver</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTTX</name>
<description>Reset Transmitter</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receiver Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receiver Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmitter Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTSTA</name>
<description>Reset Status Bits</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCS</name>
<description>Force SPI Chip Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCS</name>
<description>Release SPI Chip Select</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CR_LIN_MODE</name>
<description>Control Register</description>
<alternateRegister>US_CR_USART_MODE</alternateRegister>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RSTRX</name>
<description>Reset Receiver</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTTX</name>
<description>Reset Transmitter</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEN</name>
<description>Receiver Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDIS</name>
<description>Receiver Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEN</name>
<description>Transmitter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDIS</name>
<description>Transmitter Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTSTA</name>
<description>Reset Status Bits</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINABT</name>
<description>Abort LIN Transmission</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINWKUP</name>
<description>Send LIN Wakeup Signal</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_MR_USART_MODE</name>
<description>Mode Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<fields>
<field>
<name>USART_MODE</name>
<description>USART Mode of Operation</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>USART_MODESelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RS485</name>
<description>RS485</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HW_HANDSHAKING</name>
<description>Hardware handshaking</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODEM</name>
<description>Modem</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IS07816_T_0</name>
<description>IS07816 Protocol: T = 0</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IS07816_T_1</name>
<description>IS07816 Protocol: T = 1</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>IRDA</name>
<description>IrDA</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>LON</name>
<description>LON</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>LIN_MASTER</name>
<description>LIN Master mode</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>LIN_SLAVE</name>
<description>LIN Slave mode</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_MASTER</name>
<description>SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_SLAVE</name>
<description>SPI Slave mode</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USCLKS</name>
<description>Clock Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>USCLKSSelect</name>
<enumeratedValue>
<name>MCK</name>
<description>Peripheral clock is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV</name>
<description>Peripheral clock divided (DIV = 8) is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PCK</name>
<description>PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK</name>
<description>Serial clock (SCK) is selected</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHRL</name>
<description>Character Length</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CHRLSelect</name>
<enumeratedValue>
<name>_5_BIT</name>
<description>Character length is 5 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_6_BIT</name>
<description>Character length is 6 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_7_BIT</name>
<description>Character length is 7 bits</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_BIT</name>
<description>Character length is 8 bits</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNC</name>
<description>Synchronous Mode Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAR</name>
<description>Parity Type</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>PARSelect</name>
<enumeratedValue>
<name>EVEN</name>
<description>Even parity</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ODD</name>
<description>Odd parity</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Parity forced to 0 (Space)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Parity forced to 1 (Mark)</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>NO</name>
<description>No parity</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>MULTIDROP</name>
<description>Multidrop mode</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBSTOP</name>
<description>Number of Stop Bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBSTOPSelect</name>
<enumeratedValue>
<name>_1_BIT</name>
<description>1 stop bit</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_5_BIT</name>
<description>1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BIT</name>
<description>2 stop bits</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHMODE</name>
<description>Channel Mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CHMODESelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTOMATIC</name>
<description>Automatic Echo. Receiver input is connected to the TXD pin.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCAL_LOOPBACK</name>
<description>Local Loopback. Transmitter output is connected to the Receiver Input.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REMOTE_LOOPBACK</name>
<description>Remote Loopback. RXD pin is internally connected to the TXD pin.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Bit Order</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODE9</name>
<description>9-bit Character Length</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKO</name>
<description>Clock Output Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER</name>
<description>Oversampling Mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INACK</name>
<description>Inhibit Non Acknowledge</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSNACK</name>
<description>Disable Successive NACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VAR_SYNC</name>
<description>Variable Synchronization of Command/Data Sync Start Frame Delimiter</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVDATA</name>
<description>Inverted Data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MAX_ITERATION</name>
<description>Maximum Number of Automatic Iteration</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FILTER</name>
<description>Receive Line Filter</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MAN</name>
<description>Manchester Encoder/Decoder Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODSYNC</name>
<description>Manchester Synchronization Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>Start Frame Delimiter Selector</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_MR_SPI_MODE</name>
<description>Mode Register</description>
<alternateRegister>US_MR_USART_MODE</alternateRegister>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<fields>
<field>
<name>USART_MODE</name>
<description>USART Mode of Operation</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>USART_MODESelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RS485</name>
<description>RS485</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HW_HANDSHAKING</name>
<description>Hardware handshaking</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODEM</name>
<description>Modem</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IS07816_T_0</name>
<description>IS07816 Protocol: T = 0</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IS07816_T_1</name>
<description>IS07816 Protocol: T = 1</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>IRDA</name>
<description>IrDA</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>LON</name>
<description>LON</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>LIN_MASTER</name>
<description>LIN Master mode</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>LIN_SLAVE</name>
<description>LIN Slave mode</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_MASTER</name>
<description>SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_SLAVE</name>
<description>SPI Slave mode</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USCLKS</name>
<description>Clock Selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>USCLKSSelect</name>
<enumeratedValue>
<name>MCK</name>
<description>Peripheral clock is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV</name>
<description>Peripheral clock divided (DIV = 8) is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PCK</name>
<description>PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK</name>
<description>Serial clock (SCK) is selected</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHRL</name>
<description>Character Length</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CHRLSelect</name>
<enumeratedValue>
<name>_5_BIT</name>
<description>Character length is 5 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_6_BIT</name>
<description>Character length is 6 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_7_BIT</name>
<description>Character length is 7 bits</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_8_BIT</name>
<description>Character length is 8 bits</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKO</name>
<description>Clock Output Select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>SPI Clock Phase</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>SPI Clock Polarity</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRDBT</name>
<description>Wait Read Data Before Transfer</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IER_USART_MODE</name>
<description>Interrupt Enable Register</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBRK</name>
<description>Receiver Break Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITER</name>
<description>Max number of Repetitions Reached Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Non Acknowledge Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIIC</name>
<description>Ring Indicator Input Change Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSRIC</name>
<description>Data Set Ready Input Change Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDIC</name>
<description>Data Carrier Detect Input Change Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIC</name>
<description>Clear to Send Input Change Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MANE</name>
<description>Manchester Error Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IER_SPI_MODE</name>
<description>Interrupt Enable Register</description>
<alternateRegister>US_IER_USART_MODE</alternateRegister>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSE</name>
<description>NSS Line (Driving CTS Pin) Rising or Falling Edge Event</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IER_LIN_MODE</name>
<description>Interrupt Enable Register</description>
<alternateRegister>US_IER_USART_MODE</alternateRegister>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBK</name>
<description>LIN Break Sent or LIN Break Received Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINID</name>
<description>LIN Identifier Sent or LIN Identifier Received Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINTC</name>
<description>LIN Transfer Completed Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBE</name>
<description>LIN Bus Error Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINISFE</name>
<description>LIN Inconsistent Synch Field Error Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINIPE</name>
<description>LIN Identifier Parity Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCE</name>
<description>LIN Checksum Error Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSNRE</name>
<description>LIN Slave Not Responding Error Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSTE</name>
<description>LIN Synch Tolerance Error Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINHTE</name>
<description>LIN Header Timeout Error Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IER_LON_MODE</name>
<description>Interrupt Enable Register</description>
<alternateRegister>US_IER_USART_MODE</alternateRegister>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSFE</name>
<description>LON Short Frame Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCRCE</name>
<description>LON CRC Error Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LTXD</name>
<description>LON Transmission Done Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCOL</name>
<description>LON Collision Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFET</name>
<description>LON Frame Early Termination Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LRXD</name>
<description>LON Reception Done Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBLOVFE</name>
<description>LON Backlog Overflow Error Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDR_USART_MODE</name>
<description>Interrupt Disable Register</description>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBRK</name>
<description>Receiver Break Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITER</name>
<description>Max Number of Repetitions Reached Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Non Acknowledge Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIIC</name>
<description>Ring Indicator Input Change Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSRIC</name>
<description>Data Set Ready Input Change Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDIC</name>
<description>Data Carrier Detect Input Change Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIC</name>
<description>Clear to Send Input Change Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MANE</name>
<description>Manchester Error Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDR_SPI_MODE</name>
<description>Interrupt Disable Register</description>
<alternateRegister>US_IDR_USART_MODE</alternateRegister>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>SPI Underrun Error Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSE</name>
<description>NSS Line (Driving CTS Pin) Rising or Falling Edge Event</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDR_LIN_MODE</name>
<description>Interrupt Disable Register</description>
<alternateRegister>US_IDR_USART_MODE</alternateRegister>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBK</name>
<description>LIN Break Sent or LIN Break Received Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINID</name>
<description>LIN Identifier Sent or LIN Identifier Received Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINTC</name>
<description>LIN Transfer Completed Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBE</name>
<description>LIN Bus Error Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINISFE</name>
<description>LIN Inconsistent Synch Field Error Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINIPE</name>
<description>LIN Identifier Parity Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCE</name>
<description>LIN Checksum Error Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSNRE</name>
<description>LIN Slave Not Responding Error Interrupt Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSTE</name>
<description>LIN Synch Tolerance Error Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINHTE</name>
<description>LIN Header Timeout Error Interrupt Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDR_LON_MODE</name>
<description>Interrupt Disable Register</description>
<alternateRegister>US_IDR_USART_MODE</alternateRegister>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSFE</name>
<description>LON Short Frame Error Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCRCE</name>
<description>LON CRC Error Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>SPI Underrun Error Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LTXD</name>
<description>LON Transmission Done Interrupt Disable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCOL</name>
<description>LON Collision Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFET</name>
<description>LON Frame Early Termination Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LRXD</name>
<description>LON Reception Done Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBLOVFE</name>
<description>LON Backlog Overflow Error Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IMR_USART_MODE</name>
<description>Interrupt Mask Register</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBRK</name>
<description>Receiver Break Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITER</name>
<description>Max Number of Repetitions Reached Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Non Acknowledge Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIIC</name>
<description>Ring Indicator Input Change Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSRIC</name>
<description>Data Set Ready Input Change Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDIC</name>
<description>Data Carrier Detect Input Change Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIC</name>
<description>Clear to Send Input Change Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MANE</name>
<description>Manchester Error Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IMR_SPI_MODE</name>
<description>Interrupt Mask Register</description>
<alternateRegister>US_IMR_USART_MODE</alternateRegister>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>SPI Underrun Error Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSE</name>
<description>NSS Line (Driving CTS Pin) Rising or Falling Edge Event</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IMR_LIN_MODE</name>
<description>Interrupt Mask Register</description>
<alternateRegister>US_IMR_USART_MODE</alternateRegister>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error Interrupt Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout Interrupt Mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBK</name>
<description>LIN Break Sent or LIN Break Received Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINID</name>
<description>LIN Identifier Sent or LIN Identifier Received Interrupt Mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINTC</name>
<description>LIN Transfer Completed Interrupt Mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBE</name>
<description>LIN Bus Error Interrupt Mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINISFE</name>
<description>LIN Inconsistent Synch Field Error Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINIPE</name>
<description>LIN Identifier Parity Interrupt Mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCE</name>
<description>LIN Checksum Error Interrupt Mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSNRE</name>
<description>LIN Slave Not Responding Error Interrupt Mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSTE</name>
<description>LIN Synch Tolerance Error Interrupt Mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINHTE</name>
<description>LIN Header Timeout Error Interrupt Mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IMR_LON_MODE</name>
<description>Interrupt Mask Register</description>
<alternateRegister>US_IMR_USART_MODE</alternateRegister>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>RXRDY Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>TXRDY Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSFE</name>
<description>LON Short Frame Error Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCRCE</name>
<description>LON CRC Error Interrupt Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>TXEMPTY Interrupt Mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>SPI Underrun Error Interrupt Mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LTXD</name>
<description>LON Transmission Done Interrupt Mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCOL</name>
<description>LON Collision Interrupt Mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFET</name>
<description>LON Frame Early Termination Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LRXD</name>
<description>LON Reception Done Interrupt Mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBLOVFE</name>
<description>LON Backlog Overflow Error Interrupt Mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CSR_USART_MODE</name>
<description>Channel Status Register</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready (cleared by reading US_RHR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready (cleared by writing US_THR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBRK</name>
<description>Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmitter Empty (cleared by writing US_THR)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITER</name>
<description>Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIIC</name>
<description>Ring Indicator Input Change Flag (cleared on read)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSRIC</name>
<description>Data Set Ready Input Change Flag (cleared on read)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDIC</name>
<description>Data Carrier Detect Input Change Flag (cleared on read)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIC</name>
<description>Clear to Send Input Change Flag (cleared on read)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RI</name>
<description>Image of RI Input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR</name>
<description>Image of DSR Input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCD</name>
<description>Image of DCD Input</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>Image of CTS Input</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MANERR</name>
<description>Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CSR_SPI_MODE</name>
<description>Channel Status Register</description>
<alternateRegister>US_CSR_USART_MODE</alternateRegister>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready (cleared by reading US_RHR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready (cleared by writing US_THR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmitter Empty (cleared by writing US_THR)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>SPI Underrun Error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSE</name>
<description>NSS Line (Driving CTS Pin) Rising or Falling Edge Event</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSS</name>
<description>Image of NSS Line</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CSR_LIN_MODE</name>
<description>Channel Status Register</description>
<alternateRegister>US_CSR_USART_MODE</alternateRegister>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready (cleared by reading US_RHR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready (cleared by writing US_THR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME</name>
<description>Framing Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARE</name>
<description>Parity Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmitter Empty (cleared by writing US_THR)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBK</name>
<description>LIN Break Sent or LIN Break Received</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINID</name>
<description>LIN Identifier Sent or LIN Identifier Received</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINTC</name>
<description>LIN Transfer Completed</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBLS</name>
<description>LIN Bus Line Status</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINBE</name>
<description>LIN Bus Error</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINISFE</name>
<description>LIN Inconsistent Synch Field Error</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINIPE</name>
<description>LIN Identifier Parity Error</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCE</name>
<description>LIN Checksum Error</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSNRE</name>
<description>LIN Slave Not Responding Error Interrupt Mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINSTE</name>
<description>LIN Synch Tolerance Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINHTE</name>
<description>LIN Header Timeout Error</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_CSR_LON_MODE</name>
<description>Channel Status Register</description>
<alternateRegister>US_CSR_USART_MODE</alternateRegister>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready (cleared by reading US_RHR)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready (cleared by writing US_THR)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRE</name>
<description>Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSFE</name>
<description>LON Short Frame Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCRCE</name>
<description>LON CRC Error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmitter Empty (cleared by writing US_THR)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNRE</name>
<description>Underrun Error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LTXD</name>
<description>LON Transmission End Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCOL</name>
<description>LON Collision Detected Flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFET</name>
<description>LON Frame Early Termination</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LRXD</name>
<description>LON Reception End Flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBLOVFE</name>
<description>LON Backlog Overflow Error</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_RHR</name>
<description>Receive Holding Register</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXCHR</name>
<description>Received Character</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RXSYNH</name>
<description>Received Sync</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_THR</name>
<description>Transmit Holding Register</description>
<addressOffset>0x001C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXCHR</name>
<description>Character to be Transmitted</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>TXSYNH</name>
<description>Sync Field to be Transmitted</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_BRGR</name>
<description>Baud Rate Generator Register</description>
<addressOffset>0x0020</addressOffset>
<size>32</size>
<fields>
<field>
<name>CD</name>
<description>Clock Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FP</name>
<description>Fractional Part</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_RTOR</name>
<description>Receiver Timeout Register</description>
<addressOffset>0x0024</addressOffset>
<size>32</size>
<fields>
<field>
<name>TO</name>
<description>Timeout Value</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_TTGR_USART_MODE</name>
<description>Transmitter Timeguard Register</description>
<addressOffset>0x0028</addressOffset>
<size>32</size>
<fields>
<field>
<name>TG</name>
<description>Timeguard Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_TTGR_LON_MODE</name>
<description>Transmitter Timeguard Register</description>
<alternateRegister>US_TTGR_USART_MODE</alternateRegister>
<addressOffset>0x0028</addressOffset>
<size>32</size>
<fields>
<field>
<name>PCYCLE</name>
<description>LON PCYCLE Length</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_FIDI_USART_MODE</name>
<description>FI DI Ratio Register</description>
<addressOffset>0x0040</addressOffset>
<size>32</size>
<fields>
<field>
<name>FI_DI_RATIO</name>
<description>FI Over DI Ratio Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_FIDI_LON_MODE</name>
<description>FI DI Ratio Register</description>
<alternateRegister>US_FIDI_USART_MODE</alternateRegister>
<addressOffset>0x0040</addressOffset>
<size>32</size>
<fields>
<field>
<name>BETA2</name>
<description>LON BETA2 Length</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_NER</name>
<description>Number of Errors Register</description>
<addressOffset>0x0044</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NB_ERRORS</name>
<description>Number of Errors</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IF</name>
<description>IrDA Filter Register</description>
<addressOffset>0x004C</addressOffset>
<size>32</size>
<fields>
<field>
<name>IRDA_FILTER</name>
<description>IrDA Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_MAN</name>
<description>Manchester Configuration Register</description>
<addressOffset>0x0050</addressOffset>
<size>32</size>
<fields>
<field>
<name>TX_PL</name>
<description>Transmitter Preamble Length</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TX_PP</name>
<description>Transmitter Preamble Pattern</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>TX_PPSelect</name>
<enumeratedValue>
<name>ALL_ONE</name>
<description>The preamble is composed of '1's</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ALL_ZERO</name>
<description>The preamble is composed of '0's</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ZERO_ONE</name>
<description>The preamble is composed of '01's</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_ZERO</name>
<description>The preamble is composed of '10's</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX_MPOL</name>
<description>Transmitter Manchester Polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_PL</name>
<description>Receiver Preamble Length</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RX_PP</name>
<description>Receiver Preamble Pattern detected</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>RX_PPSelect</name>
<enumeratedValue>
<name>ALL_ONE</name>
<description>The preamble is composed of '1's</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ALL_ZERO</name>
<description>The preamble is composed of '0's</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ZERO_ONE</name>
<description>The preamble is composed of '01's</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_ZERO</name>
<description>The preamble is composed of '10's</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RX_MPOL</name>
<description>Receiver Manchester Polarity</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONE</name>
<description>Must Be Set to 1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRIFT</name>
<description>Drift Compensation</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXIDLEV</name>
<description>Receiver Idle Value</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LINMR</name>
<description>LIN Mode Register</description>
<addressOffset>0x0054</addressOffset>
<size>32</size>
<fields>
<field>
<name>NACT</name>
<description>LIN Node Action</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NACTSelect</name>
<enumeratedValue>
<name>PUBLISH</name>
<description>The USART transmits the response.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SUBSCRIBE</name>
<description>The USART receives the response.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IGNORE</name>
<description>The USART does not transmit and does not receive the response.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARDIS</name>
<description>Parity Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHKDIS</name>
<description>Checksum Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHKTYP</name>
<description>Checksum Type</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLM</name>
<description>Data Length Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSDIS</name>
<description>Frame Slot Mode Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPTYP</name>
<description>Wakeup Signal Type</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLC</name>
<description>Data Length Control</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PDCM</name>
<description>DMAC Mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCDIS</name>
<description>Synchronization Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LINIR</name>
<description>LIN Identifier Register</description>
<addressOffset>0x0058</addressOffset>
<size>32</size>
<fields>
<field>
<name>IDCHR</name>
<description>Identifier Character</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LINBRR</name>
<description>LIN Baud Rate Register</description>
<addressOffset>0x005C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LINCD</name>
<description>Clock Divider after Synchronization</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>LINFP</name>
<description>Fractional Part after Synchronization</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONMR</name>
<description>LON Mode Register</description>
<addressOffset>0x0060</addressOffset>
<size>32</size>
<fields>
<field>
<name>COMMT</name>
<description>LON comm_type Parameter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COLDET</name>
<description>LON Collision Detection Feature</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCOL</name>
<description>Terminate Frame upon Collision Notification</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDTAIL</name>
<description>LON Collision Detection on Frame Tail</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAM</name>
<description>LON DMA Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDS</name>
<description>LON Collision Detection Source</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOFS</name>
<description>End of Frame Condition Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONPR</name>
<description>LON Preamble Register</description>
<addressOffset>0x0064</addressOffset>
<size>32</size>
<fields>
<field>
<name>LONPL</name>
<description>LON Preamble Length</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONDL</name>
<description>LON Data Length Register</description>
<addressOffset>0x0068</addressOffset>
<size>32</size>
<fields>
<field>
<name>LONDL</name>
<description>LON Data Length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONL2HDR</name>
<description>LON L2HDR Register</description>
<addressOffset>0x006C</addressOffset>
<size>32</size>
<fields>
<field>
<name>BLI</name>
<description>LON Backlog Increment</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>ALTP</name>
<description>LON Alternate Path Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB</name>
<description>LON Priority Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONBL</name>
<description>LON Backlog Register</description>
<addressOffset>0x0070</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>LONBL</name>
<description>LON Node Backlog Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONB1TX</name>
<description>LON Beta1 Tx Register</description>
<addressOffset>0x0074</addressOffset>
<size>32</size>
<fields>
<field>
<name>BETA1TX</name>
<description>LON Beta1 Length after Transmission</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONB1RX</name>
<description>LON Beta1 Rx Register</description>
<addressOffset>0x0078</addressOffset>
<size>32</size>
<fields>
<field>
<name>BETA1RX</name>
<description>LON Beta1 Length after Reception</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_LONPRIO</name>
<description>LON Priority Register</description>
<addressOffset>0x007C</addressOffset>
<size>32</size>
<fields>
<field>
<name>PSNB</name>
<description>LON Priority Slot Number</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NPS</name>
<description>LON Node Priority Slot</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDTTX</name>
<description>LON IDT Tx Register</description>
<addressOffset>0x0080</addressOffset>
<size>32</size>
<fields>
<field>
<name>IDTTX</name>
<description>LON Indeterminate Time after Transmission (comm_type = 1 mode only)</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_IDTRX</name>
<description>LON IDT Rx Register</description>
<addressOffset>0x0084</addressOffset>
<size>32</size>
<fields>
<field>
<name>IDTRX</name>
<description>LON Indeterminate Time after Reception (comm_type = 1 mode only)</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_ICDIFF</name>
<description>IC DIFF Register</description>
<addressOffset>0x0088</addressOffset>
<size>32</size>
<fields>
<field>
<name>ICDIFF</name>
<description>IC Differentiator Number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>US_WPMR</name>
<description>Write Protection Mode Register</description>
<addressOffset>0x00E4</addressOffset>
<size>32</size>
<fields>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPKEY</name>
<description>Write Protection Key</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<enumeratedValues>
<name>WPKEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.</description>
<value>0x555341</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>US_WPSR</name>
<description>Write Protection Status Register</description>
<addressOffset>0x00E8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WPVS</name>
<description>Write Protection Violation Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WPVSRC</name>
<description>Write Protection Violation Source</description>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART1</name>
<baseAddress>0x40028000</baseAddress>
<interrupt>
<name>USART1</name>
<value>14</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART2</name>
<baseAddress>0x4002C000</baseAddress>
<interrupt>
<name>USART2</name>
<value>15</value>
</interrupt>
</peripheral>
<peripheral>
<name>USBHS</name>
<version>11292G</version>
<description>USB High-Speed Interface</description>
<groupName>USBHS</groupName>
<prependToName>USBHS_</prependToName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x810</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USBHS</name>
<value>34</value>
</interrupt>
<registers>
<register>
<name>DEVCTRL</name>
<description>Device General Control Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<fields>
<field>
<name>UADD</name>
<description>USB Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ADDEN</name>
<description>Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DETACH</name>
<description>Detach</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMWKUP</name>
<description>Remote Wake-Up</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPDCONF</name>
<description>Mode Configuration</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SPDCONFSelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER</name>
<description>For a better consumption, if high speed is not needed.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_SPEED</name>
<description>Forced high speed.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_FS</name>
<description>The peripheral remains in Full-speed mode whatever the host speed capability.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LS</name>
<description>Low-Speed Mode Force</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTJ</name>
<description>Test mode J</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTK</name>
<description>Test mode K</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTPCKT</name>
<description>Test packet mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPMODE2</name>
<description>Specific Operational mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVISR</name>
<description>Device Global Interrupt Status Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>SUSP</name>
<description>Suspend Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOF</name>
<description>Micro Start of Frame Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF</name>
<description>Start of Frame Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORST</name>
<description>End of Reset Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUP</name>
<description>Wake-Up Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSM</name>
<description>End of Resume Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSM</name>
<description>Upstream Resume Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Endpoint 0 Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Endpoint 1 Interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Endpoint 2 Interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Endpoint 3 Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Endpoint 4 Interrupt</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Endpoint 5 Interrupt</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Endpoint 6 Interrupt</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Endpoint 7 Interrupt</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Endpoint 8 Interrupt</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Endpoint 9 Interrupt</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 1 Interrupt</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 2 Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 3 Interrupt</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 4 Interrupt</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 5 Interrupt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 6 Interrupt</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 7 Interrupt</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVICR</name>
<description>Device Global Interrupt Clear Register</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SUSPC</name>
<description>Suspend Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOFC</name>
<description>Micro Start of Frame Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFC</name>
<description>Start of Frame Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSTC</name>
<description>End of Reset Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUPC</name>
<description>Wake-Up Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSMC</name>
<description>End of Resume Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSMC</name>
<description>Upstream Resume Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVIFR</name>
<description>Device Global Interrupt Set Register</description>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SUSPS</name>
<description>Suspend Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOFS</name>
<description>Micro Start of Frame Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFS</name>
<description>Start of Frame Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSTS</name>
<description>End of Reset Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUPS</name>
<description>Wake-Up Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSMS</name>
<description>End of Resume Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSMS</name>
<description>Upstream Resume Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 1 Interrupt Set</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 2 Interrupt Set</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 3 Interrupt Set</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 4 Interrupt Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 5 Interrupt Set</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 6 Interrupt Set</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 7 Interrupt Set</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVIMR</name>
<description>Device Global Interrupt Mask Register</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>SUSPE</name>
<description>Suspend Interrupt Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOFE</name>
<description>Micro Start of Frame Interrupt Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFE</name>
<description>Start of Frame Interrupt Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSTE</name>
<description>End of Reset Interrupt Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUPE</name>
<description>Wake-Up Interrupt Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSME</name>
<description>End of Resume Interrupt Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSME</name>
<description>Upstream Resume Interrupt Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Endpoint 0 Interrupt Mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Endpoint 1 Interrupt Mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Endpoint 2 Interrupt Mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Endpoint 3 Interrupt Mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Endpoint 4 Interrupt Mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Endpoint 5 Interrupt Mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Endpoint 6 Interrupt Mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Endpoint 7 Interrupt Mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Endpoint 8 Interrupt Mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Endpoint 9 Interrupt Mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 1 Interrupt Mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 2 Interrupt Mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 3 Interrupt Mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 4 Interrupt Mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 5 Interrupt Mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 6 Interrupt Mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 7 Interrupt Mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVIDR</name>
<description>Device Global Interrupt Disable Register</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SUSPEC</name>
<description>Suspend Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOFEC</name>
<description>Micro Start of Frame Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFEC</name>
<description>Start of Frame Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSTEC</name>
<description>End of Reset Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUPEC</name>
<description>Wake-Up Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSMEC</name>
<description>End of Resume Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSMEC</name>
<description>Upstream Resume Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Endpoint 0 Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Endpoint 1 Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Endpoint 2 Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Endpoint 3 Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Endpoint 4 Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Endpoint 5 Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Endpoint 6 Interrupt Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Endpoint 7 Interrupt Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Endpoint 8 Interrupt Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Endpoint 9 Interrupt Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 1 Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 2 Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 3 Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 4 Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 5 Interrupt Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 6 Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 7 Interrupt Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVIER</name>
<description>Device Global Interrupt Enable Register</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SUSPES</name>
<description>Suspend Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSOFES</name>
<description>Micro Start of Frame Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFES</name>
<description>Start of Frame Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSTES</name>
<description>End of Reset Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUPES</name>
<description>Wake-Up Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EORSMES</name>
<description>End of Resume Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPRSMES</name>
<description>Upstream Resume Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Endpoint 0 Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Endpoint 1 Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Endpoint 2 Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Endpoint 3 Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Endpoint 4 Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Endpoint 5 Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Endpoint 6 Interrupt Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Endpoint 7 Interrupt Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Endpoint 8 Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Endpoint 9 Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 1 Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 2 Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 3 Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 4 Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 5 Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 6 Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 7 Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVEPT</name>
<description>Device Endpoint Register</description>
<addressOffset>0x001C</addressOffset>
<size>32</size>
<fields>
<field>
<name>EPEN0</name>
<description>Endpoint 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN1</name>
<description>Endpoint 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN2</name>
<description>Endpoint 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN3</name>
<description>Endpoint 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN4</name>
<description>Endpoint 4 Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN5</name>
<description>Endpoint 5 Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN6</name>
<description>Endpoint 6 Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN7</name>
<description>Endpoint 7 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN8</name>
<description>Endpoint 8 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPEN9</name>
<description>Endpoint 9 Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST0</name>
<description>Endpoint 0 Reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST1</name>
<description>Endpoint 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST2</name>
<description>Endpoint 2 Reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST3</name>
<description>Endpoint 3 Reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST4</name>
<description>Endpoint 4 Reset</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST5</name>
<description>Endpoint 5 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST6</name>
<description>Endpoint 6 Reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST7</name>
<description>Endpoint 7 Reset</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST8</name>
<description>Endpoint 8 Reset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPRST9</name>
<description>Endpoint 9 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVFNUM</name>
<description>Device Frame Number Register</description>
<addressOffset>0x0020</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>MFNUM</name>
<description>Micro Frame Number</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FNUM</name>
<description>Frame Number</description>
<bitOffset>3</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>FNCERR</name>
<description>Frame Number CRC Error</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTCFG[%s]</name>
<description>Device Endpoint Configuration Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<fields>
<field>
<name>ALLOC</name>
<description>Endpoint Memory Allocate</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPBK</name>
<description>Endpoint Banks</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>EPBKSelect</name>
<enumeratedValue>
<name>1_BANK</name>
<description>Single-bank endpoint</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_BANK</name>
<description>Double-bank endpoint</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>3_BANK</name>
<description>Triple-bank endpoint</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EPSIZE</name>
<description>Endpoint Size</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>EPSIZESelect</name>
<enumeratedValue>
<name>8_BYTE</name>
<description>8 bytes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>16_BYTE</name>
<description>16 bytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>32_BYTE</name>
<description>32 bytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>64_BYTE</name>
<description>64 bytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>128_BYTE</name>
<description>128 bytes</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>256_BYTE</name>
<description>256 bytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>512_BYTE</name>
<description>512 bytes</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>1024_BYTE</name>
<description>1024 bytes</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint Direction</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>EPDIRSelect</name>
<enumeratedValue>
<name>OUT</name>
<description>The endpoint direction is OUT.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>The endpoint direction is IN (nor for control endpoints).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOSW</name>
<description>Automatic Switch</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYPE</name>
<description>Endpoint Type</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>EPTYPESelect</name>
<enumeratedValue>
<name>CTRL</name>
<description>Control</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO</name>
<description>Isochronous</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BLK</name>
<description>Bulk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INTRPT</name>
<description>Interrupt</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBTRANS</name>
<description>Number of transactions per microframe for isochronous endpoint</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBTRANSSelect</name>
<enumeratedValue>
<name>_0_TRANS</name>
<description>Reserved to endpoint that does not have the high-bandwidth isochronous capability.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_TRANS</name>
<description>Default value: one transaction per microframe.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_TRANS</name>
<description>Two transactions per microframe. This endpoint should be configured as double-bank.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_TRANS</name>
<description>Three transactions per microframe. This endpoint should be configured as triple-bank.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTISR_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Status Register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINI</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTI</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPI</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTI</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINI</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDI</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKET</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA2</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MDATA</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRLDIR</name>
<description>Control Direction</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYCT</name>
<description>Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTISR_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Status Register</description>
<alternateRegister>DEVEPTISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINI</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTI</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFI</name>
<description>Underflow Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERRI</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHI</name>
<description>High Bandwidth Isochronous IN Flush Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRI</name>
<description>CRC Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKET</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA2</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MDATA</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERRORTRANS</name>
<description>High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYCT</name>
<description>Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTISR_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Status Register</description>
<alternateRegister>DEVEPTISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINI</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTI</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPI</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTI</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINI</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDI</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKET</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA2</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MDATA</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRLDIR</name>
<description>Control Direction</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYCT</name>
<description>Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTISR_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Status Register</description>
<alternateRegister>DEVEPTISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINI</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTI</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPI</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTI</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINI</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDI</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKET</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA2</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MDATA</name>
<description>Reserved for high-bandwidth isochronous endpoint</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRLDIR</name>
<description>Control Direction</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYCT</name>
<description>Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTICR_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Clear Register</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIC</name>
<description>Transmitted IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTICR_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Clear Register</description>
<alternateRegister>DEVEPTICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIC</name>
<description>Transmitted IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIC</name>
<description>Underflow Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERRIC</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHIC</name>
<description>High Bandwidth Isochronous IN Flush Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRIC</name>
<description>CRC Error Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTICR_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Clear Register</description>
<alternateRegister>DEVEPTICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIC</name>
<description>Transmitted IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTICR_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Clear Register</description>
<alternateRegister>DEVEPTICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIC</name>
<description>Transmitted IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIFR_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Set Register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIS</name>
<description>Transmitted IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIS</name>
<description>Received OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIS</name>
<description>Received SETUP Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIS</name>
<description>NAKed OUT Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIS</name>
<description>NAKed IN Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIS</name>
<description>STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Interrupt Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIFR_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Set Register</description>
<alternateRegister>DEVEPTIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIS</name>
<description>Transmitted IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIS</name>
<description>Received OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIS</name>
<description>Underflow Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERRIS</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHIS</name>
<description>High Bandwidth Isochronous IN Flush Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRIS</name>
<description>CRC Error Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Interrupt Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIFR_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Set Register</description>
<alternateRegister>DEVEPTIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIS</name>
<description>Transmitted IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIS</name>
<description>Received OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIS</name>
<description>Received SETUP Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIS</name>
<description>NAKed OUT Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIS</name>
<description>NAKed IN Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIS</name>
<description>STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Interrupt Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIFR_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Set Register</description>
<alternateRegister>DEVEPTIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINIS</name>
<description>Transmitted IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTIS</name>
<description>Received OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPIS</name>
<description>Received SETUP Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTIS</name>
<description>NAKed OUT Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINIS</name>
<description>NAKed IN Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDIS</name>
<description>STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Interrupt Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIMR_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Mask Register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINE</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTE</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPE</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTE</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINE</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFE</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDE</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETE</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBK</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMA</name>
<description>Endpoint Interrupts Disable HDMA Request</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDIS</name>
<description>NYET Token Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQ</name>
<description>STALL Request</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIMR_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Mask Register</description>
<alternateRegister>DEVEPTIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINE</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTE</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFE</name>
<description>Underflow Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERRE</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHE</name>
<description>High Bandwidth Isochronous IN Flush Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFE</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRE</name>
<description>CRC Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETE</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDATAE</name>
<description>MData Interrupt</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAXE</name>
<description>DataX Interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRORTRANSE</name>
<description>Transaction Error Interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBK</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMA</name>
<description>Endpoint Interrupts Disable HDMA Request</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIMR_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Mask Register</description>
<alternateRegister>DEVEPTIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINE</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTE</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPE</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTE</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINE</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFE</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDE</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETE</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBK</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMA</name>
<description>Endpoint Interrupts Disable HDMA Request</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDIS</name>
<description>NYET Token Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQ</name>
<description>STALL Request</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIMR_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Mask Register</description>
<alternateRegister>DEVEPTIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>TXINE</name>
<description>Transmitted IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTE</name>
<description>Received OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPE</name>
<description>Received SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTE</name>
<description>NAKed OUT Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINE</name>
<description>NAKed IN Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFE</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDE</name>
<description>STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETE</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBK</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMA</name>
<description>Endpoint Interrupts Disable HDMA Request</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDIS</name>
<description>NYET Token Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQ</name>
<description>STALL Request</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIER_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Enable Register</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINES</name>
<description>Transmitted IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTES</name>
<description>Received OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPES</name>
<description>Received SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTES</name>
<description>NAKed OUT Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINES</name>
<description>NAKed IN Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDES</name>
<description>STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBKS</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONS</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAS</name>
<description>Endpoint Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISS</name>
<description>NYET Token Disable Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQS</name>
<description>STALL Request Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIER_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Enable Register</description>
<alternateRegister>DEVEPTIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINES</name>
<description>Transmitted IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTES</name>
<description>Received OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFES</name>
<description>Underflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERRES</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHES</name>
<description>High Bandwidth Isochronous IN Flush Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRES</name>
<description>CRC Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDATAES</name>
<description>MData Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAXES</name>
<description>DataX Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRORTRANSES</name>
<description>Transaction Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBKS</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONS</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAS</name>
<description>Endpoint Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIER_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Enable Register</description>
<alternateRegister>DEVEPTIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINES</name>
<description>Transmitted IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTES</name>
<description>Received OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPES</name>
<description>Received SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTES</name>
<description>NAKed OUT Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINES</name>
<description>NAKed IN Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDES</name>
<description>STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBKS</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONS</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAS</name>
<description>Endpoint Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISS</name>
<description>NYET Token Disable Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQS</name>
<description>STALL Request Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIER_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Enable Register</description>
<alternateRegister>DEVEPTIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINES</name>
<description>Transmitted IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTES</name>
<description>Received OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPES</name>
<description>Received SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTES</name>
<description>NAKed OUT Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINES</name>
<description>NAKed IN Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDES</name>
<description>STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KILLBKS</name>
<description>Kill IN Bank</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONS</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAS</name>
<description>Endpoint Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISS</name>
<description>NYET Token Disable Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQS</name>
<description>STALL Request Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIDR_CTRL_MODE[%s]</name>
<description>Device Endpoint Interrupt Disable Register</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINEC</name>
<description>Transmitted IN Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTEC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPEC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTEC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINEC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFEC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDEC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETEC</name>
<description>Shortpacket Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Interrupt Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAC</name>
<description>Endpoint Interrupts Disable HDMA Request Clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISC</name>
<description>NYET Token Disable Clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQC</name>
<description>STALL Request Clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIDR_ISO_MODE[%s]</name>
<description>Device Endpoint Interrupt Disable Register</description>
<alternateRegister>DEVEPTIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINEC</name>
<description>Transmitted IN Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTEC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFEC</name>
<description>Underflow Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOINERREC</name>
<description>High Bandwidth Isochronous IN Underflow Error Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBISOFLUSHEC</name>
<description>High Bandwidth Isochronous IN Flush Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFEC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETEC</name>
<description>Shortpacket Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDATAEC</name>
<description>MData Interrupt Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAXEC</name>
<description>DataX Interrupt Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRORTRANSEC</name>
<description>Transaction Error Interrupt Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Interrupt Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAC</name>
<description>Endpoint Interrupts Disable HDMA Request Clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIDR_BLK_MODE[%s]</name>
<description>Device Endpoint Interrupt Disable Register</description>
<alternateRegister>DEVEPTIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINEC</name>
<description>Transmitted IN Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTEC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPEC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTEC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINEC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFEC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDEC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETEC</name>
<description>Shortpacket Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Interrupt Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAC</name>
<description>Endpoint Interrupts Disable HDMA Request Clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISC</name>
<description>NYET Token Disable Clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQC</name>
<description>STALL Request Clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>DEVEPTIDR_INTRPT_MODE[%s]</name>
<description>Device Endpoint Interrupt Disable Register</description>
<alternateRegister>DEVEPTIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>TXINEC</name>
<description>Transmitted IN Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOUTEC</name>
<description>Received OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTPEC</name>
<description>Received SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKOUTEC</name>
<description>NAKed OUT Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKINEC</name>
<description>NAKed IN Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFEC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLEDEC</name>
<description>STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETEC</name>
<description>Shortpacket Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Interrupt Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISHDMAC</name>
<description>Endpoint Interrupts Disable HDMA Request Clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETDISC</name>
<description>NYET Token Disable Clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLRQC</name>
<description>STALL Request Clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>7</dim>
<dimIncrement>16</dimIncrement>
<name>USBHS_DEVDMA[%s]</name>
<description>Device DMA Channel Next Descriptor Address Register</description>
<addressOffset>0x310</addressOffset>
<register>
<name>DEVDMANXTDSC</name>
<description>Device DMA Channel Next Descriptor Address Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>NXT_DSC_ADD</name>
<description>Next Descriptor Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVDMAADDRESS</name>
<description>Device DMA Channel Address Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>BUFF_ADD</name>
<description>Buffer Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVDMACONTROL</name>
<description>Device DMA Channel Control Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHANN_ENB</name>
<description>Channel Enable Command</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDNXT_DSC</name>
<description>Load Next Channel Transfer Descriptor Enable Command</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_EN</name>
<description>End of Transfer Enable Control (OUT transfers only)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_B_EN</name>
<description>End of Buffer Enable Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_IT</name>
<description>End of Transfer Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_BUFFIT</name>
<description>End of Buffer Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DESC_LD_IT</name>
<description>Descriptor Loaded Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURST_LCK</name>
<description>Burst Lock Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUFF_LENGTH</name>
<description>Buffer Byte Length (Write-only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVDMASTATUS</name>
<description>Device DMA Channel Status Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHANN_ENB</name>
<description>Channel Enable Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHANN_ACT</name>
<description>Channel Active Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_ST</name>
<description>End of Channel Transfer Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_BF_ST</name>
<description>End of Channel Buffer Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DESC_LDST</name>
<description>Descriptor Loaded Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUFF_COUNT</name>
<description>Buffer Byte Count</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>HSTCTRL</name>
<description>Host General Control Register</description>
<addressOffset>0x0400</addressOffset>
<size>32</size>
<fields>
<field>
<name>SOFE</name>
<description>Start of Frame Generation Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESET</name>
<description>Send USB Reset</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESUME</name>
<description>Send USB Resume</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPDCONF</name>
<description>Mode Configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SPDCONFSelect</name>
<enumeratedValue>
<name>NORMAL</name>
<description>The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER</name>
<description>For a better consumption, if high speed is not needed.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_SPEED</name>
<description>Forced high speed.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_FS</name>
<description>The host remains in Full-speed mode whatever the peripheral speed capability.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HSTISR</name>
<description>Host Global Interrupt Status Register</description>
<addressOffset>0x0404</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DCONNI</name>
<description>Device Connection Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCI</name>
<description>Device Disconnection Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTI</name>
<description>USB Reset Sent Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDI</name>
<description>Downstream Resume Sent Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMI</name>
<description>Upstream Resume Received Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFI</name>
<description>Host Start of Frame Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPI</name>
<description>Host Wake-Up Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Pipe 0 Interrupt</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Pipe 1 Interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Pipe 2 Interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Pipe 3 Interrupt</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Pipe 4 Interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Pipe 5 Interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Pipe 6 Interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Pipe 7 Interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Pipe 8 Interrupt</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Pipe 9 Interrupt</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 0 Interrupt</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 1 Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 2 Interrupt</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 3 Interrupt</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 4 Interrupt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 5 Interrupt</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 6 Interrupt</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTICR</name>
<description>Host Global Interrupt Clear Register</description>
<addressOffset>0x0408</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DCONNIC</name>
<description>Device Connection Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCIC</name>
<description>Device Disconnection Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIC</name>
<description>USB Reset Sent Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDIC</name>
<description>Downstream Resume Sent Interrupt Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMIC</name>
<description>Upstream Resume Received Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFIC</name>
<description>Host Start of Frame Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPIC</name>
<description>Host Wake-Up Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIFR</name>
<description>Host Global Interrupt Set Register</description>
<addressOffset>0x040C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DCONNIS</name>
<description>Device Connection Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCIS</name>
<description>Device Disconnection Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIS</name>
<description>USB Reset Sent Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDIS</name>
<description>Downstream Resume Sent Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMIS</name>
<description>Upstream Resume Received Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFIS</name>
<description>Host Start of Frame Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPIS</name>
<description>Host Wake-Up Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 0 Interrupt Set</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 1 Interrupt Set</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 2 Interrupt Set</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 3 Interrupt Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 4 Interrupt Set</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 5 Interrupt Set</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 6 Interrupt Set</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMR</name>
<description>Host Global Interrupt Mask Register</description>
<addressOffset>0x0410</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>DCONNIE</name>
<description>Device Connection Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCIE</name>
<description>Device Disconnection Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>USB Reset Sent Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDIE</name>
<description>Downstream Resume Sent Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMIE</name>
<description>Upstream Resume Received Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFIE</name>
<description>Host Start of Frame Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPIE</name>
<description>Host Wake-Up Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Pipe 0 Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Pipe 1 Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Pipe 2 Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Pipe 3 Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Pipe 4 Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Pipe 5 Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Pipe 6 Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Pipe 7 Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Pipe 8 Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Pipe 9 Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 0 Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 1 Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 2 Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 3 Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 4 Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 5 Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 6 Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIDR</name>
<description>Host Global Interrupt Disable Register</description>
<addressOffset>0x0414</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DCONNIEC</name>
<description>Device Connection Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCIEC</name>
<description>Device Disconnection Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIEC</name>
<description>USB Reset Sent Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDIEC</name>
<description>Downstream Resume Sent Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMIEC</name>
<description>Upstream Resume Received Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFIEC</name>
<description>Host Start of Frame Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPIEC</name>
<description>Host Wake-Up Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Pipe 0 Interrupt Disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Pipe 1 Interrupt Disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Pipe 2 Interrupt Disable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Pipe 3 Interrupt Disable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Pipe 4 Interrupt Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Pipe 5 Interrupt Disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Pipe 6 Interrupt Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Pipe 7 Interrupt Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Pipe 8 Interrupt Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Pipe 9 Interrupt Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 0 Interrupt Disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 1 Interrupt Disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 2 Interrupt Disable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 3 Interrupt Disable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 4 Interrupt Disable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 5 Interrupt Disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 6 Interrupt Disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIER</name>
<description>Host Global Interrupt Enable Register</description>
<addressOffset>0x0418</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DCONNIES</name>
<description>Device Connection Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDISCIES</name>
<description>Device Disconnection Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIES</name>
<description>USB Reset Sent Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSMEDIES</name>
<description>Downstream Resume Sent Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXRSMIES</name>
<description>Upstream Resume Received Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSOFIES</name>
<description>Host Start of Frame Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWUPIES</name>
<description>Host Wake-Up Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_0</name>
<description>Pipe 0 Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_1</name>
<description>Pipe 1 Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_2</name>
<description>Pipe 2 Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_3</name>
<description>Pipe 3 Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_4</name>
<description>Pipe 4 Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_5</name>
<description>Pipe 5 Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_6</name>
<description>Pipe 6 Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_7</name>
<description>Pipe 7 Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_8</name>
<description>Pipe 8 Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEP_9</name>
<description>Pipe 9 Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_1</name>
<description>DMA Channel 0 Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_2</name>
<description>DMA Channel 1 Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_3</name>
<description>DMA Channel 2 Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_4</name>
<description>DMA Channel 3 Interrupt Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_5</name>
<description>DMA Channel 4 Interrupt Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_6</name>
<description>DMA Channel 5 Interrupt Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_7</name>
<description>DMA Channel 6 Interrupt Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTPIP</name>
<description>Host Pipe Register</description>
<addressOffset>0x0041C</addressOffset>
<size>32</size>
<fields>
<field>
<name>PEN0</name>
<description>Pipe 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN1</name>
<description>Pipe 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN2</name>
<description>Pipe 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN3</name>
<description>Pipe 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN4</name>
<description>Pipe 4 Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN5</name>
<description>Pipe 5 Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN6</name>
<description>Pipe 6 Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN7</name>
<description>Pipe 7 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEN8</name>
<description>Pipe 8 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST0</name>
<description>Pipe 0 Reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST1</name>
<description>Pipe 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST2</name>
<description>Pipe 2 Reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST3</name>
<description>Pipe 3 Reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST4</name>
<description>Pipe 4 Reset</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST5</name>
<description>Pipe 5 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST6</name>
<description>Pipe 6 Reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST7</name>
<description>Pipe 7 Reset</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRST8</name>
<description>Pipe 8 Reset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTFNUM</name>
<description>Host Frame Number Register</description>
<addressOffset>0x0420</addressOffset>
<size>32</size>
<fields>
<field>
<name>MFNUM</name>
<description>Micro Frame Number</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FNUM</name>
<description>Frame Number</description>
<bitOffset>3</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>FLENHIGH</name>
<description>Frame Length</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTADDR1</name>
<description>Host Address 1 Register</description>
<addressOffset>0x0424</addressOffset>
<size>32</size>
<fields>
<field>
<name>HSTADDRP0</name>
<description>USB Host Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP1</name>
<description>USB Host Address</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP2</name>
<description>USB Host Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP3</name>
<description>USB Host Address</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTADDR2</name>
<description>Host Address 2 Register</description>
<addressOffset>0x0428</addressOffset>
<size>32</size>
<fields>
<field>
<name>HSTADDRP4</name>
<description>USB Host Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP5</name>
<description>USB Host Address</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP6</name>
<description>USB Host Address</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP7</name>
<description>USB Host Address</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTADDR3</name>
<description>Host Address 3 Register</description>
<addressOffset>0x042C</addressOffset>
<size>32</size>
<fields>
<field>
<name>HSTADDRP8</name>
<description>USB Host Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HSTADDRP9</name>
<description>USB Host Address</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPCFG[%s]</name>
<description>Host Pipe Configuration Register</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<fields>
<field>
<name>ALLOC</name>
<description>Pipe Memory Allocate</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBK</name>
<description>Pipe Banks</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PBKSelect</name>
<enumeratedValue>
<name>_1_BANK</name>
<description>Single-bank pipe</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BANK</name>
<description>Double-bank pipe</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BANK</name>
<description>Triple-bank pipe</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSIZE</name>
<description>Pipe Size</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>PSIZESelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8 bytes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16 bytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32 bytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64 bytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_128_BYTE</name>
<description>128 bytes</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_256_BYTE</name>
<description>256 bytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_512_BYTE</name>
<description>512 bytes</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024_BYTE</name>
<description>1024 bytes</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PTOKEN</name>
<description>Pipe Token</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PTOKENSelect</name>
<enumeratedValue>
<name>SETUP</name>
<description>SETUP</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>IN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT</name>
<description>OUT</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOSW</name>
<description>Automatic Switch</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTYPE</name>
<description>Pipe Type</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PTYPESelect</name>
<enumeratedValue>
<name>CTRL</name>
<description>Control</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO</name>
<description>Isochronous</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BLK</name>
<description>Bulk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INTRPT</name>
<description>Interrupt</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PEPNUM</name>
<description>Pipe Endpoint Number</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>INTFRQ</name>
<description>Pipe Interrupt Request Frequency</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPCFG_CTRL_BULK_MODE[%s]</name>
<description>Host Pipe Configuration Register</description>
<alternateRegister>HSTPIPCFG[%s]</alternateRegister>
<addressOffset>0x500</addressOffset>
<size>32</size>
<fields>
<field>
<name>ALLOC</name>
<description>Pipe Memory Allocate</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBK</name>
<description>Pipe Banks</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PBKSelect</name>
<enumeratedValue>
<name>_1_BANK</name>
<description>Single-bank pipe</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BANK</name>
<description>Double-bank pipe</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BANK</name>
<description>Triple-bank pipe</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSIZE</name>
<description>Pipe Size</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>PSIZESelect</name>
<enumeratedValue>
<name>_8_BYTE</name>
<description>8 bytes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_16_BYTE</name>
<description>16 bytes</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_32_BYTE</name>
<description>32 bytes</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_64_BYTE</name>
<description>64 bytes</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>_128_BYTE</name>
<description>128 bytes</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>_256_BYTE</name>
<description>256 bytes</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>_512_BYTE</name>
<description>512 bytes</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>_1024_BYTE</name>
<description>1024 bytes</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PTOKEN</name>
<description>Pipe Token</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PTOKENSelect</name>
<enumeratedValue>
<name>SETUP</name>
<description>SETUP</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>IN</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT</name>
<description>OUT</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOSW</name>
<description>Automatic Switch</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTYPE</name>
<description>Pipe Type</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>PTYPESelect</name>
<enumeratedValue>
<name>CTRL</name>
<description>Control</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO</name>
<description>Isochronous</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BLK</name>
<description>Bulk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INTRPT</name>
<description>Interrupt</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PEPNUM</name>
<description>Pipe Endpoint Number</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PINGEN</name>
<description>Ping Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BINTERVAL</name>
<description>bInterval Parameter for the Bulk-Out/Ping Transaction</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPISR_CTRL_MODE[%s]</name>
<description>Host Pipe Status Register</description>
<addressOffset>0x530</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINI</name>
<description>Received IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTI</name>
<description>Transmitted OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPI</name>
<description>Transmitted SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRI</name>
<description>Pipe Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDI</name>
<description>NAKed Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDI</name>
<description>Received STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETI</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBYCT</name>
<description>Pipe Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPISR_ISO_MODE[%s]</name>
<description>Host Pipe Status Register</description>
<alternateRegister>HSTPIPISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x530</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINI</name>
<description>Received IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTI</name>
<description>Transmitted OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFI</name>
<description>Underflow Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRI</name>
<description>Pipe Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDI</name>
<description>NAKed Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRI</name>
<description>CRC Error Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETI</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBYCT</name>
<description>Pipe Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPISR_BLK_MODE[%s]</name>
<description>Host Pipe Status Register</description>
<alternateRegister>HSTPIPISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x530</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINI</name>
<description>Received IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTI</name>
<description>Transmitted OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPI</name>
<description>Transmitted SETUP Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRI</name>
<description>Pipe Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDI</name>
<description>NAKed Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDI</name>
<description>Received STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETI</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBYCT</name>
<description>Pipe Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPISR_INTRPT_MODE[%s]</name>
<description>Host Pipe Status Register</description>
<alternateRegister>HSTPIPISR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x530</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINI</name>
<description>Received IN Data Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTI</name>
<description>Transmitted OUT Data Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFI</name>
<description>Underflow Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRI</name>
<description>Pipe Error Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDI</name>
<description>NAKed Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFI</name>
<description>Overflow Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDI</name>
<description>Received STALLed Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETI</name>
<description>Short Packet Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTSEQ</name>
<description>Data Toggle Sequence</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DTSEQSelect</name>
<enumeratedValue>
<name>DATA0</name>
<description>Data0 toggle sequence</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA1</name>
<description>Data1 toggle sequence</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBUSYBK</name>
<description>Number of Busy Banks</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NBUSYBKSelect</name>
<enumeratedValue>
<name>_0_BUSY</name>
<description>0 busy bank (all banks free)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>_1_BUSY</name>
<description>1 busy bank</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>_2_BUSY</name>
<description>2 busy banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>_3_BUSY</name>
<description>3 busy banks</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CURRBK</name>
<description>Current Bank</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CURRBKSelect</name>
<enumeratedValue>
<name>BANK0</name>
<description>Current bank is bank0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK1</name>
<description>Current bank is bank1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BANK2</name>
<description>Current bank is bank2</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWALL</name>
<description>Read/Write Allowed</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGOK</name>
<description>Configuration OK Status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBYCT</name>
<description>Pipe Byte Count</description>
<bitOffset>20</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPICR_CTRL_MODE[%s]</name>
<description>Host Pipe Clear Register</description>
<addressOffset>0x560</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIC</name>
<description>Received IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIC</name>
<description>Transmitted OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPIC</name>
<description>Transmitted SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIC</name>
<description>NAKed Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIC</name>
<description>Received STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPICR_ISO_MODE[%s]</name>
<description>Host Pipe Clear Register</description>
<alternateRegister>HSTPIPICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x560</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIC</name>
<description>Received IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIC</name>
<description>Transmitted OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIC</name>
<description>Underflow Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIC</name>
<description>NAKed Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRIC</name>
<description>CRC Error Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPICR_BLK_MODE[%s]</name>
<description>Host Pipe Clear Register</description>
<alternateRegister>HSTPIPICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x560</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIC</name>
<description>Received IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIC</name>
<description>Transmitted OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPIC</name>
<description>Transmitted SETUP Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIC</name>
<description>NAKed Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIC</name>
<description>Received STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPICR_INTRPT_MODE[%s]</name>
<description>Host Pipe Clear Register</description>
<alternateRegister>HSTPIPICR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x560</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIC</name>
<description>Received IN Data Interrupt Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIC</name>
<description>Transmitted OUT Data Interrupt Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIC</name>
<description>Underflow Interrupt Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIC</name>
<description>NAKed Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIC</name>
<description>Overflow Interrupt Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIC</name>
<description>Received STALLed Interrupt Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIC</name>
<description>Short Packet Interrupt Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIFR_CTRL_MODE[%s]</name>
<description>Host Pipe Set Register</description>
<addressOffset>0x590</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIS</name>
<description>Received IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIS</name>
<description>Transmitted OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPIS</name>
<description>Transmitted SETUP Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIS</name>
<description>Pipe Error Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIS</name>
<description>NAKed Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIS</name>
<description>Received STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIFR_ISO_MODE[%s]</name>
<description>Host Pipe Set Register</description>
<alternateRegister>HSTPIPIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x590</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIS</name>
<description>Received IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIS</name>
<description>Transmitted OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIS</name>
<description>Underflow Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIS</name>
<description>Pipe Error Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIS</name>
<description>NAKed Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRIS</name>
<description>CRC Error Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIFR_BLK_MODE[%s]</name>
<description>Host Pipe Set Register</description>
<alternateRegister>HSTPIPIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x590</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIS</name>
<description>Received IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIS</name>
<description>Transmitted OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPIS</name>
<description>Transmitted SETUP Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIS</name>
<description>Pipe Error Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIS</name>
<description>NAKed Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIS</name>
<description>Received STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIFR_INTRPT_MODE[%s]</name>
<description>Host Pipe Set Register</description>
<alternateRegister>HSTPIPIFR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x590</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINIS</name>
<description>Received IN Data Interrupt Set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTIS</name>
<description>Transmitted OUT Data Interrupt Set</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIS</name>
<description>Underflow Interrupt Set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIS</name>
<description>Pipe Error Interrupt Set</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDIS</name>
<description>NAKed Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIS</name>
<description>Overflow Interrupt Set</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDIS</name>
<description>Received STALLed Interrupt Set</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIS</name>
<description>Short Packet Interrupt Set</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKS</name>
<description>Number of Busy Banks Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIMR_CTRL_MODE[%s]</name>
<description>Host Pipe Mask Register</description>
<addressOffset>0x5C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINE</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTE</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPE</name>
<description>Transmitted SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRE</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDE</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIE</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDE</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIE</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMA</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZE</name>
<description>Pipe Freeze</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIMR_ISO_MODE[%s]</name>
<description>Host Pipe Mask Register</description>
<alternateRegister>HSTPIPIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINE</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTE</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIE</name>
<description>Underflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRE</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDE</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIE</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRE</name>
<description>CRC Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIE</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMA</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZE</name>
<description>Pipe Freeze</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIMR_BLK_MODE[%s]</name>
<description>Host Pipe Mask Register</description>
<alternateRegister>HSTPIPIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINE</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTE</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPE</name>
<description>Transmitted SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRE</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDE</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIE</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDE</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIE</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMA</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZE</name>
<description>Pipe Freeze</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIMR_INTRPT_MODE[%s]</name>
<description>Host Pipe Mask Register</description>
<alternateRegister>HSTPIPIMR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5C0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RXINE</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTE</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIE</name>
<description>Underflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRE</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDE</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIE</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDE</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIE</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKE</name>
<description>Number of Busy Banks Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCON</name>
<description>FIFO Control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMA</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZE</name>
<description>Pipe Freeze</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDT</name>
<description>Reset Data Toggle</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIER_CTRL_MODE[%s]</name>
<description>Host Pipe Enable Register</description>
<addressOffset>0x5F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINES</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTES</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPES</name>
<description>Transmitted SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRES</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDES</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDES</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAS</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZES</name>
<description>Pipe Freeze Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIER_ISO_MODE[%s]</name>
<description>Host Pipe Enable Register</description>
<alternateRegister>HSTPIPIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINES</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTES</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIES</name>
<description>Underflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRES</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDES</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERRES</name>
<description>CRC Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAS</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZES</name>
<description>Pipe Freeze Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIER_BLK_MODE[%s]</name>
<description>Host Pipe Enable Register</description>
<alternateRegister>HSTPIPIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINES</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTES</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPES</name>
<description>Transmitted SETUP Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRES</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDES</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDES</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAS</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZES</name>
<description>Pipe Freeze Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIER_INTRPT_MODE[%s]</name>
<description>Host Pipe Enable Register</description>
<alternateRegister>HSTPIPIER_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x5F0</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINES</name>
<description>Received IN Data Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTES</name>
<description>Transmitted OUT Data Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIES</name>
<description>Underflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRES</name>
<description>Pipe Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDES</name>
<description>NAKed Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIES</name>
<description>Overflow Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDES</name>
<description>Received STALLed Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIES</name>
<description>Short Packet Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKES</name>
<description>Number of Busy Banks Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAS</name>
<description>Pipe Interrupts Disable HDMA Request Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZES</name>
<description>Pipe Freeze Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDTS</name>
<description>Reset Data Toggle Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIDR_CTRL_MODE[%s]</name>
<description>Host Pipe Disable Register</description>
<addressOffset>0x620</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINEC</name>
<description>Received IN Data Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTEC</name>
<description>Transmitted OUT Data Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPEC</name>
<description>Transmitted SETUP Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERREC</name>
<description>Pipe Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDEC</name>
<description>NAKed Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIEC</name>
<description>Overflow Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDEC</name>
<description>Received STALLed Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIEC</name>
<description>Short Packet Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAC</name>
<description>Pipe Interrupts Disable HDMA Request Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZEC</name>
<description>Pipe Freeze Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIDR_ISO_MODE[%s]</name>
<description>Host Pipe Disable Register</description>
<alternateRegister>HSTPIPIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x620</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINEC</name>
<description>Received IN Data Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTEC</name>
<description>Transmitted OUT Data Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIEC</name>
<description>Underflow Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERREC</name>
<description>Pipe Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDEC</name>
<description>NAKed Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIEC</name>
<description>Overflow Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCERREC</name>
<description>CRC Error Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIEC</name>
<description>Short Packet Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAC</name>
<description>Pipe Interrupts Disable HDMA Request Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZEC</name>
<description>Pipe Freeze Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIDR_BLK_MODE[%s]</name>
<description>Host Pipe Disable Register</description>
<alternateRegister>HSTPIPIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x620</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINEC</name>
<description>Received IN Data Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTEC</name>
<description>Transmitted OUT Data Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSTPEC</name>
<description>Transmitted SETUP Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERREC</name>
<description>Pipe Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDEC</name>
<description>NAKed Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIEC</name>
<description>Overflow Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDEC</name>
<description>Received STALLed Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIEC</name>
<description>Short Packet Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAC</name>
<description>Pipe Interrupts Disable HDMA Request Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZEC</name>
<description>Pipe Freeze Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPIDR_INTRPT_MODE[%s]</name>
<description>Host Pipe Disable Register</description>
<alternateRegister>HSTPIPIDR_CTRL_MODE[%s]</alternateRegister>
<addressOffset>0x620</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RXINEC</name>
<description>Received IN Data Interrupt Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOUTEC</name>
<description>Transmitted OUT Data Interrupt Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDERFIEC</name>
<description>Underflow Interrupt Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERREC</name>
<description>Pipe Error Interrupt Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKEDEC</name>
<description>NAKed Interrupt Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVERFIEC</name>
<description>Overflow Interrupt Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTALLDEC</name>
<description>Received STALLed Interrupt Disable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHORTPACKETIEC</name>
<description>Short Packet Interrupt Disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBUSYBKEC</name>
<description>Number of Busy Banks Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOCONC</name>
<description>FIFO Control Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDISHDMAC</name>
<description>Pipe Interrupts Disable HDMA Request Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PFREEZEC</name>
<description>Pipe Freeze Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPINRQ[%s]</name>
<description>Host Pipe IN Request Register</description>
<addressOffset>0x650</addressOffset>
<size>32</size>
<fields>
<field>
<name>INRQ</name>
<description>IN Request Number before Freeze</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>INMODE</name>
<description>IN Request Mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>4</dimIncrement>
<name>HSTPIPERR[%s]</name>
<description>Host Pipe Error Register</description>
<addressOffset>0x680</addressOffset>
<size>32</size>
<fields>
<field>
<name>DATATGL</name>
<description>Data Toggle Error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAPID</name>
<description>Data PID Error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PID</name>
<description>Data PID Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUT</name>
<description>Time-Out Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC16</name>
<description>CRC16 Error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTER</name>
<description>Error Counter</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>7</dim>
<dimIncrement>16</dimIncrement>
<name>USBHS_HSTDMA[%s]</name>
<description>Host DMA Channel Next Descriptor Address Register</description>
<addressOffset>0x710</addressOffset>
<register>
<name>HSTDMANXTDSC</name>
<description>Host DMA Channel Next Descriptor Address Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<fields>
<field>
<name>NXT_DSC_ADD</name>
<description>Next Descriptor Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTDMAADDRESS</name>
<description>Host DMA Channel Address Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>BUFF_ADD</name>
<description>Buffer Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTDMACONTROL</name>
<description>Host DMA Channel Control Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHANN_ENB</name>
<description>Channel Enable Command</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDNXT_DSC</name>
<description>Load Next Channel Transfer Descriptor Enable Command</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_EN</name>
<description>End of Transfer Enable Control (OUT transfers only)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_B_EN</name>
<description>End of Buffer Enable Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_IT</name>
<description>End of Transfer Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_BUFFIT</name>
<description>End of Buffer Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DESC_LD_IT</name>
<description>Descriptor Loaded Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURST_LCK</name>
<description>Burst Lock Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUFF_LENGTH</name>
<description>Buffer Byte Length (Write-only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTDMASTATUS</name>
<description>Host DMA Channel Status Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<fields>
<field>
<name>CHANN_ENB</name>
<description>Channel Enable Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHANN_ACT</name>
<description>Channel Active Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_TR_ST</name>
<description>End of Channel Transfer Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_BF_ST</name>
<description>End of Channel Buffer Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DESC_LDST</name>
<description>Descriptor Loaded Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUFF_COUNT</name>
<description>Buffer Byte Count</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</cluster>
<register>
<name>CTRL</name>
<description>General Control Register</description>
<addressOffset>0x0800</addressOffset>
<size>32</size>
<fields>
<field>
<name>RDERRE</name>
<description>Remote Device Connection Error Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSHWC</name>
<description>VBUS Hardware Control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRZCLK</name>
<description>Freeze USB Clock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBE</name>
<description>USBHS Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UID</name>
<description>UID Pin Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIMOD</name>
<description>USBHS Mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UIMODSelect</name>
<enumeratedValue>
<name>HOST</name>
<description>The module is in USB Host mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEVICE</name>
<description>The module is in USB Device mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>General Status Register</description>
<addressOffset>0x0804</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>RDERRI</name>
<description>Remote Device Connection Error Interrupt (Host mode only)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPEED</name>
<description>Speed Status (Device mode only)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SPEEDSelect</name>
<enumeratedValue>
<name>FULL_SPEED</name>
<description>Full-Speed mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_SPEED</name>
<description>High-Speed mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_SPEED</name>
<description>Low-Speed mode</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKUSABLE</name>
<description>UTMI Clock Usable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>General Status Clear Register</description>
<addressOffset>0x0808</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDERRIC</name>
<description>Remote Device Connection Error Interrupt Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SFR</name>
<description>General Status Set Register</description>
<addressOffset>0x080C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RDERRIS</name>
<description>Remote Device Connection Error Interrupt Set</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSRQS</name>
<description>VBUS Request Set</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UTMI</name>
<version>11300A</version>
<description>USB Transmitter Interface Macrocell</description>
<groupName>UTMI</groupName>
<prependToName>UTMI_</prependToName>
<baseAddress>0x400E0400</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OHCIICR</name>
<description>OHCI Interrupt Configuration Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>RES0</name>
<description>USB PORTx Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARIE</name>
<description>OHCI Asynchronous Resume Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APPSTART</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPPUDIS</name>
<description>USB Device Pull-up Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKTRIM</name>
<description>UTMI Clock Trimming Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>FREQ</name>
<description>UTMI Reference Clock Frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>FREQSelect</name>
<enumeratedValue>
<name>XTAL12</name>
<description>12 MHz reference clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XTAL16</name>
<description>16 MHz reference clock</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDT</name>
<version>6080N</version>
<description>Watchdog Timer</description>
<groupName>WDT</groupName>
<prependToName>WDT_</prependToName>
<baseAddress>0x400E1850</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDT</name>
<value>4</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>WDRSTT</name>
<description>Watchdog Restart</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Password</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<name>KEYSelect</name>
<enumeratedValue>
<name>PASSWD</name>
<description>Writing any other value in this field aborts the write operation.</description>
<value>0xA5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>WDV</name>
<description>Watchdog Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WDFIEN</name>
<description>Watchdog Fault Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDRSTEN</name>
<description>Watchdog Reset Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDDIS</name>
<description>Watchdog Disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDD</name>
<description>Watchdog Delta Value</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WDDBGHLT</name>
<description>Watchdog Debug Halt</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIDLEHLT</name>
<description>Watchdog Idle Halt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>WDUNF</name>
<description>Watchdog Underflow (cleared on read)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDERR</name>
<description>Watchdog Error (cleared on read)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>XDMAC</name>
<version>11161K</version>
<description>Extensible DMA Controller</description>
<groupName>XDMAC</groupName>
<prependToName>XDMAC_</prependToName>
<baseAddress>0x40078000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE60</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>XDMAC</name>
<value>58</value>
</interrupt>
<registers>
<register>
<name>GTYPE</name>
<description>Global Type Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>NB_CH</name>
<description>Number of Channels Minus One</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>FIFO_SZ</name>
<description>Number of Bytes</description>
<bitOffset>5</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>NB_REQ</name>
<description>Number of Peripheral Requests Minus One</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>GCFG</name>
<description>Global Configuration Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<fields>
<field>
<name>CGDISREG</name>
<description>Configuration Registers Clock Gating Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGDISPIPE</name>
<description>Pipeline Clock Gating Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGDISFIFO</name>
<description>FIFO Clock Gating Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGDISIF</name>
<description>Bus Interface Clock Gating Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BXKBEN</name>
<description>Boundary X Kilobyte Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GWAC</name>
<description>Global Weighted Arbiter Configuration Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<fields>
<field>
<name>PW0</name>
<description>Pool Weight 0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PW1</name>
<description>Pool Weight 1</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PW2</name>
<description>Pool Weight 2</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PW3</name>
<description>Pool Weight 3</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GIE</name>
<description>Global Interrupt Enable Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>IE0</name>
<description>XDMAC Channel 0 Interrupt Enable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE1</name>
<description>XDMAC Channel 1 Interrupt Enable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE2</name>
<description>XDMAC Channel 2 Interrupt Enable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE3</name>
<description>XDMAC Channel 3 Interrupt Enable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE4</name>
<description>XDMAC Channel 4 Interrupt Enable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE5</name>
<description>XDMAC Channel 5 Interrupt Enable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE6</name>
<description>XDMAC Channel 6 Interrupt Enable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE7</name>
<description>XDMAC Channel 7 Interrupt Enable Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE8</name>
<description>XDMAC Channel 8 Interrupt Enable Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE9</name>
<description>XDMAC Channel 9 Interrupt Enable Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE10</name>
<description>XDMAC Channel 10 Interrupt Enable Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE11</name>
<description>XDMAC Channel 11 Interrupt Enable Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE12</name>
<description>XDMAC Channel 12 Interrupt Enable Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE13</name>
<description>XDMAC Channel 13 Interrupt Enable Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE14</name>
<description>XDMAC Channel 14 Interrupt Enable Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE15</name>
<description>XDMAC Channel 15 Interrupt Enable Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE16</name>
<description>XDMAC Channel 16 Interrupt Enable Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE17</name>
<description>XDMAC Channel 17 Interrupt Enable Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE18</name>
<description>XDMAC Channel 18 Interrupt Enable Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE19</name>
<description>XDMAC Channel 19 Interrupt Enable Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE20</name>
<description>XDMAC Channel 20 Interrupt Enable Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE21</name>
<description>XDMAC Channel 21 Interrupt Enable Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE22</name>
<description>XDMAC Channel 22 Interrupt Enable Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE23</name>
<description>XDMAC Channel 23 Interrupt Enable Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GID</name>
<description>Global Interrupt Disable Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>ID0</name>
<description>XDMAC Channel 0 Interrupt Disable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID1</name>
<description>XDMAC Channel 1 Interrupt Disable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID2</name>
<description>XDMAC Channel 2 Interrupt Disable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID3</name>
<description>XDMAC Channel 3 Interrupt Disable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID4</name>
<description>XDMAC Channel 4 Interrupt Disable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID5</name>
<description>XDMAC Channel 5 Interrupt Disable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID6</name>
<description>XDMAC Channel 6 Interrupt Disable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID7</name>
<description>XDMAC Channel 7 Interrupt Disable Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID8</name>
<description>XDMAC Channel 8 Interrupt Disable Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID9</name>
<description>XDMAC Channel 9 Interrupt Disable Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID10</name>
<description>XDMAC Channel 10 Interrupt Disable Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID11</name>
<description>XDMAC Channel 11 Interrupt Disable Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID12</name>
<description>XDMAC Channel 12 Interrupt Disable Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID13</name>
<description>XDMAC Channel 13 Interrupt Disable Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID14</name>
<description>XDMAC Channel 14 Interrupt Disable Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID15</name>
<description>XDMAC Channel 15 Interrupt Disable Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID16</name>
<description>XDMAC Channel 16 Interrupt Disable Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID17</name>
<description>XDMAC Channel 17 Interrupt Disable Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID18</name>
<description>XDMAC Channel 18 Interrupt Disable Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID19</name>
<description>XDMAC Channel 19 Interrupt Disable Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID20</name>
<description>XDMAC Channel 20 Interrupt Disable Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID21</name>
<description>XDMAC Channel 21 Interrupt Disable Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID22</name>
<description>XDMAC Channel 22 Interrupt Disable Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID23</name>
<description>XDMAC Channel 23 Interrupt Disable Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GIM</name>
<description>Global Interrupt Mask Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>IM0</name>
<description>XDMAC Channel 0 Interrupt Mask Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM1</name>
<description>XDMAC Channel 1 Interrupt Mask Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM2</name>
<description>XDMAC Channel 2 Interrupt Mask Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM3</name>
<description>XDMAC Channel 3 Interrupt Mask Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM4</name>
<description>XDMAC Channel 4 Interrupt Mask Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM5</name>
<description>XDMAC Channel 5 Interrupt Mask Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM6</name>
<description>XDMAC Channel 6 Interrupt Mask Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM7</name>
<description>XDMAC Channel 7 Interrupt Mask Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM8</name>
<description>XDMAC Channel 8 Interrupt Mask Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM9</name>
<description>XDMAC Channel 9 Interrupt Mask Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM10</name>
<description>XDMAC Channel 10 Interrupt Mask Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM11</name>
<description>XDMAC Channel 11 Interrupt Mask Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM12</name>
<description>XDMAC Channel 12 Interrupt Mask Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM13</name>
<description>XDMAC Channel 13 Interrupt Mask Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM14</name>
<description>XDMAC Channel 14 Interrupt Mask Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM15</name>
<description>XDMAC Channel 15 Interrupt Mask Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM16</name>
<description>XDMAC Channel 16 Interrupt Mask Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM17</name>
<description>XDMAC Channel 17 Interrupt Mask Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM18</name>
<description>XDMAC Channel 18 Interrupt Mask Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM19</name>
<description>XDMAC Channel 19 Interrupt Mask Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM20</name>
<description>XDMAC Channel 20 Interrupt Mask Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM21</name>
<description>XDMAC Channel 21 Interrupt Mask Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM22</name>
<description>XDMAC Channel 22 Interrupt Mask Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM23</name>
<description>XDMAC Channel 23 Interrupt Mask Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GIS</name>
<description>Global Interrupt Status Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>IS0</name>
<description>XDMAC Channel 0 Interrupt Status Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS1</name>
<description>XDMAC Channel 1 Interrupt Status Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS2</name>
<description>XDMAC Channel 2 Interrupt Status Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS3</name>
<description>XDMAC Channel 3 Interrupt Status Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS4</name>
<description>XDMAC Channel 4 Interrupt Status Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS5</name>
<description>XDMAC Channel 5 Interrupt Status Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS6</name>
<description>XDMAC Channel 6 Interrupt Status Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS7</name>
<description>XDMAC Channel 7 Interrupt Status Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS8</name>
<description>XDMAC Channel 8 Interrupt Status Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS9</name>
<description>XDMAC Channel 9 Interrupt Status Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS10</name>
<description>XDMAC Channel 10 Interrupt Status Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS11</name>
<description>XDMAC Channel 11 Interrupt Status Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS12</name>
<description>XDMAC Channel 12 Interrupt Status Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS13</name>
<description>XDMAC Channel 13 Interrupt Status Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS14</name>
<description>XDMAC Channel 14 Interrupt Status Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS15</name>
<description>XDMAC Channel 15 Interrupt Status Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS16</name>
<description>XDMAC Channel 16 Interrupt Status Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS17</name>
<description>XDMAC Channel 17 Interrupt Status Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS18</name>
<description>XDMAC Channel 18 Interrupt Status Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS19</name>
<description>XDMAC Channel 19 Interrupt Status Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS20</name>
<description>XDMAC Channel 20 Interrupt Status Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS21</name>
<description>XDMAC Channel 21 Interrupt Status Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS22</name>
<description>XDMAC Channel 22 Interrupt Status Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IS23</name>
<description>XDMAC Channel 23 Interrupt Status Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GE</name>
<description>Global Channel Enable Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>EN0</name>
<description>XDMAC Channel 0 Enable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN1</name>
<description>XDMAC Channel 1 Enable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN2</name>
<description>XDMAC Channel 2 Enable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN3</name>
<description>XDMAC Channel 3 Enable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN4</name>
<description>XDMAC Channel 4 Enable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN5</name>
<description>XDMAC Channel 5 Enable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN6</name>
<description>XDMAC Channel 6 Enable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN7</name>
<description>XDMAC Channel 7 Enable Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN8</name>
<description>XDMAC Channel 8 Enable Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN9</name>
<description>XDMAC Channel 9 Enable Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN10</name>
<description>XDMAC Channel 10 Enable Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN11</name>
<description>XDMAC Channel 11 Enable Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN12</name>
<description>XDMAC Channel 12 Enable Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN13</name>
<description>XDMAC Channel 13 Enable Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN14</name>
<description>XDMAC Channel 14 Enable Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN15</name>
<description>XDMAC Channel 15 Enable Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN16</name>
<description>XDMAC Channel 16 Enable Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN17</name>
<description>XDMAC Channel 17 Enable Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN18</name>
<description>XDMAC Channel 18 Enable Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN19</name>
<description>XDMAC Channel 19 Enable Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN20</name>
<description>XDMAC Channel 20 Enable Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN21</name>
<description>XDMAC Channel 21 Enable Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN22</name>
<description>XDMAC Channel 22 Enable Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN23</name>
<description>XDMAC Channel 23 Enable Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GD</name>
<description>Global Channel Disable Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>DI0</name>
<description>XDMAC Channel 0 Disable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI1</name>
<description>XDMAC Channel 1 Disable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI2</name>
<description>XDMAC Channel 2 Disable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI3</name>
<description>XDMAC Channel 3 Disable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI4</name>
<description>XDMAC Channel 4 Disable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI5</name>
<description>XDMAC Channel 5 Disable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI6</name>
<description>XDMAC Channel 6 Disable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI7</name>
<description>XDMAC Channel 7 Disable Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI8</name>
<description>XDMAC Channel 8 Disable Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI9</name>
<description>XDMAC Channel 9 Disable Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI10</name>
<description>XDMAC Channel 10 Disable Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI11</name>
<description>XDMAC Channel 11 Disable Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI12</name>
<description>XDMAC Channel 12 Disable Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI13</name>
<description>XDMAC Channel 13 Disable Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI14</name>
<description>XDMAC Channel 14 Disable Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI15</name>
<description>XDMAC Channel 15 Disable Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI16</name>
<description>XDMAC Channel 16 Disable Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI17</name>
<description>XDMAC Channel 17 Disable Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI18</name>
<description>XDMAC Channel 18 Disable Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI19</name>
<description>XDMAC Channel 19 Disable Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI20</name>
<description>XDMAC Channel 20 Disable Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI21</name>
<description>XDMAC Channel 21 Disable Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI22</name>
<description>XDMAC Channel 22 Disable Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DI23</name>
<description>XDMAC Channel 23 Disable Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GS</name>
<description>Global Channel Status Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>ST0</name>
<description>XDMAC Channel 0 Status Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST1</name>
<description>XDMAC Channel 1 Status Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST2</name>
<description>XDMAC Channel 2 Status Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST3</name>
<description>XDMAC Channel 3 Status Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST4</name>
<description>XDMAC Channel 4 Status Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST5</name>
<description>XDMAC Channel 5 Status Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST6</name>
<description>XDMAC Channel 6 Status Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST7</name>
<description>XDMAC Channel 7 Status Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST8</name>
<description>XDMAC Channel 8 Status Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST9</name>
<description>XDMAC Channel 9 Status Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST10</name>
<description>XDMAC Channel 10 Status Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST11</name>
<description>XDMAC Channel 11 Status Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST12</name>
<description>XDMAC Channel 12 Status Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST13</name>
<description>XDMAC Channel 13 Status Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST14</name>
<description>XDMAC Channel 14 Status Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST15</name>
<description>XDMAC Channel 15 Status Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST16</name>
<description>XDMAC Channel 16 Status Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST17</name>
<description>XDMAC Channel 17 Status Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST18</name>
<description>XDMAC Channel 18 Status Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST19</name>
<description>XDMAC Channel 19 Status Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST20</name>
<description>XDMAC Channel 20 Status Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST21</name>
<description>XDMAC Channel 21 Status Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST22</name>
<description>XDMAC Channel 22 Status Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST23</name>
<description>XDMAC Channel 23 Status Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRS</name>
<description>Global Channel Read Suspend Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<fields>
<field>
<name>RS0</name>
<description>XDMAC Channel 0 Read Suspend Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS1</name>
<description>XDMAC Channel 1 Read Suspend Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS2</name>
<description>XDMAC Channel 2 Read Suspend Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS3</name>
<description>XDMAC Channel 3 Read Suspend Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS4</name>
<description>XDMAC Channel 4 Read Suspend Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS5</name>
<description>XDMAC Channel 5 Read Suspend Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS6</name>
<description>XDMAC Channel 6 Read Suspend Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS7</name>
<description>XDMAC Channel 7 Read Suspend Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS8</name>
<description>XDMAC Channel 8 Read Suspend Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS9</name>
<description>XDMAC Channel 9 Read Suspend Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS10</name>
<description>XDMAC Channel 10 Read Suspend Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS11</name>
<description>XDMAC Channel 11 Read Suspend Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS12</name>
<description>XDMAC Channel 12 Read Suspend Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS13</name>
<description>XDMAC Channel 13 Read Suspend Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS14</name>
<description>XDMAC Channel 14 Read Suspend Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS15</name>
<description>XDMAC Channel 15 Read Suspend Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS16</name>
<description>XDMAC Channel 16 Read Suspend Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS17</name>
<description>XDMAC Channel 17 Read Suspend Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS18</name>
<description>XDMAC Channel 18 Read Suspend Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS19</name>
<description>XDMAC Channel 19 Read Suspend Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS20</name>
<description>XDMAC Channel 20 Read Suspend Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS21</name>
<description>XDMAC Channel 21 Read Suspend Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS22</name>
<description>XDMAC Channel 22 Read Suspend Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS23</name>
<description>XDMAC Channel 23 Read Suspend Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GWS</name>
<description>Global Channel Write Suspend Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<fields>
<field>
<name>WS0</name>
<description>XDMAC Channel 0 Write Suspend Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS1</name>
<description>XDMAC Channel 1 Write Suspend Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS2</name>
<description>XDMAC Channel 2 Write Suspend Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS3</name>
<description>XDMAC Channel 3 Write Suspend Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS4</name>
<description>XDMAC Channel 4 Write Suspend Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS5</name>
<description>XDMAC Channel 5 Write Suspend Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS6</name>
<description>XDMAC Channel 6 Write Suspend Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS7</name>
<description>XDMAC Channel 7 Write Suspend Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS8</name>
<description>XDMAC Channel 8 Write Suspend Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS9</name>
<description>XDMAC Channel 9 Write Suspend Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS10</name>
<description>XDMAC Channel 10 Write Suspend Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS11</name>
<description>XDMAC Channel 11 Write Suspend Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS12</name>
<description>XDMAC Channel 12 Write Suspend Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS13</name>
<description>XDMAC Channel 13 Write Suspend Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS14</name>
<description>XDMAC Channel 14 Write Suspend Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS15</name>
<description>XDMAC Channel 15 Write Suspend Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS16</name>
<description>XDMAC Channel 16 Write Suspend Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS17</name>
<description>XDMAC Channel 17 Write Suspend Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS18</name>
<description>XDMAC Channel 18 Write Suspend Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS19</name>
<description>XDMAC Channel 19 Write Suspend Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS20</name>
<description>XDMAC Channel 20 Write Suspend Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS21</name>
<description>XDMAC Channel 21 Write Suspend Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS22</name>
<description>XDMAC Channel 22 Write Suspend Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WS23</name>
<description>XDMAC Channel 23 Write Suspend Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRWS</name>
<description>Global Channel Read Write Suspend Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RWS0</name>
<description>XDMAC Channel 0 Read Write Suspend Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS1</name>
<description>XDMAC Channel 1 Read Write Suspend Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS2</name>
<description>XDMAC Channel 2 Read Write Suspend Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS3</name>
<description>XDMAC Channel 3 Read Write Suspend Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS4</name>
<description>XDMAC Channel 4 Read Write Suspend Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS5</name>
<description>XDMAC Channel 5 Read Write Suspend Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS6</name>
<description>XDMAC Channel 6 Read Write Suspend Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS7</name>
<description>XDMAC Channel 7 Read Write Suspend Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS8</name>
<description>XDMAC Channel 8 Read Write Suspend Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS9</name>
<description>XDMAC Channel 9 Read Write Suspend Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS10</name>
<description>XDMAC Channel 10 Read Write Suspend Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS11</name>
<description>XDMAC Channel 11 Read Write Suspend Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS12</name>
<description>XDMAC Channel 12 Read Write Suspend Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS13</name>
<description>XDMAC Channel 13 Read Write Suspend Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS14</name>
<description>XDMAC Channel 14 Read Write Suspend Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS15</name>
<description>XDMAC Channel 15 Read Write Suspend Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS16</name>
<description>XDMAC Channel 16 Read Write Suspend Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS17</name>
<description>XDMAC Channel 17 Read Write Suspend Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS18</name>
<description>XDMAC Channel 18 Read Write Suspend Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS19</name>
<description>XDMAC Channel 19 Read Write Suspend Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS20</name>
<description>XDMAC Channel 20 Read Write Suspend Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS21</name>
<description>XDMAC Channel 21 Read Write Suspend Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS22</name>
<description>XDMAC Channel 22 Read Write Suspend Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWS23</name>
<description>XDMAC Channel 23 Read Write Suspend Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRWR</name>
<description>Global Channel Read Write Resume Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>RWR0</name>
<description>XDMAC Channel 0 Read Write Resume Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR1</name>
<description>XDMAC Channel 1 Read Write Resume Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR2</name>
<description>XDMAC Channel 2 Read Write Resume Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR3</name>
<description>XDMAC Channel 3 Read Write Resume Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR4</name>
<description>XDMAC Channel 4 Read Write Resume Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR5</name>
<description>XDMAC Channel 5 Read Write Resume Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR6</name>
<description>XDMAC Channel 6 Read Write Resume Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR7</name>
<description>XDMAC Channel 7 Read Write Resume Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR8</name>
<description>XDMAC Channel 8 Read Write Resume Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR9</name>
<description>XDMAC Channel 9 Read Write Resume Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR10</name>
<description>XDMAC Channel 10 Read Write Resume Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR11</name>
<description>XDMAC Channel 11 Read Write Resume Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR12</name>
<description>XDMAC Channel 12 Read Write Resume Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR13</name>
<description>XDMAC Channel 13 Read Write Resume Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR14</name>
<description>XDMAC Channel 14 Read Write Resume Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR15</name>
<description>XDMAC Channel 15 Read Write Resume Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR16</name>
<description>XDMAC Channel 16 Read Write Resume Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR17</name>
<description>XDMAC Channel 17 Read Write Resume Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR18</name>
<description>XDMAC Channel 18 Read Write Resume Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR19</name>
<description>XDMAC Channel 19 Read Write Resume Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR20</name>
<description>XDMAC Channel 20 Read Write Resume Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR21</name>
<description>XDMAC Channel 21 Read Write Resume Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR22</name>
<description>XDMAC Channel 22 Read Write Resume Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWR23</name>
<description>XDMAC Channel 23 Read Write Resume Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GSWR</name>
<description>Global Channel Software Request Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SWREQ0</name>
<description>XDMAC Channel 0 Software Request Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ1</name>
<description>XDMAC Channel 1 Software Request Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ2</name>
<description>XDMAC Channel 2 Software Request Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ3</name>
<description>XDMAC Channel 3 Software Request Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ4</name>
<description>XDMAC Channel 4 Software Request Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ5</name>
<description>XDMAC Channel 5 Software Request Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ6</name>
<description>XDMAC Channel 6 Software Request Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ7</name>
<description>XDMAC Channel 7 Software Request Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ8</name>
<description>XDMAC Channel 8 Software Request Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ9</name>
<description>XDMAC Channel 9 Software Request Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ10</name>
<description>XDMAC Channel 10 Software Request Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ11</name>
<description>XDMAC Channel 11 Software Request Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ12</name>
<description>XDMAC Channel 12 Software Request Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ13</name>
<description>XDMAC Channel 13 Software Request Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ14</name>
<description>XDMAC Channel 14 Software Request Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ15</name>
<description>XDMAC Channel 15 Software Request Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ16</name>
<description>XDMAC Channel 16 Software Request Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ17</name>
<description>XDMAC Channel 17 Software Request Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ18</name>
<description>XDMAC Channel 18 Software Request Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ19</name>
<description>XDMAC Channel 19 Software Request Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ20</name>
<description>XDMAC Channel 20 Software Request Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ21</name>
<description>XDMAC Channel 21 Software Request Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ22</name>
<description>XDMAC Channel 22 Software Request Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWREQ23</name>
<description>XDMAC Channel 23 Software Request Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GSWS</name>
<description>Global Channel Software Request Status Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>SWRS0</name>
<description>XDMAC Channel 0 Software Request Status Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS1</name>
<description>XDMAC Channel 1 Software Request Status Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS2</name>
<description>XDMAC Channel 2 Software Request Status Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS3</name>
<description>XDMAC Channel 3 Software Request Status Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS4</name>
<description>XDMAC Channel 4 Software Request Status Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS5</name>
<description>XDMAC Channel 5 Software Request Status Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS6</name>
<description>XDMAC Channel 6 Software Request Status Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS7</name>
<description>XDMAC Channel 7 Software Request Status Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS8</name>
<description>XDMAC Channel 8 Software Request Status Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS9</name>
<description>XDMAC Channel 9 Software Request Status Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS10</name>
<description>XDMAC Channel 10 Software Request Status Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS11</name>
<description>XDMAC Channel 11 Software Request Status Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS12</name>
<description>XDMAC Channel 12 Software Request Status Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS13</name>
<description>XDMAC Channel 13 Software Request Status Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS14</name>
<description>XDMAC Channel 14 Software Request Status Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS15</name>
<description>XDMAC Channel 15 Software Request Status Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS16</name>
<description>XDMAC Channel 16 Software Request Status Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS17</name>
<description>XDMAC Channel 17 Software Request Status Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS18</name>
<description>XDMAC Channel 18 Software Request Status Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS19</name>
<description>XDMAC Channel 19 Software Request Status Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS20</name>
<description>XDMAC Channel 20 Software Request Status Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS21</name>
<description>XDMAC Channel 21 Software Request Status Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS22</name>
<description>XDMAC Channel 22 Software Request Status Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRS23</name>
<description>XDMAC Channel 23 Software Request Status Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GSWF</name>
<description>Global Channel Software Flush Request Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>SWF0</name>
<description>XDMAC Channel 0 Software Flush Request Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF1</name>
<description>XDMAC Channel 1 Software Flush Request Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF2</name>
<description>XDMAC Channel 2 Software Flush Request Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF3</name>
<description>XDMAC Channel 3 Software Flush Request Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF4</name>
<description>XDMAC Channel 4 Software Flush Request Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF5</name>
<description>XDMAC Channel 5 Software Flush Request Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF6</name>
<description>XDMAC Channel 6 Software Flush Request Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF7</name>
<description>XDMAC Channel 7 Software Flush Request Bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF8</name>
<description>XDMAC Channel 8 Software Flush Request Bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF9</name>
<description>XDMAC Channel 9 Software Flush Request Bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF10</name>
<description>XDMAC Channel 10 Software Flush Request Bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF11</name>
<description>XDMAC Channel 11 Software Flush Request Bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF12</name>
<description>XDMAC Channel 12 Software Flush Request Bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF13</name>
<description>XDMAC Channel 13 Software Flush Request Bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF14</name>
<description>XDMAC Channel 14 Software Flush Request Bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF15</name>
<description>XDMAC Channel 15 Software Flush Request Bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF16</name>
<description>XDMAC Channel 16 Software Flush Request Bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF17</name>
<description>XDMAC Channel 17 Software Flush Request Bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF18</name>
<description>XDMAC Channel 18 Software Flush Request Bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF19</name>
<description>XDMAC Channel 19 Software Flush Request Bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF20</name>
<description>XDMAC Channel 20 Software Flush Request Bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF21</name>
<description>XDMAC Channel 21 Software Flush Request Bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF22</name>
<description>XDMAC Channel 22 Software Flush Request Bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWF23</name>
<description>XDMAC Channel 23 Software Flush Request Bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>24</dim>
<dimIncrement>64</dimIncrement>
<name>XDMAC_CHID[%s]</name>
<description>Channel Interrupt Enable Register</description>
<addressOffset>0x50</addressOffset>
<register>
<name>CIE</name>
<description>Channel Interrupt Enable Register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>BIE</name>
<description>End of Block Interrupt Enable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIE</name>
<description>End of Linked List Interrupt Enable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIE</name>
<description>End of Disable Interrupt Enable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIE</name>
<description>End of Flush Interrupt Enable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBIE</name>
<description>Read Bus Error Interrupt Enable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBIE</name>
<description>Write Bus Error Interrupt Enable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROIE</name>
<description>Request Overflow Error Interrupt Enable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CID</name>
<description>Channel Interrupt Disable Register</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field>
<name>BID</name>
<description>End of Block Interrupt Disable Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LID</name>
<description>End of Linked List Interrupt Disable Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DID</name>
<description>End of Disable Interrupt Disable Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FID</name>
<description>End of Flush Interrupt Disable Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBEID</name>
<description>Read Bus Error Interrupt Disable Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBEID</name>
<description>Write Bus Error Interrupt Disable Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROID</name>
<description>Request Overflow Error Interrupt Disable Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIM</name>
<description>Channel Interrupt Mask Register</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>BIM</name>
<description>End of Block Interrupt Mask Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIM</name>
<description>End of Linked List Interrupt Mask Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIM</name>
<description>End of Disable Interrupt Mask Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIM</name>
<description>End of Flush Interrupt Mask Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBEIM</name>
<description>Read Bus Error Interrupt Mask Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBEIM</name>
<description>Write Bus Error Interrupt Mask Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROIM</name>
<description>Request Overflow Error Interrupt Mask Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS</name>
<description>Channel Interrupt Status Register</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field>
<name>BIS</name>
<description>End of Block Interrupt Status Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIS</name>
<description>End of Linked List Interrupt Status Bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS</name>
<description>End of Disable Interrupt Status Bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIS</name>
<description>End of Flush Interrupt Status Bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBEIS</name>
<description>Read Bus Error Interrupt Status Bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBEIS</name>
<description>Write Bus Error Interrupt Status Bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROIS</name>
<description>Request Overflow Error Interrupt Status Bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSA</name>
<description>Channel Source Address Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<fields>
<field>
<name>SA</name>
<description>Channel x Source Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDA</name>
<description>Channel Destination Address Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<fields>
<field>
<name>DA</name>
<description>Channel x Destination Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDA</name>
<description>Channel Next Descriptor Address Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<fields>
<field>
<name>NDAIF</name>
<description>Channel x Next Descriptor Interface</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NDA</name>
<description>Channel x Next Descriptor Address</description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDC</name>
<description>Channel Next Descriptor Control Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<fields>
<field>
<name>NDE</name>
<description>Channel x Next Descriptor Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NDESelect</name>
<enumeratedValue>
<name>DSCR_FETCH_DIS</name>
<description>Descriptor fetch is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DSCR_FETCH_EN</name>
<description>Descriptor fetch is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NDSUP</name>
<description>Channel x Next Descriptor Source Update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NDSUPSelect</name>
<enumeratedValue>
<name>SRC_PARAMS_UNCHANGED</name>
<description>Source parameters remain unchanged.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SRC_PARAMS_UPDATED</name>
<description>Source parameters are updated when the descriptor is retrieved.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NDDUP</name>
<description>Channel x Next Descriptor Destination Update</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NDDUPSelect</name>
<enumeratedValue>
<name>DST_PARAMS_UNCHANGED</name>
<description>Destination parameters remain unchanged.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DST_PARAMS_UPDATED</name>
<description>Destination parameters are updated when the descriptor is retrieved.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NDVIEW</name>
<description>Channel x Next Descriptor View</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>NDVIEWSelect</name>
<enumeratedValue>
<name>NDV0</name>
<description>Next Descriptor View 0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NDV1</name>
<description>Next Descriptor View 1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>NDV2</name>
<description>Next Descriptor View 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NDV3</name>
<description>Next Descriptor View 3</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CUBC</name>
<description>Channel Microblock Control Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<fields>
<field>
<name>UBLEN</name>
<description>Channel x Microblock Length</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CBC</name>
<description>Channel Block Control Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<fields>
<field>
<name>BLEN</name>
<description>Channel x Block Length</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>CC</name>
<description>Channel Configuration Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<fields>
<field>
<name>TYPE</name>
<description>Channel x Transfer Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TYPESelect</name>
<enumeratedValue>
<name>MEM_TRAN</name>
<description>Self-triggered mode (memory-to-memory transfer).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PER_TRAN</name>
<description>Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MBSIZE</name>
<description>Channel x Memory Burst Size</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>MBSIZESelect</name>
<enumeratedValue>
<name>SINGLE</name>
<description>The memory burst size is set to one.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>The memory burst size is set to four.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EIGHT</name>
<description>The memory burst size is set to eight.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SIXTEEN</name>
<description>The memory burst size is set to sixteen.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSYNC</name>
<description>Channel x Synchronization</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DSYNCSelect</name>
<enumeratedValue>
<name>PER2MEM</name>
<description>Peripheral-to-memory transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MEM2PER</name>
<description>Memory-to-peripheral transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWREQ</name>
<description>Channel x Software Request Trigger</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SWREQSelect</name>
<enumeratedValue>
<name>HWR_CONNECTED</name>
<description>Hardware request line is connected to the peripheral request line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SWR_CONNECTED</name>
<description>Software request is connected to the peripheral request line.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEMSET</name>
<description>Channel x Fill Block of memory</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MEMSETSelect</name>
<enumeratedValue>
<name>NORMAL_MODE</name>
<description>Memset is not activated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HW_MODE</name>
<description>Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIZE</name>
<description>Channel x Chunk Size</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>CSIZESelect</name>
<enumeratedValue>
<name>CHK_1</name>
<description>1 data transferred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CHK_2</name>
<description>2 data transferred</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CHK_4</name>
<description>4 data transferred</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CHK_8</name>
<description>8 data transferred</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CHK_16</name>
<description>16 data transferred</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DWIDTH</name>
<description>Channel x Data Width</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DWIDTHSelect</name>
<enumeratedValue>
<name>BYTE</name>
<description>The data size is set to 8 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALFWORD</name>
<description>The data size is set to 16 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WORD</name>
<description>The data size is set to 32 bits</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIF</name>
<description>Channel x Source Interface Identifier</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SIFSelect</name>
<enumeratedValue>
<name>AHB_IF0</name>
<description>The data is read through the system bus interface 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AHB_IF1</name>
<description>The data is read through the system bus interface 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIF</name>
<description>Channel x Destination Interface Identifier</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIFSelect</name>
<enumeratedValue>
<name>AHB_IF0</name>
<description>The data is written through the system bus interface 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AHB_IF1</name>
<description>The data is written though the system bus interface 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAM</name>
<description>Channel x Source Addressing Mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SAMSelect</name>
<enumeratedValue>
<name>FIXED_AM</name>
<description>The address remains unchanged.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INCREMENTED_AM</name>
<description>The addressing mode is incremented (the increment size is set to the data size).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>UBS_AM</name>
<description>The microblock stride is added at the microblock boundary.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UBS_DS_AM</name>
<description>The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAM</name>
<description>Channel x Destination Addressing Mode</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>DAMSelect</name>
<enumeratedValue>
<name>FIXED_AM</name>
<description>The address remains unchanged.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>INCREMENTED_AM</name>
<description>The addressing mode is incremented (the increment size is set to the data size).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>UBS_AM</name>
<description>The microblock stride is added at the microblock boundary.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>UBS_DS_AM</name>
<description>The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITD</name>
<description>Channel Initialization Terminated (this bit is read-only)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INITDSelect</name>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>Channel initialization is in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TERMINATED</name>
<description>Channel initialization is completed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDIP</name>
<description>Read in Progress (this bit is read-only)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RDIPSelect</name>
<enumeratedValue>
<name>DONE</name>
<description>No active read transaction on the bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>A read transaction is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WRIP</name>
<description>Write in Progress (this bit is read-only)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>WRIPSelect</name>
<enumeratedValue>
<name>DONE</name>
<description>No active write transaction on the bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>A write transaction is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PERID</name>
<description>Channel x Peripheral Hardware Request Line Identifier</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<enumeratedValues>
<name>PERIDSelect</name>
<enumeratedValue>
<name>HSMCI</name>
<description>HSMCI</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_TX</name>
<description>SPI0_TX</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_RX</name>
<description>SPI0_RX</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>QSPI_TX</name>
<description>QSPI_TX</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>QSPI_RX</name>
<description>QSPI_RX</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_TX</name>
<description>USART0_TX</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_RX</name>
<description>USART0_RX</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>USART1_TX</name>
<description>USART1_TX</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>USART1_RX</name>
<description>USART1_RX</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>USART2_TX</name>
<description>USART2_TX</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>USART2_RX</name>
<description>USART2_RX</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM0</name>
<description>PWM0</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS0_TX</name>
<description>TWIHS0_TX</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS0_RX</name>
<description>TWIHS0_RX</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS1_TX</name>
<description>TWIHS1_TX</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS1_RX</name>
<description>TWIHS1_RX</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS2_TX</name>
<description>TWIHS2_TX</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>TWIHS2_RX</name>
<description>TWIHS2_RX</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>UART0_TX</name>
<description>UART0_TX</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>UART0_RX</name>
<description>UART0_RX</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>UART1_TX</name>
<description>UART1_TX</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>UART1_RX</name>
<description>UART1_RX</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>UART2_TX</name>
<description>UART2_TX</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>UART2_RX</name>
<description>UART2_RX</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>UART3_TX</name>
<description>UART3_TX</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>UART3_RX</name>
<description>UART3_RX</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>UART4_TX</name>
<description>UART4_TX</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>UART4_RX</name>
<description>UART4_RX</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>DACC0</name>
<description>DACC0</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>DACC1</name>
<description>DACC1</description>
<value>31</value>
</enumeratedValue>
<enumeratedValue>
<name>SSC_TX</name>
<description>SSC_TX</description>
<value>32</value>
</enumeratedValue>
<enumeratedValue>
<name>SSC_RX</name>
<description>SSC_RX</description>
<value>33</value>
</enumeratedValue>
<enumeratedValue>
<name>PIOA</name>
<description>PIOA</description>
<value>34</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC0</name>
<description>AFEC0</description>
<value>35</value>
</enumeratedValue>
<enumeratedValue>
<name>AFEC1</name>
<description>AFEC1</description>
<value>36</value>
</enumeratedValue>
<enumeratedValue>
<name>AES_TX</name>
<description>AES_TX</description>
<value>37</value>
</enumeratedValue>
<enumeratedValue>
<name>AES_RX</name>
<description>AES_RX</description>
<value>38</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM1</name>
<description>PWM1</description>
<value>39</value>
</enumeratedValue>
<enumeratedValue>
<name>TC0</name>
<description>TC0</description>
<value>40</value>
</enumeratedValue>
<enumeratedValue>
<name>TC3</name>
<description>TC3</description>
<value>41</value>
</enumeratedValue>
<enumeratedValue>
<name>TC6</name>
<description>TC6</description>
<value>42</value>
</enumeratedValue>
<enumeratedValue>
<name>TC9</name>
<description>TC9</description>
<value>43</value>
</enumeratedValue>
<enumeratedValue>
<name>I2SC0_TX_LEFT</name>
<description>I2SC0_TX_LEFT</description>
<value>44</value>
</enumeratedValue>
<enumeratedValue>
<name>I2SC0_RX_LEFT</name>
<description>I2SC0_RX_LEFT</description>
<value>45</value>
</enumeratedValue>
<enumeratedValue>
<name>I2SC0_TX_RIGHT</name>
<description>I2SC0_TX_RIGHT</description>
<value>48</value>
</enumeratedValue>
<enumeratedValue>
<name>I2SC0_RX_RIGHT</name>
<description>I2SC0_RX_RIGHT</description>
<value>49</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CDS_MSP</name>
<description>Channel Data Stride Memory Set Pattern</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<fields>
<field>
<name>SDS_MSP</name>
<description>Channel x Source Data stride or Memory Set Pattern</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DDS_MSP</name>
<description>Channel x Destination Data Stride or Memory Set Pattern</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSUS</name>
<description>Channel Source Microblock Stride</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<fields>
<field>
<name>SUBS</name>
<description>Channel x Source Microblock Stride</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDUS</name>
<description>Channel Destination Microblock Stride</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<fields>
<field>
<name>DUBS</name>
<description>Channel x Destination Microblock Stride</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>LOCKBIT</name>
<groupName>LOCKBIT</groupName>
<prependToName>LOCKBIT_</prependToName>
<baseAddress>0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>WORD0</name>
<description>Lock Bits Word 0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<fields>
<field>
<name>LOCK_REGION_0</name>
<description>Lock Region 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_1</name>
<description>Lock Region 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_2</name>
<description>Lock Region 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_3</name>
<description>Lock Region 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_4</name>
<description>Lock Region 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_5</name>
<description>Lock Region 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_6</name>
<description>Lock Region 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_7</name>
<description>Lock Region 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_8</name>
<description>Lock Region 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_9</name>
<description>Lock Region 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_10</name>
<description>Lock Region 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_11</name>
<description>Lock Region 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_12</name>
<description>Lock Region 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_13</name>
<description>Lock Region 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_14</name>
<description>Lock Region 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_15</name>
<description>Lock Region 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_16</name>
<description>Lock Region 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_17</name>
<description>Lock Region 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_18</name>
<description>Lock Region 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_19</name>
<description>Lock Region 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_20</name>
<description>Lock Region 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_21</name>
<description>Lock Region 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_22</name>
<description>Lock Region 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_23</name>
<description>Lock Region 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_24</name>
<description>Lock Region 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_25</name>
<description>Lock Region 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_26</name>
<description>Lock Region 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_27</name>
<description>Lock Region 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_28</name>
<description>Lock Region 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_29</name>
<description>Lock Region 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_30</name>
<description>Lock Region 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK_REGION_31</name>
<description>Lock Region 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCnSCB</name>
<description>System control not in SCB</description>
<groupName>SCnSCB</groupName>
<prependToName>SCnSCB_</prependToName>
<baseAddress>0xE000E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ICTR</name>
<description>Interrupt Controller Type Register</description>
<addressOffset>0x00000004</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>INTLINESNUM</name>
<description>Total number of interrupt lines supported by an implementation, defined in groups of 32</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACTLR</name>
<description>Auxiliary Control Register</description>
<addressOffset>0x00000008</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>DISFOLD</name>
<description>Disables folding of IT instructions</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPEXCODIS</name>
<description>Disables FPU exception outputs</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISRAMODE</name>
<description>Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISITMATBFLUSH</name>
<description>Disables ITM and DWT ATB flush</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISBTACREAD</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISBTACALLOC</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCRITAXIRUR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISDI</name>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DISISSCH1</name>
<bitOffset>21</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DISDYNADD</name>
<description>Disables dynamic allocation of ADD and SUB instructions</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCRITAXIRUW</name>
<description>Disable critical AXI read-under-write</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFPUISSOPT</name>
<description>Disables dynamic allocation of ADD and SUB instructions</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB</name>
<description>System Control Block</description>
<groupName>SCB</groupName>
<prependToName>SCB_</prependToName>
<baseAddress>0xE000ED00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x24C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CCW</name>
<value>64</value>
</interrupt>
<interrupt>
<name>CCF</name>
<value>65</value>
</interrupt>
<registers>
<register>
<name>CPUID</name>
<description>CPUID Base Register</description>
<addressOffset>0x00000000</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x411FC271</resetValue>
<fields>
<field>
<name>REVISION</name>
<description>Indicates patch release: 0x0 = Patch 0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PARTNO</name>
<description>Indicates part number</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>ARCHITECTURE</name>
<description>Indicates architecture. Reads as 0xF</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VARIANT</name>
<description>Indicates processor revision: 0x2 = Revision 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IMPLEMENTER</name>
<description>Implementer code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<description>Interrupt Control and State Register</description>
<addressOffset>0x00000004</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Active exception number</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RETTOBASE</name>
<description>Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>RETTOBASESelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>there are preempted active exceptions to execute</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>there are no active exceptions, or the currently-executing exception is the only active exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTPENDING</name>
<description>Exception number of the highest priority pending enabled exception</description>
<bitOffset>12</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>ISRPENDING</name>
<description>Is external interrupt, generated by the NVIC, pending</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISRPREEMPT</name>
<description>Indicates whether a pending exception will be serviced on exit from debug halt state</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ISRPREEMPTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>Will not service</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>Will service a pending exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PENDSTCLR</name>
<description>Removes the pending status of the SysTick exception</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PENDSTCLRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>removes the pending state from the SysTick exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PENDSTSET</name>
<description>Sets the SysTick exception as pending, or reads the current state of the exception</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PENDSTSETSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>write: no effect; read: SysTick exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PENDSVCLR</name>
<description>Removes the pending status of the PendSV exception</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PENDSVCLRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>removes the pending state from the PendSV exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PENDSVSET</name>
<description>Sets the PendSV exception as pending, or reads the current state of the exception</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PENDSVSETSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>write: no effect; read: PendSV exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NMIPENDSET</name>
<description>Makes the NMI exception active, or reads the state of the exception</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NMIPENDSETSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>write: no effect; read: NMI exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>write: changes NMI exception state to pending; read: NMI exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>VTOR</name>
<description>Vector Table Offset Register</description>
<addressOffset>0x00000008</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>TBLOFF</name>
<description>Bits[31:7] of the vector table address</description>
<bitOffset>7</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<description>Application Interrupt and Reset Control Register</description>
<addressOffset>0x0000000c</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>VECTRESET</name>
<description>Writing 1 to this bit causes a local system reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTCLRACTIVE</name>
<description>Clears all active state information for fixed and configurable exceptions</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSRESETREQ</name>
<description>System Reset Request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SYSRESETREQSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no system reset request</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>asserts a signal to the outer system that requests a reset</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRIGROUP</name>
<description>Interrupt priority grouping field. This field determines the split of group priority from subpriority.</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ENDIANNESS</name>
<description>Memory system endianness</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ENDIANNESSSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>Little-endian</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>Big-endian</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEY</name>
<description>Vector key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>System Control Register</description>
<addressOffset>0x00000010</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SLEEPONEXITSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>o not sleep when returning to Thread mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enter sleep, or deep sleep, on return from an ISR</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEEPDEEP</name>
<description>Provides a qualifying hint indicating that waking from sleep might take longer</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SLEEPDEEPSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>sleep</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>deep sleep</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEVONPEND</name>
<description>Determines whether an interrupt transition from inactive state to pending state is a wakeup event</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SEVONPENDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Configuration and Control Register</description>
<addressOffset>0x00000014</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>NONBASETHRDENA</name>
<description>Controls whether the processor can enter Thread mode with exceptions active</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NONBASETHRDENASelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>processor can enter Thread mode only when no exception is active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>processor can enter Thread mode from any level under the control of an EXC_RETURN value</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USERSETMPEND</name>
<description>Enables unprivileged software access to the STIR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>USERSETMPENDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UNALIGN_TRP</name>
<description>Enables unaligned access traps</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UNALIGN_TRPSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>do not trap unaligned halfword and word accesses</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>trap unaligned halfword and word accesses</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIV_0_TRP</name>
<description>Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIV_0_TRPSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>do not trap divide by 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>trap divide by 0</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BFHFNMIGN</name>
<description>Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BFHFNMIGNSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>data bus faults caused by load and store instructions cause a lock-up</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STKALIGN</name>
<description>Indicates stack alignment on exception entry</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>STKALIGNSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>4-byte aligned</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>8-byte aligned</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DC</name>
<description>Cache enable bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IC</name>
<description>Instruction cache enable bi</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BP</name>
<description>Branch prediction enable bi</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR1</name>
<description>System Handler Priority Register 1</description>
<addressOffset>0x00000018</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of system handler 4, MemManage</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_5</name>
<description>Priority of system handler 5, BusFault</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_6</name>
<description>Priority of system handler 6, UsageFault</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<description>System Handler Priority Register 2</description>
<addressOffset>0x0000001c</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler 11, SVCall</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<description>System Handler Priority Register 3</description>
<addressOffset>0x00000020</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>PRI_12</name>
<description>Priority of system handler 12, SysTick</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_14</name>
<description>Priority of system handler 14, PendSV</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_15</name>
<description>Priority of system handler 15, SysTick exception</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHCSR</name>
<description>System Handler Control and State Register</description>
<addressOffset>0x00000024</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>MEMFAULTACT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MEMFAULTACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSFAULTACT</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BUSFAULTACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USGFAULTACT</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>USGFAULTACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SVCALLACT</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SVCALLACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONITORACT</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MONITORACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PENDSVACT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PENDSVACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSTICKACT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SYSTICKACTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USGFAULTPENDED</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>USGFAULTPENDEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEMFAULTPENDED</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MEMFAULTPENDEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSFAULTPENDED</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BUSFAULTPENDEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SVCALLPENDED</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SVCALLPENDEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>exception is not pending</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>exception is pending</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEMFAULTENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MEMFAULTENASelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>disable the exception</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enable the exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSFAULTENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BUSFAULTENASelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>disable the exception</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enable the exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USGFAULTENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>USGFAULTENASelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>disable the exception</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>enable the exception</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFSR</name>
<description>Configurable Fault Status Registers</description>
<addressOffset>0x00000028</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>IACCVIOL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>IACCVIOLSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no instruction access violation fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor attempted an instruction fetch from a location that does not permit execution</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACCVIOL</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DACCVIOLSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no data access violation fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor attempted a load or store at a location that does not permit the operation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUNSTKERR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MUNSTKERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no unstacking fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>unstack for an exception return has caused one or more access violations</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTKERR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MSTKERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no stacking fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>stacking for an exception entry has caused one or more access violations</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MLSPERR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MLSPERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No MemManage fault occurred during floating-point lazy state preservation</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>A MemManage fault occurred during floating-point lazy state preservation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MMARVALID</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>MMARVALIDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>value in MMAR is not a valid fault address</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>MMAR holds a valid fault address</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IBUSERR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>IBUSERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no instruction bus error</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>instruction bus error</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRECISERR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>PRECISERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no precise data bus error</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IMPRECISERR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>IMPRECISERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no imprecise data bus error</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UNSTKERR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UNSTKERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no unstacking fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>unstack for an exception return has caused one or more BusFaults</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STKERR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>STKERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no stacking fault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>stacking for an exception entry has caused one or more BusFaults</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSPERR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>LSPERRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No bus fault occurred during floating-point lazy state preservation</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>A bus fault occurred during floating-point lazy state preservation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BFARVALID</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BFARVALIDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>value in BFAR is not a valid fault address</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>BFAR holds a valid fault address</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UNDEFINSTR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UNDEFINSTRSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no undefined instruction UsageFault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has attempted to execute an undefined instruction</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVSTATE</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INVSTATESelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no invalid state UsageFault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has attempted to execute an instruction that makes illegal use of the EPSR</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVPC</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INVPCSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no invalid PC load UsageFault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has attempted an illegal load of EXC_RETURN to the PC</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOCP</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NOCPSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no UsageFault caused by attempting to access a coprocessor</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has attempted to access a coprocessor</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UNALIGNED</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>UNALIGNEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no unaligned access fault, or unaligned access trapping not enabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has made an unaligned memory access</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVBYZERO</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIVBYZEROSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no divide by zero fault, or divide by zero trapping not enabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>the processor has executed an SDIV or UDIV instruction with a divisor of 0</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HFSR</name>
<description>HardFault Status register</description>
<addressOffset>0x0000002c</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>VECTTBL</name>
<description>Indicates when a fault has occurred because of a vector table read error on exception processing</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>VECTTBLSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no BusFault on vector table read</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>BusFault on vector table read</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCED</name>
<description>Indicates that a fault with configurable priority has been escalated to a HardFault exception</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FORCEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>no forced HardFault</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>forced HardFault</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEBUGEVT</name>
<description>Indicates when a Debug event has occurred</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DFSR</name>
<description>Debug Fault Status Register</description>
<addressOffset>0x00000030</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>HALTED</name>
<description>debug event generated by</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>HALTEDSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No active halt request debug event</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>Halt request debug event active</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKPT</name>
<description>debug event generated by BKPT instruction execution or a breakpoint match in FPB</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>BKPTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No current breakpoint debug event</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>At least one current breakpoint debug event</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DWTTRAP</name>
<description>debug event generated by the DWT</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DWTTRAPSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No current debug events generated by the DWT</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>At least one current debug event generated by the DWT</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VCATCH</name>
<description>triggering of a Vector catch</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>VCATCHSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No Vector catch triggered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>Vector catch triggered</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTERNAL</name>
<description>debug event generated because of the assertion of an external debug request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>EXTERNALSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>No EDBGRQ debug event</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>EDBGRQ debug event</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MMFAR</name>
<description>MemManage Fault Address Register</description>
<addressOffset>0x00000034</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Data address for an MPU fault</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFAR</name>
<description>BusFault Address Register</description>
<addressOffset>0x00000038</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Data address for a precise bus fault</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFSR</name>
<description>Auxiliary Fault Status Register</description>
<addressOffset>0x0000003C</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>CLIDR</name>
<description>Cache Level ID Register</description>
<addressOffset>0x00000078</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x09000003</resetValue>
<fields>
<field>
<name>LoC</name>
<description>Level of Coherency</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>LoCSelect</name>
<enumeratedValue>
<name>LEVEL_1</name>
<description>if neither instruction nor data cache is implemented</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>if either cache is implemented</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LoU</name>
<description>Level of Unification</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>LoUSelect</name>
<enumeratedValue>
<name>LEVEL_1</name>
<description>if neither instruction nor data cache is implemented</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>if either cache is implemented</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTR</name>
<description>Cache Type Register</description>
<addressOffset>0x0000007c</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x8303C003</resetValue>
<fields>
<field>
<name>IMINLINE</name>
<description>Smallest cache line of all the instruction caches under the control of the processor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMINLINE</name>
<description>Smallest cache line of all the data and unified caches under the core control</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ERG</name>
<description>Exclusives Reservation Granule</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CWG</name>
<description>Cache Writeback Granule</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FORMAT</name>
<description>Register format</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCSIDR</name>
<description>Cache Size ID Register</description>
<addressOffset>0x00000080</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>LineSize</name>
<description>number of words in each cache line</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>Associativity</name>
<description>number of ways</description>
<bitOffset>3</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NumSets</name>
<description>number of sets</description>
<bitOffset>12</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>WA</name>
<description>Write allocation support</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RA</name>
<description>Read allocation support</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WB</name>
<description>Write-Back support</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WT</name>
<description>Write-Through support</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSSELR</name>
<description>Cache Size Selection Register</description>
<addressOffset>0x00000084</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>IND</name>
<description>selection of instruction or data cache</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>INDSelect</name>
<enumeratedValue>
<name>DATA</name>
<description>Data cache</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INSTRUCTION</name>
<description>Instruction cache</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEVEL</name>
<description>cache level selected</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPACR</name>
<description>Coprocessor Access Control Register</description>
<addressOffset>0x00000088</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>CP10</name>
<description>Access privileges for coprocessor 10.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CP11</name>
<description>Access privileges for coprocessor 11.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICIALLU</name>
<description>I-cache invalidate all to PoU</description>
<addressOffset>0x00000150</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>ICIMVAU</name>
<description>I-cache invalidate by MVA to PoU</description>
<addressOffset>0x00000158</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCIMVAC</name>
<description>D-cache invalidate by MVA to PoC</description>
<addressOffset>0x0000015c</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCISW</name>
<description>D-cache invalidate by set-way</description>
<addressOffset>0x00000160</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCCMVAU</name>
<description>D-cache clean by MVA to PoU</description>
<addressOffset>0x00000164</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCCMVAC</name>
<description>D-cache clean by MVA to PoC</description>
<addressOffset>0x000000168</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCCSW</name>
<description>D-cache clean by set-way</description>
<addressOffset>0x0000016c</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCCIMVAC</name>
<description>D-cache clean and invalidate by MVA to PoC</description>
<addressOffset>0x00000170</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>DCCISW</name>
<description>D-cache clean and invalidate by set-way</description>
<addressOffset>0x00000174</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>BPIALL</name>
<description>Branch predictor invalidate all</description>
<addressOffset>0x00000178</addressOffset>
<size>32</size>
<access>write-only</access>
</register>
<register>
<name>STIR</name>
<description>Software Trigger Interrupt Register</description>
<addressOffset>0x00000200</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>MVFR0</name>
<description>Media and VFP Feature Register 0</description>
<addressOffset>0x00000240</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10110021</resetValue>
</register>
<register>
<name>MVFR1</name>
<description>Media and VFP Feature Register 1</description>
<addressOffset>0x00000244</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10110021</resetValue>
</register>
<register>
<name>MVFR2</name>
<description>Media and VFP Feature Register 2</description>
<addressOffset>0x00000248</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10110021</resetValue>
</register>
</registers>
</peripheral>
<peripheral>
<name>SysTick</name>
<description>System timer</description>
<groupName>SysTick</groupName>
<prependToName>SysTick_</prependToName>
<baseAddress>0xE000E010</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<description>Control and Status Register</description>
<addressOffset>0x00000000</addressOffset>
<size>32</size>
<resetValue>0x4</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the counter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ENABLESelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>counter disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>counter enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TICKINT</name>
<description>Enables SysTick exception request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>TICKINTSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>counting down to 0 does not assert the SysTick exception request</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>counting down to 0 asserts the SysTick exception request</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSOURCE</name>
<description>Indicates the clock source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CLKSOURCESelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>external clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>processor clock</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COUNTFLAG</name>
<description>Returns 1 if timer counted to 0 since last time this was read</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RVR</name>
<description>Reload Value Register</description>
<addressOffset>0x00000004</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>Value to load into the SysTick Current Value Register when the counter reaches 0</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVR</name>
<description>Current Value Register</description>
<addressOffset>0x00000008</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>CURRENT</name>
<description>Current value at the time the register is accessed</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<description>Calibration Value Register</description>
<addressOffset>0x0000000c</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>TENMS</name>
<description>Reload value to use for 10ms timing</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SKEW</name>
<description>Indicates whether the TENMS value is exact</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>SKEWSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>10ms calibration value is exact</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>10ms calibration value is inexact, because of the clock frequency</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOREF</name>
<description>Indicates whether the device provides a reference clock to the processor</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>NOREFSelect</name>
<enumeratedValue>
<name>VALUE_0</name>
<description>The reference clock is provided</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VALUE_1</name>
<description>The reference clock is not provided</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt Controller</description>
<groupName>NVIC</groupName>
<prependToName>NVIC_</prependToName>
<baseAddress>0xE000E100</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE04</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>ISER[%s]</name>
<description>Interrupt Set Enable Register n</description>
<addressOffset>0x00000000</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>Interrupt set enable bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>ICER[%s]</name>
<description>Interrupt Clear Enable Register n</description>
<addressOffset>0x00000080</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>Interrupt clear-enable bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>ISPR[%s]</name>
<description>Interrupt Set Pending Register n</description>
<addressOffset>0x00000100</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>Interrupt set-pending bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>ICPR[%s]</name>
<description>Interrupt Clear Pending Register n</description>
<addressOffset>0x00000180</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>Interrupt clear-pending bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>IABR[%s]</name>
<description>Interrupt Active bit Register n</description>
<addressOffset>0x00000200</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>Interrupt active flags</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>240</dim>
<dimIncrement>1</dimIncrement>
<name>IP[%s]</name>
<description>Interrupt Priority Register (8Bit wide) n</description>
<addressOffset>0x00000300</addressOffset>
<size>8</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>PRI0</name>
<description>Priority of interrupt 0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STIR</name>
<description>Software Trigger Interrupt Register</description>
<addressOffset>0x00000e00</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory Protection Unit</description>
<groupName>MPU</groupName>
<prependToName>MPU_</prependToName>
<baseAddress>0xE000ED90</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x2C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TYPE</name>
<description>MPU Type Register</description>
<addressOffset>0x00000000</addressOffset>
<size>32</size>
<resetValue>0x00001000</resetValue>
<fields>
<field>
<name>SEPARATE</name>
<description>Indicates support for unified or separate instruction and date memory maps.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREGION</name>
<description>Indicates the number of supported MPU instruction regions.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IREGION</name>
<description>Indicates the number of supported MPU data regions.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>MPU Control Register</description>
<addressOffset>0x00000004</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFNMIENA</name>
<description>Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIVDEFENA</name>
<description>Enables privileged software access to the default memory map.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RNR</name>
<description>MPU Region Number Register</description>
<addressOffset>0x00000008</addressOffset>
<size>32</size>
<fields>
<field>
<name>REGION</name>
<description>Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RBAR</name>
<description>MPU Region Base Address Register</description>
<addressOffset>0x0000000C</addressOffset>
<size>32</size>
<fields>
<field>
<name>REGION</name>
<description>MPU region field.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VALID</name>
<description>MPU Region Number valid bit.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Region base address field.</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>RASR</name>
<description>MPU Region Attribute and Size Register</description>
<addressOffset>0x00000010</addressOffset>
<size>32</size>
<fields>
<field>
<name>ENABLE</name>
<description>Region enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZE</name>
<description>Specifies the size of the MPU protection region.</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SRD</name>
<description>Subregion disable bits.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>B</name>
<description>MPU access permission attributes.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>MPU access permission attributes.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S</name>
<description>Shareable bit.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEX</name>
<description>MPU access permission attributes.</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AP</name>
<description>Access permission field.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XN</name>
<description>Instruction access disable bit.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RBAR_A1</name>
<description>MPU Alias 1 Region Base Address Register</description>
<addressOffset>0x00000014</addressOffset>
<size>32</size>
</register>
<register>
<name>RASR_A1</name>
<description>MPU Alias 1 Region Attribute and Size Register</description>
<addressOffset>0x00000018</addressOffset>
<size>32</size>
</register>
<register>
<name>RBAR_A2</name>
<description>MPU Alias 2 Region Base Address Register</description>
<addressOffset>0x0000001c</addressOffset>
<size>32</size>
</register>
<register>
<name>RASR_A2</name>
<description>MPU Alias 2 Region Attribute and Size Register</description>
<addressOffset>0x00000020</addressOffset>
<size>32</size>
</register>
<register>
<name>RBAR_A3</name>
<description>MPU Alias 3 Region Base Address Register</description>
<addressOffset>0x00000024</addressOffset>
<size>32</size>
</register>
<register>
<name>RASR_A3</name>
<description>MPU Alias 3 Region Attribute and Size Register</description>
<addressOffset>0x00000028</addressOffset>
<size>32</size>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU</name>
<description>Floating Point Unit</description>
<groupName>FPU</groupName>
<prependToName>FPU_</prependToName>
<baseAddress>0xE000EF30</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<value>61</value>
</interrupt>
<interrupt>
<name>IXC</name>
<value>68</value>
</interrupt>
<registers>
<register>
<name>FPCCR</name>
<description>Floating-point Context Control Register</description>
<addressOffset>0x00000004</addressOffset>
<size>32</size>
<resetValue>0xC0000000</resetValue>
<fields>
<field>
<name>LSPACT</name>
<description>Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER</name>
<description>Privilege level was user when the floating-point stack frame was allocated.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THREAD</name>
<description>Mode was Thread Mode when the floating-point stack frame was allocated.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFRDY</name>
<description>Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRDY</name>
<description>MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFRDY</name>
<description>BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONRDY</name>
<description>DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPEN</name>
<description>Enable automatic lazy state preservation for floating-point context.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASPEN</name>
<description>Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPCAR</name>
<description>Floating-point Context Address Register</description>
<addressOffset>0x00000008</addressOffset>
<size>32</size>
<fields>
<field>
<name>ADDRESS</name>
<description>The location of the unpopulated floating-point register space allocated on an exception stack frame.</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPDSCR</name>
<description>Floating-point Default Status Control Register</description>
<addressOffset>0x0000000C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RMode</name>
<description>Default value for FPSCR.RMode.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FZ</name>
<description>Default value for FPSCR.FZ.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DN</name>
<description>Default value for FPSCR.DN.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHP</name>
<description>Default value for FPSCR.AHP.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MVFR0</name>
<description>Media and VFP Feature Register 0</description>
<addressOffset>0x00000010</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10110021</resetValue>
<fields>
<field>
<name>A_SIMD_registers</name>
<description>Indicates the size of the FP register bank</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Single_precision</name>
<description>Indicates the hardware support for FP single-precision operations</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Double_precision</name>
<description>Indicates the hardware support for FP double-precision operations</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FP_excep_trapping</name>
<description>Indicates whether the FP hardware implementation supports exception trapping</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Divide</name>
<description>Indicates the hardware support for FP divide operations</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Square_root</name>
<description>Indicates the hardware support for FP square root operations</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Short_vectors</name>
<description>Indicates the hardware support for FP short vectors</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FP_rounding_modes</name>
<description>Indicates the rounding modes supported by the FP floating-point hardware</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>MVFR1</name>
<description>Media and VFP Feature Register 1</description>
<addressOffset>0x00000014</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x11000011</resetValue>
<fields>
<field>
<name>FtZ_mode</name>
<description>Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>D_NaN_mode</name>
<description>Indicates whether the FP hardware implementation supports only the Default NaN mode</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FP_HPFP</name>
<description>Floating Point Half-Precision and double-precision</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FP_fused_MAC</name>
<description>Indicates whether the FP supports fused multiply accumulate operations</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>MVFR2</name>
<description>Media and VFP Feature Register 2</description>
<addressOffset>0x00000018</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>VFP_Misc</name>
<description>Indicates the hardware support for FP miscellaneous features</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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