22702 lines
964 KiB
XML
22702 lines
964 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!--
|
|
Copyright (c) 2017 Microchip Technology Inc.
|
|
|
|
SPDX-License-Identifier: Apache-2.0
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
you may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.
|
|
-->
|
|
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
|
|
schemaVersion="1.1"
|
|
xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
|
|
<vendor>Microchip Technology</vendor>
|
|
<vendorID>MCHP</vendorID>
|
|
<name>ATSAML11D14A</name>
|
|
<series>SAML11</series>
|
|
<version>0</version>
|
|
<description>Microchip ATSAML11D14A Microcontroller</description>
|
|
<cpu>
|
|
<name>CM23</name>
|
|
<revision>r0p0</revision>
|
|
<endian>selectable</endian>
|
|
<mpuPresent>true</mpuPresent>
|
|
<fpuPresent>false</fpuPresent>
|
|
<nvicPrioBits>2</nvicPrioBits>
|
|
<vendorSystickConfig>false</vendorSystickConfig>
|
|
</cpu>
|
|
<addressUnitBits>8</addressUnitBits>
|
|
<width>32</width>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>AC</name>
|
|
<version>U22451.0.2</version>
|
|
<description>Analog Comparators</description>
|
|
<groupName>AC</groupName>
|
|
<prependToName>AC_</prependToName>
|
|
<baseAddress>0x40003400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>AC</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START0</name>
|
|
<description>Comparator 0 Start Comparison</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START1</name>
|
|
<description>Comparator 1 Start Comparison</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMPEO0</name>
|
|
<description>Comparator 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPEO1</name>
|
|
<description>Comparator 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINEO0</name>
|
|
<description>Window 0 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPEI0</name>
|
|
<description>Comparator 0 Event Input Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPEI1</name>
|
|
<description>Comparator 1 Event Input Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEI0</name>
|
|
<description>Comparator 0 Input Event Invert Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEI1</name>
|
|
<description>Comparator 1 Input Event Invert Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Comparator 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Comparator 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIN0</name>
|
|
<description>Window 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Comparator 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Comparator 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIN0</name>
|
|
<description>Window 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Comparator 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Comparator 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIN0</name>
|
|
<description>Window 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSA</name>
|
|
<description>Status A</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STATE0</name>
|
|
<description>Comparator 0 Current State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATE1</name>
|
|
<description>Comparator 1 Current State</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WSTATE0</name>
|
|
<description>Window 0 Current State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WSTATE0Select</name>
|
|
<enumeratedValue>
|
|
<name>ABOVE</name>
|
|
<description>Signal is above window</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INSIDE</name>
|
|
<description>Signal is inside window</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BELOW</name>
|
|
<description>Signal is below window</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSB</name>
|
|
<description>Status B</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READY0</name>
|
|
<description>Comparator 0 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY1</name>
|
|
<description>Comparator 1 Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINCTRL</name>
|
|
<description>Window Control</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WEN0</name>
|
|
<description>Window 0 Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINTSEL0</name>
|
|
<description>Window 0 Interrupt Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WINTSEL0Select</name>
|
|
<enumeratedValue>
|
|
<name>ABOVE</name>
|
|
<description>Interrupt on signal above window</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INSIDE</name>
|
|
<description>Interrupt on signal inside window</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BELOW</name>
|
|
<description>Interrupt on signal below window</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE</name>
|
|
<description>Interrupt on signal outside window</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>SCALER[%s]</name>
|
|
<description>Scaler n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Scaler Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>COMPCTRL[%s]</name>
|
|
<description>Comparator Control n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINGLE</name>
|
|
<description>Single-Shot Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTSEL</name>
|
|
<description>Interrupt Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INTSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Interrupt on comparator output toggle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Interrupt on comparator output rising</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Interrupt on comparator output falling</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EOC</name>
|
|
<description>Interrupt on end of comparison (single-shot mode only)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXNEG</name>
|
|
<description>Negative Input Mux Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXNEGSelect</name>
|
|
<enumeratedValue>
|
|
<name>PIN0</name>
|
|
<description>I/O pin 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN1</name>
|
|
<description>I/O pin 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN2</name>
|
|
<description>I/O pin 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN3</name>
|
|
<description>I/O pin 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GND</name>
|
|
<description>Ground</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSCALE</name>
|
|
<description>VDD scaler</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BANDGAP</name>
|
|
<description>Internal bandgap voltage</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPAMP</name>
|
|
<description>OPAMP output (on AC1)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC output (on AC0)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXPOS</name>
|
|
<description>Positive Input Mux Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXPOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>PIN0</name>
|
|
<description>I/O pin 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN1</name>
|
|
<description>I/O pin 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN2</name>
|
|
<description>I/O pin 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN3</name>
|
|
<description>I/O pin 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSCALE</name>
|
|
<description>VDD Scaler</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap Inputs and Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPEEDSelect</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low speed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDLOW</name>
|
|
<description>Medium low speed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDHIGH</name>
|
|
<description>Medium high speed</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High speed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYSTEN</name>
|
|
<description>Hysteresis Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis Level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HYSTSelect</name>
|
|
<enumeratedValue>
|
|
<name>HYST50</name>
|
|
<description>50mV</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST70</name>
|
|
<description>70mV</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST90</name>
|
|
<description>90mV</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST110</name>
|
|
<description>110mV</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEN</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FLENSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>No filtering</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJ3</name>
|
|
<description>3-bit majority function (2 of 3)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJ5</name>
|
|
<description>5-bit majority function (3 of 5)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>OUTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>The output of COMPn is not routed to the COMPn I/O port</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINCTRL</name>
|
|
<description>WINCTRL Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPCTRL0</name>
|
|
<description>COMPCTRL 0 Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPCTRL1</name>
|
|
<description>COMPCTRL 1 Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<version>U22472.4.0</version>
|
|
<description>Analog Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC_</prependToName>
|
|
<baseAddress>0x42001C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2E</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC_OTHER</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_RESRDY</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVEEN</name>
|
|
<description>Slave Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run During Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Peripheral clock divided by 2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Peripheral clock divided by 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Peripheral clock divided by 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Peripheral clock divided by 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Peripheral clock divided by 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Peripheral clock divided by 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Peripheral clock divided by 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Peripheral clock divided by 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFCTRL</name>
|
|
<description>Reference Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>INTREF</name>
|
|
<description>Internal Bandgap Reference</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTVCC0</name>
|
|
<description>1/1.6 VDDANA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTVCC1</name>
|
|
<description>1/2 VDDANA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AREFA</name>
|
|
<description>External Reference</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AREFB</name>
|
|
<description>External Reference</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTVCC2</name>
|
|
<description>VCCANA</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFCOMP</name>
|
|
<description>Reference Buffer Offset Compensation Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLUSHEI</name>
|
|
<description>Flush Event Input Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTEI</name>
|
|
<description>Start Conversion Event Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLUSHINV</name>
|
|
<description>Flush Event Invert Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTINV</name>
|
|
<description>Satrt Event Invert Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDYEO</name>
|
|
<description>Result Ready Event Out</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMONEO</name>
|
|
<description>Window Monitor Event Out</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQSTATUS</name>
|
|
<description>Sequence Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEQSTATE</name>
|
|
<description>Sequence State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEQBUSY</name>
|
|
<description>Sequence Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUTCTRL</name>
|
|
<description>Input Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUXPOS</name>
|
|
<description>Positive Mux Input Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXPOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>AIN0</name>
|
|
<description>ADC AIN0 Pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN1</name>
|
|
<description>ADC AIN1 Pin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN2</name>
|
|
<description>ADC AIN2 Pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN3</name>
|
|
<description>ADC AIN3 Pin</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN4</name>
|
|
<description>ADC AIN4 Pin</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN5</name>
|
|
<description>ADC AIN5 Pin</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN6</name>
|
|
<description>ADC AIN6 Pin</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN7</name>
|
|
<description>ADC AIN7 Pin</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN8</name>
|
|
<description>ADC AIN8 Pin</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN9</name>
|
|
<description>ADC AIN9 Pin</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN10</name>
|
|
<description>ADC AIN10 Pin</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN11</name>
|
|
<description>ADC AIN11 Pin</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN12</name>
|
|
<description>ADC AIN12 Pin</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN13</name>
|
|
<description>ADC AIN13 Pin</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN14</name>
|
|
<description>ADC AIN14 Pin</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN15</name>
|
|
<description>ADC AIN15 Pin</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN16</name>
|
|
<description>ADC AIN16 Pin</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN17</name>
|
|
<description>ADC AIN17 Pin</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN18</name>
|
|
<description>ADC AIN18 Pin</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN19</name>
|
|
<description>ADC AIN19 Pin</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN20</name>
|
|
<description>ADC AIN20 Pin</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN21</name>
|
|
<description>ADC AIN21 Pin</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN22</name>
|
|
<description>ADC AIN22 Pin</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN23</name>
|
|
<description>ADC AIN23 Pin</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP</name>
|
|
<description>Temperature Sensor</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BANDGAP</name>
|
|
<description>Bandgap Voltage</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDCOREVCC</name>
|
|
<description>1/4 Scaled Core Supply</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDIOVCC</name>
|
|
<description>1/4 Scaled I/O Supply</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC Output</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDVBAT</name>
|
|
<description>1/4 Scaled VBAT Supply</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPAMP01</name>
|
|
<description>OPAMP0 or OPAMP1 output</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPAMP2</name>
|
|
<description>OPAMP2 output</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXNEG</name>
|
|
<description>Negative Mux Input Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXNEGSelect</name>
|
|
<enumeratedValue>
|
|
<name>AIN0</name>
|
|
<description>ADC AIN0 Pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN1</name>
|
|
<description>ADC AIN1 Pin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN2</name>
|
|
<description>ADC AIN2 Pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN3</name>
|
|
<description>ADC AIN3 Pin</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN4</name>
|
|
<description>ADC AIN4 Pin</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN5</name>
|
|
<description>ADC AIN5 Pin</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN6</name>
|
|
<description>ADC AIN6 Pin</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN7</name>
|
|
<description>ADC AIN7 Pin</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIFFMODE</name>
|
|
<description>Differential Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEFTADJ</name>
|
|
<description>Left-Adjusted Result</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREERUN</name>
|
|
<description>Free Running Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CORREN</name>
|
|
<description>Digital Correction Logic Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESSEL</name>
|
|
<description>Conversion Result Resolution</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RESSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>12BIT</name>
|
|
<description>12-bit result</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>For averaging mode output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BIT</name>
|
|
<description>10-bit result</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>8-bit result</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R2R</name>
|
|
<description>Rail-to-Rail mode enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMODE</name>
|
|
<description>Window Monitor Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WINMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No window mode (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>RESULT > WINLT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>RESULT < WINUT</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>WINLT < RESULT < WINUT</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE4</name>
|
|
<description>!(WINLT < RESULT < WINUT)</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUALSEL</name>
|
|
<description>Dual Mode Trigger Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DUALSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Start event or software trigger will start a conversion on both ADCs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERLEAVE</name>
|
|
<description>START event or software trigger will alternatingly start a conversion on ADC0 and ADC1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AVGCTRL</name>
|
|
<description>Average Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLENUM</name>
|
|
<description>Number of Samples to be Collected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SAMPLENUMSelect</name>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1 sample</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>2 samples</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>4 samples</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 samples</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 samples</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 samples</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 samples</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128</name>
|
|
<description>128 samples</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256</name>
|
|
<description>256 samples</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 samples</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 samples</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADJRES</name>
|
|
<description>Adjusting Result / Division Coefficient</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMPCTRL</name>
|
|
<description>Sample Time Control</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLEN</name>
|
|
<description>Sampling Time Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFCOMP</name>
|
|
<description>Comparator Offset Compensation Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINLT</name>
|
|
<description>Window Monitor Lower Threshold</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>Window Lower Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINUT</name>
|
|
<description>Window Monitor Upper Threshold</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>Window Upper Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLUSH</name>
|
|
<description>ADC Flush</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start ADC Conversion</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>SWRST Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>ENABLE Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INPUTCTRL</name>
|
|
<description>INPUTCTRL Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLC</name>
|
|
<description>CTRLC Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AVGCTRL</name>
|
|
<description>AVGCTRL Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPCTRL</name>
|
|
<description>SAMPCTRL Synchronization Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>WINLT Synchronization Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>WINUT Synchronization Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>GAINCORR Synchronization Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>OFFSETCTRL Synchronization Busy</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>SWTRG Synchronization Busy</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESULT</name>
|
|
<description>Result</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>Result Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQCTRL</name>
|
|
<description>Sequence Control</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEQEN</name>
|
|
<description>Enable Positive Input in the Sequence</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>Calibration</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIASCOMP</name>
|
|
<description>Bias Comparator Scaling</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIASREFBUF</name>
|
|
<description>Bias Reference Buffer Scaling</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCL</name>
|
|
<version>U22252.0.0</version>
|
|
<description>Configurable Custom Logic</description>
|
|
<groupName>CCL</groupName>
|
|
<prependToName>CCL_</prependToName>
|
|
<baseAddress>0x42002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>SEQCTRL[%s]</name>
|
|
<description>SEQ Control x</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEQSEL</name>
|
|
<description>Sequential Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SEQSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Sequential logic is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DFF</name>
|
|
<description>D flip flop</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>JK</name>
|
|
<description>JK flip flop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCH</name>
|
|
<description>D latch</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RS</name>
|
|
<description>RS latch</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>LUTCTRL[%s]</name>
|
|
<description>LUT Control x</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>LUT Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTSEL</name>
|
|
<description>Filter Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FILTSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCH</name>
|
|
<description>Synchronizer enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER</name>
|
|
<description>Filter enabled</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGESEL</name>
|
|
<description>Edge Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSEL0</name>
|
|
<description>Input Selection 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL0Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2TC</name>
|
|
<description>Alternate 2 TC input source</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCEVENT</name>
|
|
<description>Asynchronous event input source. The EVENT input will bypass edge detection logic.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL1</name>
|
|
<description>Input Selection 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL1Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2TC</name>
|
|
<description>Alternate 2 TC input source</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCEVENT</name>
|
|
<description>Asynchronous event input source. The EVENT input will bypass edge detection logic.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL2</name>
|
|
<description>Input Selection 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL2Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2TC</name>
|
|
<description>Alternate 2 TC input source</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCEVENT</name>
|
|
<description>Asynchronous event input source. The EVENT input will bypass edge detection logic.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVEI</name>
|
|
<description>Inverted Event Input Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUTEI</name>
|
|
<description>LUT Event Input Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUTEO</name>
|
|
<description>LUT Event Output Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRUTH</name>
|
|
<description>Truth Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<version>U22142.1.0</version>
|
|
<description>Digital Analog Converter</description>
|
|
<groupName>DAC</groupName>
|
|
<prependToName>DAC_</prependToName>
|
|
<baseAddress>0x42002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x15</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC_UNDERRUN_A</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC_EMPTY</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EOEN</name>
|
|
<description>External Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOEN</name>
|
|
<description>Internal Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEFTADJ</name>
|
|
<description>Left Adjusted Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPD</name>
|
|
<description>Voltage Pump Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dither Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>INT1V</name>
|
|
<description>Internal 1.0V reference</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVCC</name>
|
|
<description>AVCC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREFP</name>
|
|
<description>External reference</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STARTEI</name>
|
|
<description>Start Conversion Event Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTYEO</name>
|
|
<description>Data Buffer Empty Event Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEI</name>
|
|
<description>Invert Event Input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN</name>
|
|
<description>Underrun Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY</name>
|
|
<description>Data Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN</name>
|
|
<description>Underrun Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY</name>
|
|
<description>Data Buffer Empty Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN</name>
|
|
<description>Underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY</name>
|
|
<description>Data Buffer Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READY</name>
|
|
<description>Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data value to be converted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATABUF</name>
|
|
<description>Data Buffer</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATABUF</name>
|
|
<description>Data Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATABUF</name>
|
|
<description>Data Buffer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAC</name>
|
|
<version>U22232.4.0</version>
|
|
<description>Direct Memory Access Controller</description>
|
|
<groupName>DMAC</groupName>
|
|
<prependToName>DMAC_</prependToName>
|
|
<baseAddress>0x41006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x50</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMAC_0</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_1</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_2</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_3</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_OTHER</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAENABLE</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCENABLE</name>
|
|
<description>CRC Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN0</name>
|
|
<description>Priority Level 0 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN1</name>
|
|
<description>Priority Level 1 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN2</name>
|
|
<description>Priority Level 2 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN3</name>
|
|
<description>Priority Level 3 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCCTRL</name>
|
|
<description>CRC Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCBEATSIZE</name>
|
|
<description>CRC Beat Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCBEATSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>BYTE</name>
|
|
<description>8-bit bus transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HWORD</name>
|
|
<description>16-bit bus transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD</name>
|
|
<description>32-bit bus transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>CRC Polynomial Type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCPOLYSelect</name>
|
|
<enumeratedValue>
|
|
<name>CRC16</name>
|
|
<description>CRC-16 (CRC-CCITT)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC32</name>
|
|
<description>CRC32 (IEEE 802.3)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCSRC</name>
|
|
<description>CRC Input Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCSRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOACT</name>
|
|
<description>No action</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O interface</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDATAIN</name>
|
|
<description>CRC Data Input</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDATAIN</name>
|
|
<description>CRC Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCCHKSUM</name>
|
|
<description>CRC Checksum</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCCHKSUM</name>
|
|
<description>CRC Checksum</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCSTATUS</name>
|
|
<description>CRC Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCBUSY</name>
|
|
<description>CRC Module Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCZERO</name>
|
|
<description>CRC Zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QOSCTRL</name>
|
|
<description>QOS Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x2A</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRBQOS</name>
|
|
<description>Write-Back Quality of Service</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WRBQOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Background (no sensitive operation)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Sensitive Bandwidth</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM</name>
|
|
<description>Sensitive Latency</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Critical Latency</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FQOS</name>
|
|
<description>Fetch Quality of Service</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FQOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Background (no sensitive operation)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Sensitive Bandwidth</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM</name>
|
|
<description>Sensitive Latency</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Critical Latency</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DQOS</name>
|
|
<description>Data Transfer Quality of Service</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DQOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Background (no sensitive operation)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Sensitive Bandwidth</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM</name>
|
|
<description>Sensitive Latency</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Critical Latency</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRIGCTRL</name>
|
|
<description>Software Trigger Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRIG0</name>
|
|
<description>Channel 0 Software Trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG1</name>
|
|
<description>Channel 1 Software Trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG2</name>
|
|
<description>Channel 2 Software Trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG3</name>
|
|
<description>Channel 3 Software Trigger</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG4</name>
|
|
<description>Channel 4 Software Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG5</name>
|
|
<description>Channel 5 Software Trigger</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG6</name>
|
|
<description>Channel 6 Software Trigger</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG7</name>
|
|
<description>Channel 7 Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRICTRL0</name>
|
|
<description>Priority Control 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LVLPRI0</name>
|
|
<description>Level 0 Channel Priority Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN0</name>
|
|
<description>Level 0 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI1</name>
|
|
<description>Level 1 Channel Priority Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN1</name>
|
|
<description>Level 1 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI2</name>
|
|
<description>Level 2 Channel Priority Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN2</name>
|
|
<description>Level 2 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI3</name>
|
|
<description>Level 3 Channel Priority Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN3</name>
|
|
<description>Level 3 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTPEND</name>
|
|
<description>Interrupt Pending</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Transfer Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Transfer Complete</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Fetch Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEND</name>
|
|
<description>Pending</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHINT0</name>
|
|
<description>Channel 0 Pending Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT1</name>
|
|
<description>Channel 1 Pending Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT2</name>
|
|
<description>Channel 2 Pending Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT3</name>
|
|
<description>Channel 3 Pending Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT4</name>
|
|
<description>Channel 4 Pending Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT5</name>
|
|
<description>Channel 5 Pending Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT6</name>
|
|
<description>Channel 6 Pending Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT7</name>
|
|
<description>Channel 7 Pending Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channels</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYCH0</name>
|
|
<description>Busy Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH1</name>
|
|
<description>Busy Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH2</name>
|
|
<description>Busy Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH3</name>
|
|
<description>Busy Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH4</name>
|
|
<description>Busy Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH5</name>
|
|
<description>Busy Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH6</name>
|
|
<description>Busy Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH7</name>
|
|
<description>Busy Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PENDCH</name>
|
|
<description>Pending Channels</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PENDCH0</name>
|
|
<description>Pending Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH1</name>
|
|
<description>Pending Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH2</name>
|
|
<description>Pending Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH3</name>
|
|
<description>Pending Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH4</name>
|
|
<description>Pending Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH5</name>
|
|
<description>Pending Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH6</name>
|
|
<description>Pending Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH7</name>
|
|
<description>Pending Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTIVE</name>
|
|
<description>Active Channel and Levels</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LVLEX0</name>
|
|
<description>Level 0 Channel Trigger Request Executing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX1</name>
|
|
<description>Level 1 Channel Trigger Request Executing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX2</name>
|
|
<description>Level 2 Channel Trigger Request Executing</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX3</name>
|
|
<description>Level 3 Channel Trigger Request Executing</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Active Channel ID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABUSY</name>
|
|
<description>Active Channel Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTCNT</name>
|
|
<description>Active Channel Block Transfer Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASEADDR</name>
|
|
<description>Descriptor Memory Section Base Address</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BASEADDR</name>
|
|
<description>Descriptor Memory Base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRBADDR</name>
|
|
<description>Write-Back Memory Section Base Address</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRBADDR</name>
|
|
<description>Write-Back Memory Base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHID</name>
|
|
<description>Channel ID</description>
|
|
<addressOffset>0x3F</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTRLA</name>
|
|
<description>Channel Control A</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Channel Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Channel run in standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTRLB</name>
|
|
<description>Channel Control B</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Input Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOACT</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG</name>
|
|
<description>Transfer and periodic transfer trigger</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTRIG</name>
|
|
<description>Conditional transfer trigger</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CBLOCK</name>
|
|
<description>Conditional block transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>Channel suspend operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>Channel resume operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSKIP</name>
|
|
<description>Skip next block suspend action</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVIE</name>
|
|
<description>Channel Event Input Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVOE</name>
|
|
<description>Channel Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVL</name>
|
|
<description>Channel Arbitration Level</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIGSRC</name>
|
|
<description>Trigger Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRIGSRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Only software/event triggers</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGACT</name>
|
|
<description>Trigger Action</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRIGACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>BLOCK</name>
|
|
<description>One trigger required for each block transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BEAT</name>
|
|
<description>One trigger required for each beat transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSACTION</name>
|
|
<description>One trigger required for each transaction</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Software Command</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOACT</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>Channel suspend operation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>Channel resume operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENCLR</name>
|
|
<description>Channel Interrupt Enable Clear</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENSET</name>
|
|
<description>Channel Interrupt Enable Set</description>
|
|
<addressOffset>0x4D</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTFLAG</name>
|
|
<description>Channel Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x4E</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSTATUS</name>
|
|
<description>Channel Status</description>
|
|
<addressOffset>0x4F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEND</name>
|
|
<description>Channel Pending</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Channel Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Channel Fetch Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DSU</name>
|
|
<version>U28101.0.0</version>
|
|
<description>Device Service Unit</description>
|
|
<groupName>DSU</groupName>
|
|
<prependToName>DSU_</prependToName>
|
|
<baseAddress>0x41002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>32-bit Cyclic Redundancy Code</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBIST</name>
|
|
<description>Memory built-in self-test</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSA</name>
|
|
<description>Status A</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRSTEXT</name>
|
|
<description>CPU Reset Phase Extension</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAIL</name>
|
|
<description>Failure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Protection Error Detected by the State Machine</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BREXT</name>
|
|
<description>BootRom Phase Extension</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSB</name>
|
|
<description>Status B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAL</name>
|
|
<description>Debugger Access Level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DALSelect</name>
|
|
<enumeratedValue>
|
|
<name>SECURED</name>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NS_DEBUG</name>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_DEBUG</name>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGPRES</name>
|
|
<description>Debugger Present</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPE</name>
|
|
<description>Hot-Plugging Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCD0</name>
|
|
<description>Debug Communication Channel 0 Dirty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCD1</name>
|
|
<description>Debug Communication Channel 1 Dirty</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCCD0</name>
|
|
<description>Boot ROM Communication Channel 0 Dirty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCCD1</name>
|
|
<description>Boot ROM Communication Channel 1 Dirty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSC</name>
|
|
<description>Status C</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AMOD</name>
|
|
<description>Access Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>Length</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>DCC[%s]</name>
|
|
<description>Debug Communication Channel n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DID</name>
|
|
<description>Device Identification</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x20830005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIE</name>
|
|
<description>Die Number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERIES</name>
|
|
<description>Series</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SERIESSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cortex-M0+ processor, basic feature set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cortex-M0+ processor, USB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAMILY</name>
|
|
<description>Family</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FAMILYSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General purpose microcontroller</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PicoPower</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROCESSOR</name>
|
|
<description>Processor</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PROCESSORSelect</name>
|
|
<enumeratedValue>
|
|
<name>CM0P</name>
|
|
<description>Cortex-M0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM23</name>
|
|
<description>Cortex-M23</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM3</name>
|
|
<description>Cortex-M3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM4</name>
|
|
<description>Cortex-M4</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM4F</name>
|
|
<description>Cortex-M4 with FPU</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM33</name>
|
|
<description>Cortex-M33</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LQOS</name>
|
|
<description>Latency Quality Of Service</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCDMALEVEL</name>
|
|
<description>DMA Trigger Level</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DCCDMALEVELSelect</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Trigger rises when DCC is empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>Trigger rises when DCC is full</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>BCC[%s]</name>
|
|
<description>Boot ROM Communication Channel n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>DCFG[%s]</name>
|
|
<description>Device Configuration</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCFG</name>
|
|
<description>Device Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENTRY0</name>
|
|
<description>CoreSight ROM Table Entry 0</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x9F0FC002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPRES</name>
|
|
<description>Entry Present</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMT</name>
|
|
<description>Format</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDOFF</name>
|
|
<description>Address Offset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENTRY1</name>
|
|
<description>CoreSight ROM Table Entry 1</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>END</name>
|
|
<description>CoreSight ROM Table End</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>END</name>
|
|
<description>End Marker</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEMTYPE</name>
|
|
<description>CoreSight ROM Table Memory Type</description>
|
|
<addressOffset>0x1FCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEMP</name>
|
|
<description>System Memory Present</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID4</name>
|
|
<description>Peripheral Identification 4</description>
|
|
<addressOffset>0x1FD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JEPCC</name>
|
|
<description>JEP-106 Continuation Code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FKBC</name>
|
|
<description>4KB count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID5</name>
|
|
<description>Peripheral Identification 5</description>
|
|
<addressOffset>0x1FD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID6</name>
|
|
<description>Peripheral Identification 6</description>
|
|
<addressOffset>0x1FD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID7</name>
|
|
<description>Peripheral Identification 7</description>
|
|
<addressOffset>0x1FDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID0</name>
|
|
<description>Peripheral Identification 0</description>
|
|
<addressOffset>0x1FE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNBL</name>
|
|
<description>Part Number Low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID1</name>
|
|
<description>Peripheral Identification 1</description>
|
|
<addressOffset>0x1FE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000FC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNBH</name>
|
|
<description>Part Number High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEPIDCL</name>
|
|
<description>Low part of the JEP-106 Identity Code</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID2</name>
|
|
<description>Peripheral Identification 2</description>
|
|
<addressOffset>0x1FE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000009</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JEPIDCH</name>
|
|
<description>JEP-106 Identity Code High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEPU</name>
|
|
<description>JEP-106 Identity Code is used</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID3</name>
|
|
<description>Peripheral Identification 3</description>
|
|
<addressOffset>0x1FEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CUSMOD</name>
|
|
<description>ARM CUSMOD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID0</name>
|
|
<description>Component Identification 0</description>
|
|
<addressOffset>0x1FF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB0</name>
|
|
<description>Preamble Byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID1</name>
|
|
<description>Component Identification 1</description>
|
|
<addressOffset>0x1FF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLE</name>
|
|
<description>Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLASS</name>
|
|
<description>Component Class</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID2</name>
|
|
<description>Component Identification 2</description>
|
|
<addressOffset>0x1FF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB2</name>
|
|
<description>Preamble Byte 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID3</name>
|
|
<description>Component Identification 3</description>
|
|
<addressOffset>0x1FFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB3</name>
|
|
<description>Preamble Byte 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DSU">
|
|
<name>DSU_EXT</name>
|
|
<prependToName>DSU_EXT_</prependToName>
|
|
<baseAddress>0x41002100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EIC</name>
|
|
<version>U28041.0.0</version>
|
|
<description>External Interrupt Controller</description>
|
|
<groupName>EIC</groupName>
|
|
<prependToName>EIC_</prependToName>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x44</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EIC_0</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_1</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_2</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_3</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_OTHER</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMICTRL</name>
|
|
<description>Non-Maskable Interrupt Control</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NMISENSE</name>
|
|
<description>Non-Maskable Interrupt Sense Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NMISENSESelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising-edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling-edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both-edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High-level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low-level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIFILTEN</name>
|
|
<description>Non-Maskable Interrupt Filter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMIASYNCH</name>
|
|
<description>Asynchronous Edge Detection Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMIFLAG</name>
|
|
<description>Non-Maskable Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>Non-Maskable Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINTEO</name>
|
|
<description>External Interrupt Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-secure Check Interrupt Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-secure Check Interrupt Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-secure Check Interrupt</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASYNCH</name>
|
|
<description>External Interrupt Asynchronous Mode</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCH</name>
|
|
<description>Asynchronous Edge Detection Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CONFIG[%s]</name>
|
|
<description>External Interrupt Sense Configuration</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SENSE0</name>
|
|
<description>Input Sense Configuration 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE0Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN0</name>
|
|
<description>Filter Enable 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE1</name>
|
|
<description>Input Sense Configuration 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE1Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN1</name>
|
|
<description>Filter Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE2</name>
|
|
<description>Input Sense Configuration 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE2Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN2</name>
|
|
<description>Filter Enable 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE3</name>
|
|
<description>Input Sense Configuration 3</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE3Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN3</name>
|
|
<description>Filter Enable 3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE4</name>
|
|
<description>Input Sense Configuration 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE4Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN4</name>
|
|
<description>Filter Enable 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE5</name>
|
|
<description>Input Sense Configuration 5</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE5Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN5</name>
|
|
<description>Filter Enable 5</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE6</name>
|
|
<description>Input Sense Configuration 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE6Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN6</name>
|
|
<description>Filter Enable 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE7</name>
|
|
<description>Input Sense Configuration 7</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE7Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN7</name>
|
|
<description>Filter Enable 7</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBOUNCEN</name>
|
|
<description>Debouncer Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEBOUNCEN</name>
|
|
<description>Debouncer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPRESCALER</name>
|
|
<description>Debouncer Prescaler</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER0</name>
|
|
<description>Debouncer Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATES0</name>
|
|
<description>Debouncer number of states</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TICKON</name>
|
|
<description>Pin Sampler frequency selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINSTATE</name>
|
|
<description>Pin State</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PINSTATE</name>
|
|
<description>Pin State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NSCHK</name>
|
|
<description>Non-secure Interrupt Check Enable</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Nonsecure Check Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>Non-Maskable External Interrupt Nonsecure Check Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSEC</name>
|
|
<description>Non-secure Interrupt</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Nonsecure Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>Non-Maskable Interrupt Nonsecure Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="EIC">
|
|
<name>EIC_SEC</name>
|
|
<prependToName>EIC_SEC_</prependToName>
|
|
<baseAddress>0x40002A00</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EVSYS</name>
|
|
<version>U25042.0.0</version>
|
|
<description>Event System Interface</description>
|
|
<groupName>EVSYS</groupName>
|
|
<prependToName>EVSYS_</prependToName>
|
|
<baseAddress>0x42000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1F4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EVSYS_0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_1</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_2</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_3</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_NSCHK</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVT</name>
|
|
<description>Software Event</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL0</name>
|
|
<description>Channel 0 Software Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL1</name>
|
|
<description>Channel 1 Software Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL2</name>
|
|
<description>Channel 2 Software Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL3</name>
|
|
<description>Channel 3 Software Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL4</name>
|
|
<description>Channel 4 Software Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL5</name>
|
|
<description>Channel 5 Software Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL6</name>
|
|
<description>Channel 6 Software Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL7</name>
|
|
<description>Channel 7 Software Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRICTRL</name>
|
|
<description>Priority Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Channel Priority Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RREN</name>
|
|
<description>Round-Robin Scheduling Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTPEND</name>
|
|
<description>Channel Pending Interrupt</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x4000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY</name>
|
|
<description>Ready</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHINT0</name>
|
|
<description>Channel 0 Pending Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT1</name>
|
|
<description>Channel 1 Pending Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT2</name>
|
|
<description>Channel 2 Pending Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT3</name>
|
|
<description>Channel 3 Pending Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channels</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYCH0</name>
|
|
<description>Busy Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH1</name>
|
|
<description>Busy Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH2</name>
|
|
<description>Busy Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH3</name>
|
|
<description>Busy Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READYUSR</name>
|
|
<description>Ready Users</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READYUSR0</name>
|
|
<description>Ready User for Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR1</name>
|
|
<description>Ready User for Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR2</name>
|
|
<description>Ready User for Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR3</name>
|
|
<description>Ready User for Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<name>CHANNEL[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x020</addressOffset>
|
|
<register>
|
|
<name>CHANNEL</name>
|
|
<description>Channel n Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVGEN</name>
|
|
<description>Event Generator Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PATH</name>
|
|
<description>Path Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PATHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS</name>
|
|
<description>Synchronous path</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNCHRONIZED</name>
|
|
<description>Resynchronized path</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS</name>
|
|
<description>Asynchronous path</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGSEL</name>
|
|
<description>Edge Detection Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EDGSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO_EVT_OUTPUT</name>
|
|
<description>No event output when using the resynchronized or synchronous path</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in standby</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Generic Clock On Demand</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENCLR</name>
|
|
<description>Channel n Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENSET</name>
|
|
<description>Channel n Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTFLAG</name>
|
|
<description>Channel n Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSTATUS</name>
|
|
<description>Channel n Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDYUSR</name>
|
|
<description>Ready User</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channel</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<register>
|
|
<dim>23</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>USER[%s]</name>
|
|
<description>User Multiplexer n</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL</name>
|
|
<description>Channel Event Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x1D5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x1D6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSECCHAN</name>
|
|
<description>Channels Security Attribution</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL0</name>
|
|
<description>Non-Secure for Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL1</name>
|
|
<description>Non-Secure for Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL2</name>
|
|
<description>Non-Secure for Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL3</name>
|
|
<description>Non-Secure for Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL4</name>
|
|
<description>Non-Secure for Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL5</name>
|
|
<description>Non-Secure for Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL6</name>
|
|
<description>Non-Secure for Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL7</name>
|
|
<description>Non-Secure for Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NSCHKCHAN</name>
|
|
<description>Non-Secure Channels Check</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL0</name>
|
|
<description>Channel 0 to be checked as non-secured</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL1</name>
|
|
<description>Channel 1 to be checked as non-secured</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL2</name>
|
|
<description>Channel 2 to be checked as non-secured</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL3</name>
|
|
<description>Channel 3 to be checked as non-secured</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL4</name>
|
|
<description>Channel 4 to be checked as non-secured</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL5</name>
|
|
<description>Channel 5 to be checked as non-secured</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL6</name>
|
|
<description>Channel 6 to be checked as non-secured</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL7</name>
|
|
<description>Channel 7 to be checked as non-secured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NONSECUSER[%s]</name>
|
|
<description>Users Security Attribution</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USER0</name>
|
|
<description>Non-Secure for User 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER1</name>
|
|
<description>Non-Secure for User 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER2</name>
|
|
<description>Non-Secure for User 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER3</name>
|
|
<description>Non-Secure for User 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER4</name>
|
|
<description>Non-Secure for User 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER5</name>
|
|
<description>Non-Secure for User 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER6</name>
|
|
<description>Non-Secure for User 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER7</name>
|
|
<description>Non-Secure for User 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER8</name>
|
|
<description>Non-Secure for User 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER9</name>
|
|
<description>Non-Secure for User 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER10</name>
|
|
<description>Non-Secure for User 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER11</name>
|
|
<description>Non-Secure for User 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER12</name>
|
|
<description>Non-Secure for User 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER13</name>
|
|
<description>Non-Secure for User 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER14</name>
|
|
<description>Non-Secure for User 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER15</name>
|
|
<description>Non-Secure for User 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER16</name>
|
|
<description>Non-Secure for User 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER17</name>
|
|
<description>Non-Secure for User 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER18</name>
|
|
<description>Non-Secure for User 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER19</name>
|
|
<description>Non-Secure for User 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER20</name>
|
|
<description>Non-Secure for User 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER21</name>
|
|
<description>Non-Secure for User 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER22</name>
|
|
<description>Non-Secure for User 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NSCHKUSER[%s]</name>
|
|
<description>Non-Secure Users Check</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USER0</name>
|
|
<description>User 0 to be checked as non-secured</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER1</name>
|
|
<description>User 1 to be checked as non-secured</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER2</name>
|
|
<description>User 2 to be checked as non-secured</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER3</name>
|
|
<description>User 3 to be checked as non-secured</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER4</name>
|
|
<description>User 4 to be checked as non-secured</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER5</name>
|
|
<description>User 5 to be checked as non-secured</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER6</name>
|
|
<description>User 6 to be checked as non-secured</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER7</name>
|
|
<description>User 7 to be checked as non-secured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER8</name>
|
|
<description>User 8 to be checked as non-secured</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER9</name>
|
|
<description>User 9 to be checked as non-secured</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER10</name>
|
|
<description>User 10 to be checked as non-secured</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER11</name>
|
|
<description>User 11 to be checked as non-secured</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER12</name>
|
|
<description>User 12 to be checked as non-secured</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER13</name>
|
|
<description>User 13 to be checked as non-secured</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER14</name>
|
|
<description>User 14 to be checked as non-secured</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER15</name>
|
|
<description>User 15 to be checked as non-secured</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER16</name>
|
|
<description>User 16 to be checked as non-secured</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER17</name>
|
|
<description>User 17 to be checked as non-secured</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER18</name>
|
|
<description>User 18 to be checked as non-secured</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER19</name>
|
|
<description>User 19 to be checked as non-secured</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER20</name>
|
|
<description>User 20 to be checked as non-secured</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER21</name>
|
|
<description>User 21 to be checked as non-secured</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER22</name>
|
|
<description>User 22 to be checked as non-secured</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="EVSYS">
|
|
<name>EVSYS_SEC</name>
|
|
<prependToName>EVSYS_SEC_</prependToName>
|
|
<baseAddress>0x42000200</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FREQM</name>
|
|
<version>U22572.1.0</version>
|
|
<description>Frequency Meter</description>
|
|
<groupName>FREQM</groupName>
|
|
<prependToName>FREQM_</prependToName>
|
|
<baseAddress>0x40002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FREQM</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGA</name>
|
|
<description>Config A register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REFNUM</name>
|
|
<description>Number of Reference Clock Cycles</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIVREF</name>
|
|
<description>Divide Reference Clock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set Register</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>FREQM Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Sticky Count Value Overflow</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VALUE</name>
|
|
<description>Count Value Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Measurement Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GCLK</name>
|
|
<version>U21221.1.2</version>
|
|
<description>Generic Clock Generator</description>
|
|
<groupName>GCLK</groupName>
|
|
<prependToName>GCLK_</prependToName>
|
|
<baseAddress>0x40001C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x104</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchroniation Busy bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL0</name>
|
|
<description>Generic Clock Generator Control 0 Synchronization Busy bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL1</name>
|
|
<description>Generic Clock Generator Control 1 Synchronization Busy bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL2</name>
|
|
<description>Generic Clock Generator Control 2 Synchronization Busy bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL3</name>
|
|
<description>Generic Clock Generator Control 3 Synchronization Busy bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL4</name>
|
|
<description>Generic Clock Generator Control 4 Synchronization Busy bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GENCTRL[%s]</name>
|
|
<description>Generic Clock Generator Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRC</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>XOSC</name>
|
|
<description>XOSC oscillator output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLKIN</name>
|
|
<description>Generator input pad</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLKGEN1</name>
|
|
<description>Generic clock generator 1 output</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSCULP32K</name>
|
|
<description>OSCULP32K oscillator output</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC32K</name>
|
|
<description>XOSC32K oscillator output</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC16M</name>
|
|
<description>OSC16M oscillator output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DFLLULP</name>
|
|
<description>DFLLULP output</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FDPLL96M</name>
|
|
<description>FDPLL output</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GENEN</name>
|
|
<description>Generic Clock Generator Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDC</name>
|
|
<description>Improve Duty Cycle</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OOV</name>
|
|
<description>Output Off Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIVSEL</name>
|
|
<description>Divide Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Division Factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>21</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PCHCTRL[%s]</name>
|
|
<description>Peripheral Clock Control</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GEN</name>
|
|
<description>Generic Clock Generator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>GENSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK0</name>
|
|
<description>Generic clock generator 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK1</name>
|
|
<description>Generic clock generator 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK2</name>
|
|
<description>Generic clock generator 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK3</name>
|
|
<description>Generic clock generator 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK4</name>
|
|
<description>Generic clock generator 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IDAU</name>
|
|
<version>U28031.0.0</version>
|
|
<description>Implementation Defined Attribution Unit</description>
|
|
<groupName>IDAU</groupName>
|
|
<prependToName>IDAU_</prependToName>
|
|
<baseAddress>0x41000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xD</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SECCTRL</name>
|
|
<description>SECCTRL</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x03</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXN</name>
|
|
<description>CPU RAM is eXecute Never</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGB</name>
|
|
<description>SCFGB</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BS</name>
|
|
<description>Boot Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BNSC</name>
|
|
<description>Boot Secure, Non-secure Callable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOOTPROT</name>
|
|
<description>Boot Protection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGA</name>
|
|
<description>SCFGA</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Application Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANSC</name>
|
|
<description>Application Secure, Non-secure Callable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>DATAFLASH Data Secure</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR</name>
|
|
<description>SCFGR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>RAM Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCLK</name>
|
|
<version>U22343.0.0</version>
|
|
<description>Main Clock</description>
|
|
<groupName>MCLK</groupName>
|
|
<prependToName>MCLK_</prependToName>
|
|
<baseAddress>0x40000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>Clock Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUDIV</name>
|
|
<description>CPU Clock Division</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPUDIV</name>
|
|
<description>CPU Clock Division Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPUDIVSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide by 128</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBMASK</name>
|
|
<description>AHB Mask</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00001FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPB0_</name>
|
|
<description>HPB0 AHB Clock Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB1_</name>
|
|
<description>HPB1 AHB Clock Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB2_</name>
|
|
<description>HPB2 AHB Clock Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC AHB Clock Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU AHB Clock Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC AHB Clock Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL AHB Clock Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAM_</name>
|
|
<description>TRAM AHB Clock Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBAMASK</name>
|
|
<description>APBA Mask</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00007FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC APB Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL APB Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT APB Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT APB Clock Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC APB Clock Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBBMASK</name>
|
|
<description>APBB Mask</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000017</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDAU_</name>
|
|
<description>IDAU APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBCMASK</name>
|
|
<description>APBC Mask</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00001FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 APB Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_</name>
|
|
<description>ADC APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC APB Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTC_</name>
|
|
<description>PTC APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP_</name>
|
|
<description>OPAMP APB Clock Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVMCTRL</name>
|
|
<version>U28021.0.0</version>
|
|
<description>Non-Volatile Memory Controller</description>
|
|
<groupName>NVMCTRL</groupName>
|
|
<prependToName>NVMCTRL_</prependToName>
|
|
<baseAddress>0x41004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>NVMCTRL</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>ER</name>
|
|
<description>Erase Row - Erases the row addressed by the ADDR register.</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WP</name>
|
|
<description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPRM</name>
|
|
<description>Sets the power reduction mode.</description>
|
|
<value>0x42</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPRM</name>
|
|
<description>Clears the power reduction mode.</description>
|
|
<value>0x43</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PBC</name>
|
|
<description>Page Buffer Clear - Clears the page buffer.</description>
|
|
<value>0x44</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALL</name>
|
|
<description>Invalidate all cache lines.</description>
|
|
<value>0x46</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDAL0</name>
|
|
<description>Set DAL=0</description>
|
|
<value>0x4B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDAL1</name>
|
|
<description>Set DAL=1</description>
|
|
<value>0x4C</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEX</name>
|
|
<description>Command Execution</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDEXSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Execution Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RWS</name>
|
|
<description>NVM Read Wait States</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPPRM</name>
|
|
<description>Power Reduction Mode during Sleep</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPPRMSelect</name>
|
|
<enumeratedValue>
|
|
<name>WAKEONACCESS</name>
|
|
<description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKEUPINSTANT</name>
|
|
<description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Auto power reduction disabled.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWUP</name>
|
|
<description>fast wake-up</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READMODE</name>
|
|
<description>NVMCTRL Read Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>READMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO_MISS_PENALTY</name>
|
|
<description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_POWER</name>
|
|
<description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETERMINISTIC</name>
|
|
<description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CACHEDIS</name>
|
|
<description>Cache Disable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QWEN</name>
|
|
<description>Quick Write Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MANW</name>
|
|
<description>Manual Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOWEI</name>
|
|
<description>Auto Write Event Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTOWINV</name>
|
|
<description>Auto Write Event Polarity Inverted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>NVM Done Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error Status Interrupt Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error Status Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEYE</name>
|
|
<description>Key Write Error Interrupt Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>NS configuration change detected Interrupt Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>NVM Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error Status Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error Status Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEYE</name>
|
|
<description>Key Write Error Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>NS configuration change detected Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>NVM Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEYE</name>
|
|
<description>KEY Write Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>NS configuration change detected</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRM</name>
|
|
<description>Power Reduction Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>NVM Page Buffer Active Loading</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY</name>
|
|
<description>NVM Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DALFUSE</name>
|
|
<description>Debug Access Level Fuse</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AOFFSET</name>
|
|
<description>NVM Address Offset In The Selected Array</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARRAY</name>
|
|
<description>Array Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ARRAYSelect</name>
|
|
<enumeratedValue>
|
|
<name>FLASH</name>
|
|
<description>FLASH Array</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATAFLASH</name>
|
|
<description>DATA FLASH Array</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUX</name>
|
|
<description>Auxilliary Space</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SULCK</name>
|
|
<description>Secure Unlock Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>BS</name>
|
|
<description>Secure Boot Region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Secure Application Region</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Data Secure Region</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLKEY</name>
|
|
<description>Write Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLKEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Write Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NSULCK</name>
|
|
<description>Non-Secure Unlock Register</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>BNS</name>
|
|
<description>Non-Secure Boot Region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANS</name>
|
|
<description>Non-Secure Application Region</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DNS</name>
|
|
<description>Non-Secure Data Region</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSLKEY</name>
|
|
<description>Write Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NSLKEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Write Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>NVM Parameter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASHP</name>
|
|
<description>FLASH Pages</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSZ</name>
|
|
<description>Page Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PSZSelect</name>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 bytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 bytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128</name>
|
|
<description>128 bytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256</name>
|
|
<description>256 bytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 bytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 bytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFLASHP</name>
|
|
<description>DATAFLASH Pages</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCC</name>
|
|
<description>Data Scramble Configuration</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DSCKEY</name>
|
|
<description>Data Scramble Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECCTRL</name>
|
|
<description>Security Control</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000030</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPEEN</name>
|
|
<description>Tamper Erase Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SILACC</name>
|
|
<description>Silent Access</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSCEN</name>
|
|
<description>Data Scramble Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DXN</name>
|
|
<description>Data Flash is eXecute Never</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEROW</name>
|
|
<description>Tamper Rease Row</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Key</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Write Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGB</name>
|
|
<description>Secure Boot Configuration</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BCREN</name>
|
|
<description>Boot Configuration Row Read Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCWEN</name>
|
|
<description>Boot Configuration Row Write Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGAD</name>
|
|
<description>Secure Application and Data Configuration</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>URWEN</name>
|
|
<description>User Row Write Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSEC</name>
|
|
<description>Non-secure Write Enable</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Non-secure APB alias write enable, non-secure AHB writes to non-secure regions enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NSCHK</name>
|
|
<description>Non-secure Write Reference Value</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Reference value to be checked against NONSEC.WRITE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="NVMCTRL">
|
|
<name>NVMCTRL_SEC</name>
|
|
<prependToName>NVMCTRL_SEC_</prependToName>
|
|
<baseAddress>0x41005000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OPAMP</name>
|
|
<version>U22372.0.0</version>
|
|
<description>Operational Amplifier</description>
|
|
<groupName>OPAMP</groupName>
|
|
<prependToName>OPAMP_</prependToName>
|
|
<baseAddress>0x42003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x11</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMUX</name>
|
|
<description>Low-Power Mux</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READY0</name>
|
|
<description>OPAMP 0 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY1</name>
|
|
<description>OPAMP 1 Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY2</name>
|
|
<description>OPAMP 2 Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>OPAMPCTRL[%s]</name>
|
|
<description>OPAMP n Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Operational Amplifier Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANAOUT</name>
|
|
<description>Analog Output</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS</name>
|
|
<description>Bias Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES2VCC</name>
|
|
<description>Resistor ladder To VCC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES2OUT</name>
|
|
<description>Resistor ladder To Output</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES1EN</name>
|
|
<description>Resistor 1 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES1MUX</name>
|
|
<description>Resistor 1 Mux</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POTMUX</name>
|
|
<description>Potentiometer Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXPOS</name>
|
|
<description>Positive Input Mux Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXNEG</name>
|
|
<description>Negative Input Mux Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESCTRL</name>
|
|
<description>Resister Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RES2OUT</name>
|
|
<description>Resistor ladder To Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES1EN</name>
|
|
<description>Resistor 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES1MUX</name>
|
|
<description>Resistor 1 Mux</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POTMUX</name>
|
|
<description>Potentiometer Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFBUFLEVEL</name>
|
|
<description>Reference output voltage level select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSCCTRL</name>
|
|
<version>U21194.0.0</version>
|
|
<description>Oscillators Control</description>
|
|
<groupName>OSCCTRL</groupName>
|
|
<prependToName>OSCCTRL_</prependToName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x41</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEO</name>
|
|
<description>Clock Failure Detector Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TUNEEI</name>
|
|
<description>Tune Event Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TUNEINV</name>
|
|
<description>Tune Event Input Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY</name>
|
|
<description>XOSC Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL</name>
|
|
<description>XOSC Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC16MRDY</name>
|
|
<description>OSC16M Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPRDY</name>
|
|
<description>DFLLULP Ready interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPLOCK</name>
|
|
<description>DFLLULP Lock Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPNOLOCK</name>
|
|
<description>DFLLULP No Lock Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKR</name>
|
|
<description>DPLL Lock Rise Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKF</name>
|
|
<description>DPLL Lock Fall Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLTO</name>
|
|
<description>DPLL Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLDRTO</name>
|
|
<description>DPLL Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY</name>
|
|
<description>XOSC Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL</name>
|
|
<description>XOSC Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC16MRDY</name>
|
|
<description>OSC16M Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPRDY</name>
|
|
<description>DFLLULP Ready interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPLOCK</name>
|
|
<description>DFLLULP Lock Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPNOLOCK</name>
|
|
<description>DFLLULP No Lock Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKR</name>
|
|
<description>DPLL Lock Rise Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKF</name>
|
|
<description>DPLL Lock Fall Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLTO</name>
|
|
<description>DPLL Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLDRTO</name>
|
|
<description>DPLL Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY</name>
|
|
<description>XOSC Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL</name>
|
|
<description>XOSC Clock Failure Detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC16MRDY</name>
|
|
<description>OSC16M Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPRDY</name>
|
|
<description>DFLLULP Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPLOCK</name>
|
|
<description>DFLLULP Lock</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPNOLOCK</name>
|
|
<description>DFLLULP No Lock</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKR</name>
|
|
<description>DPLL Lock Rise</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKF</name>
|
|
<description>DPLL Lock Fall</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLTO</name>
|
|
<description>DPLL Lock Timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLDRTO</name>
|
|
<description>DPLL Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY</name>
|
|
<description>XOSC Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL</name>
|
|
<description>XOSC Clock Failure Detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCCKSW</name>
|
|
<description>XOSC Clock Switch</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC16MRDY</name>
|
|
<description>OSC16M Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPRDY</name>
|
|
<description>DFLLULP Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPLOCK</name>
|
|
<description>DFLLULP Lock</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLULPNOLOCK</name>
|
|
<description>DFLLULP No Lock</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKR</name>
|
|
<description>DPLL Lock Rise</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLCKF</name>
|
|
<description>DPLL Lock Fall</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLTO</name>
|
|
<description>DPLL Lock Timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLLDRTO</name>
|
|
<description>DPLL Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XOSCCTRL</name>
|
|
<description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XTALEN</name>
|
|
<description>Crystal Oscillator Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CFDEN</name>
|
|
<description>Clock Failure Detector Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWBEN</name>
|
|
<description>Xosc Clock Switch Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GAIN</name>
|
|
<description>Oscillator Gain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMPGC</name>
|
|
<description>Automatic Amplitude Gain Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Start-Up Time</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFDPRESC</name>
|
|
<description>Clock Failure Detector Prescaler</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDPRESC</name>
|
|
<description>Clock Failure Detector Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC16MCTRL</name>
|
|
<description>16MHz Internal Oscillator (OSC16M) Control</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x82</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>Oscillator Frequency Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>4MHz</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12</name>
|
|
<description>12MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16MHz</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPCTRL</name>
|
|
<description>DFLLULP Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0504</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BINSE</name>
|
|
<description>Binary Search Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAFE</name>
|
|
<description>Tuner Safe Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Tuner Dither Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Division Factor</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIVSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Frequency Divided by 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Frequency Divided by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Frequency Divided by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Frequency Divided by 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Frequency Divided by 16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Frequency Divided by 32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPDITHER</name>
|
|
<description>DFLLULP Dither Control</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>Dither Step</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STEPSelect</name>
|
|
<enumeratedValue>
|
|
<name>STEP1</name>
|
|
<description>Dither Step = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STEP2</name>
|
|
<description>Dither Step = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STEP4</name>
|
|
<description>Dither Step = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STEP8</name>
|
|
<description>Dither Step = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Dither Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PERSelect</name>
|
|
<enumeratedValue>
|
|
<name>PER1</name>
|
|
<description>Dither Over 1 Reference Clock Period</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PER2</name>
|
|
<description>Dither Over 2 Reference Clock Period</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PER4</name>
|
|
<description>Dither Over 4 Reference Clock Period</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PER8</name>
|
|
<description>Dither Over 8 Reference Clock Period</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PER16</name>
|
|
<description>Dither Over 16 Reference Clock Period</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PER32</name>
|
|
<description>Dither Over 32 Reference Clock Period</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPRREQ</name>
|
|
<description>DFLLULP Read Request</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RREQ</name>
|
|
<description>Read Request</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPDLY</name>
|
|
<description>DFLLULP Delay Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPRATIO</name>
|
|
<description>DFLLULP Target Ratio</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RATIO</name>
|
|
<description>Target Tuner Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLULPSYNCBUSY</name>
|
|
<description>DFLLULP Synchronization Busy</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TUNE</name>
|
|
<description>Tune Bit Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay Register Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLCTRLA</name>
|
|
<description>DPLL Control A</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x80</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DPLL Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Clock Activation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLRATIO</name>
|
|
<description>DPLL Ratio Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LDR</name>
|
|
<description>Loop Divider Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDRFRAC</name>
|
|
<description>Loop Divider Ratio Fractional Part</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLCTRLB</name>
|
|
<description>DPLL Control B</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Proportional Integral Filter Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FILTERSelect</name>
|
|
<enumeratedValue>
|
|
<name>Default</name>
|
|
<description>Default Filter Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LBFILT</name>
|
|
<description>Low Bandwidth Filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HBFILT</name>
|
|
<description>High Bandwidth Filter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HDFILT</name>
|
|
<description>High Damping Filter</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPEN</name>
|
|
<description>Low-Power Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>Wake Up Fast</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCLK</name>
|
|
<description>Reference Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFCLKSelect</name>
|
|
<enumeratedValue>
|
|
<name>XOSC32K</name>
|
|
<description>XOSC32K Clock Reference</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC</name>
|
|
<description>XOSC Clock Reference</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>GCLK Clock Reference</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LTIME</name>
|
|
<description>Lock Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LTIMESelect</name>
|
|
<enumeratedValue>
|
|
<name>Default</name>
|
|
<description>No time-out. Automatic lock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8MS</name>
|
|
<description>Time-out if no lock within 8 ms</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9MS</name>
|
|
<description>Time-out if no lock within 9 ms</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10MS</name>
|
|
<description>Time-out if no lock within 10 ms</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11MS</name>
|
|
<description>Time-out if no lock within 11 ms</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBYPASS</name>
|
|
<description>Lock Bypass</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLPRESC</name>
|
|
<description>DPLL Prescaler</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Output Clock Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>DPLL output is divided by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>DPLL output is divided by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>DPLL output is divided by 4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLSYNCBUSY</name>
|
|
<description>DPLL Synchronization Busy</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DPLL Enable Synchronization Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLRATIO</name>
|
|
<description>DPLL Loop Divider Ratio Synchronization Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLPRESC</name>
|
|
<description>DPLL Prescaler Synchronization Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLSTATUS</name>
|
|
<description>DPLL Status</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>DPLL Lock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKRDY</name>
|
|
<description>DPLL Clock Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC32KCTRL</name>
|
|
<version>U22464.0.0</version>
|
|
<description>32k Oscillators Control</description>
|
|
<groupName>OSC32KCTRL</groupName>
|
|
<prependToName>OSC32KCTRL_</prependToName>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Power and Clocks Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSW</name>
|
|
<description>XOSC32K Clock switch</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULP32KSW</name>
|
|
<description>OSCULP32K Clock Switch</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCCTRL</name>
|
|
<description>RTC Clock Selection</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTCSEL</name>
|
|
<description>RTC Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RTCSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>ULP1K</name>
|
|
<description>1.024kHz from 32kHz internal ULP oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULP32K</name>
|
|
<description>32.768kHz from 32kHz internal ULP oscillator</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC1K</name>
|
|
<description>1.024kHz from 32.768kHz internal oscillator</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC32K</name>
|
|
<description>32.768kHz from 32.768kHz internal oscillator</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC1K</name>
|
|
<description>1.024kHz from 32.768kHz internal oscillator</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC32K</name>
|
|
<description>32.768kHz from 32.768kHz external crystal oscillator</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XOSC32K</name>
|
|
<description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XTALEN</name>
|
|
<description>Crystal Oscillator Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN32K</name>
|
|
<description>32kHz Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN1K</name>
|
|
<description>1kHz Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Oscillator Start-Up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFDCTRL</name>
|
|
<description>Clock Failure Detector Control</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEN</name>
|
|
<description>Clock Failure Detector Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWBACK</name>
|
|
<description>Clock Switch Back</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CFDPRESC</name>
|
|
<description>Clock Failure Detector Prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEO</name>
|
|
<description>Clock Failure Detector Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCULP32K</name>
|
|
<description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ULP32KSW</name>
|
|
<description>OSCULP32K Clock Switch Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALIB</name>
|
|
<description>Oscillator Calibration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PAC</name>
|
|
<version>U21202.0.0</version>
|
|
<description>Peripheral Access Controller</description>
|
|
<groupName>PAC</groupName>
|
|
<prependToName>PAC_</prependToName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PAC</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WRCTRL</name>
|
|
<description>Write control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERID</name>
|
|
<description>Peripheral identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Peripheral access control key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR</name>
|
|
<description>Clear protection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set protection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETLCK</name>
|
|
<description>Set and lock protection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETSEC</name>
|
|
<description>Set IP secure</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETNONSEC</name>
|
|
<description>Set IP non-secure</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECLOCK</name>
|
|
<description>Lock IP security value</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERREO</name>
|
|
<description>Peripheral acess error event output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt enable clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Peripheral access error interrupt disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt enable set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Peripheral access error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGAHB</name>
|
|
<description>Bridge interrupt flag status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_</name>
|
|
<description>FLASH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB0_</name>
|
|
<description>HPB0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB1_</name>
|
|
<description>HPB1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB2_</name>
|
|
<description>HPB2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSRAMCPU_</name>
|
|
<description>HSRAMCPU</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSRAMDMAC_</name>
|
|
<description>HSRAMDMAC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSRAMDSU_</name>
|
|
<description>HSRAMDSU</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGA</name>
|
|
<description>Peripheral interrupt flag status - Bridge A</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGB</name>
|
|
<description>Peripheral interrupt flag status - Bridge B</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDAU_</name>
|
|
<description>IDAU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGC</name>
|
|
<description>Peripheral interrupt flag status - Bridge C</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_</name>
|
|
<description>ADC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTC_</name>
|
|
<description>PTC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP_</name>
|
|
<description>OPAMP</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAM_</name>
|
|
<description>TRAM</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSA</name>
|
|
<description>Peripheral write protection status - Bridge A</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000C000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT APB Protect Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT APB Protect Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC APB Protect Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSB</name>
|
|
<description>Peripheral write protection status - Bridge B</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDAU_</name>
|
|
<description>IDAU APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSC</name>
|
|
<description>Peripheral write protection status - Bridge C</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_</name>
|
|
<description>ADC APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC APB Protect Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTC_</name>
|
|
<description>PTC APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP_</name>
|
|
<description>OPAMP APB Protect Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAM_</name>
|
|
<description>TRAM APB Protect Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSECA</name>
|
|
<description>Peripheral non-secure status - Bridge A</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC Non-Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM Non-Secure</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK Non-Secure</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC Non-Secure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL Non-Secure</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL Non-Secure</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC Non-Secure</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK Non-Secure</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT Non-Secure</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC Non-Secure</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC Non-Secure</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM Non-Secure</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT Non-Secure</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC Non-Secure</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSECB</name>
|
|
<description>Peripheral non-secure status - Bridge B</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDAU_</name>
|
|
<description>IDAU Non-Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU Non-Secure</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL Non-Secure</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC Non-Secure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSECC</name>
|
|
<description>Peripheral non-secure status - Bridge C</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS Non-Secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 Non-Secure</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 Non-Secure</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 Non-Secure</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 Non-Secure</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 Non-Secure</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_</name>
|
|
<description>ADC Non-Secure</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC Non-Secure</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTC_</name>
|
|
<description>PTC Non-Secure</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG Non-Secure</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL Non-Secure</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP_</name>
|
|
<description>OPAMP Non-Secure</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAM_</name>
|
|
<description>TRAM Non-Secure</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECLOCKA</name>
|
|
<description>Peripheral secure status locked - Bridge A</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC Secure Status Locked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM Secure Status Locked</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK Secure Status Locked</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC Secure Status Locked</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL Secure Status Locked</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL Secure Status Locked</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC Secure Status Locked</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK Secure Status Locked</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT Secure Status Locked</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC Secure Status Locked</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC Secure Status Locked</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM Secure Status Locked</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT Secure Status Locked</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC Secure Status Locked</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECLOCKB</name>
|
|
<description>Peripheral secure status locked - Bridge B</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDAU_</name>
|
|
<description>IDAU Secure Status Locked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU Secure Status Locked</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL Secure Status Locked</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC Secure Status Locked</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECLOCKC</name>
|
|
<description>Peripheral secure status locked - Bridge C</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS Secure Status Locked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 Secure Status Locked</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 Secure Status Locked</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 Secure Status Locked</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 Secure Status Locked</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 Secure Status Locked</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_</name>
|
|
<description>ADC Secure Status Locked</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC Secure Status Locked</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTC_</name>
|
|
<description>PTC Secure Status Locked</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG Secure Status Locked</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL Secure Status Locked</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAMP_</name>
|
|
<description>OPAMP Secure Status Locked</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRAM_</name>
|
|
<description>TRAM Secure Status Locked</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PAC">
|
|
<name>PAC_SEC</name>
|
|
<prependToName>PAC_SEC_</prependToName>
|
|
<baseAddress>0x40000200</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PM</name>
|
|
<version>U22403.1.0</version>
|
|
<description>Power Manager</description>
|
|
<groupName>PM</groupName>
|
|
<prependToName>PM_</prependToName>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SLEEPCFG</name>
|
|
<description>Sleep Configuration</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x02</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPMODE</name>
|
|
<description>Sleep Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>CPU, AHB, APB clocks are OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>All Clocks are OFF</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All power domains are powered OFF</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLCFG</name>
|
|
<description>Performance Level Configuration</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLSEL</name>
|
|
<description>Performance Level Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PLSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>PL0</name>
|
|
<description>Performance Level 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PL2</name>
|
|
<description>Performance Level 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLDIS</name>
|
|
<description>Performance Level Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWCFG</name>
|
|
<description>Power Configuration</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAMPSWC</name>
|
|
<description>RAM Power Switch Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RAMPSWCSelect</name>
|
|
<enumeratedValue>
|
|
<name>16KB</name>
|
|
<description>16KB Available</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12KB</name>
|
|
<description>12KB Available</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8KB</name>
|
|
<description>8KB Available</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4KB</name>
|
|
<description>4KB Available</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLRDY</name>
|
|
<description>Performance Level Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLRDY</name>
|
|
<description>Performance Level Ready interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLRDY</name>
|
|
<description>Performance Level Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STDBYCFG</name>
|
|
<description>Standby Configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PDCFG</name>
|
|
<description>Power Domain Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PDCFGSelect</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>PDSW power domain switching is handled by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDSW</name>
|
|
<description>PDSW is forced ACTIVE.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPGPDSW</name>
|
|
<description>Dynamic Power Gating for PDSW</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DPGPDSWSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Dynamic Power Gating disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Dynamic Power Gating enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREGSMOD</name>
|
|
<description>Voltage Regulator Standby mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>VREGSMODSelect</name>
|
|
<enumeratedValue>
|
|
<name>AUTO</name>
|
|
<description>Automatic mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERFORMANCE</name>
|
|
<description>Performance oriented</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LP</name>
|
|
<description>Low Power oriented</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBIASHS</name>
|
|
<description>Back Bias for HSRAM</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBIASTR</name>
|
|
<description>Back Bias for Trust RAM</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORT</name>
|
|
<version>U22103.0.0</version>
|
|
<description>Port Module</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORT_</prependToName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORT</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<dim>1</dim>
|
|
<dimIncrement>0x80</dimIncrement>
|
|
<name>GROUP[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x00</addressOffset>
|
|
<register>
|
|
<name>DIR</name>
|
|
<description>Data Direction</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRCLR</name>
|
|
<description>Data Direction Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRCLR</name>
|
|
<description>Port Data Direction Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRSET</name>
|
|
<description>Data Direction Set</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRSET</name>
|
|
<description>Port Data Direction Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRTGL</name>
|
|
<description>Data Direction Toggle</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRTGL</name>
|
|
<description>Port Data Direction Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT</name>
|
|
<description>Data Output Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>PORT Data Output Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTCLR</name>
|
|
<description>Data Output Value Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTCLR</name>
|
|
<description>PORT Data Output Value Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTSET</name>
|
|
<description>Data Output Value Set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTSET</name>
|
|
<description>PORT Data Output Value Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTTGL</name>
|
|
<description>Data Output Value Toggle</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTTGL</name>
|
|
<description>PORT Data Output Value Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN</name>
|
|
<description>Data Input Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN</name>
|
|
<description>PORT Data Input Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLING</name>
|
|
<description>Input Sampling Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRCONFIG</name>
|
|
<description>Write Configuration</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PINMASK</name>
|
|
<description>Pin Mask for Multiple Pin Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUXEN</name>
|
|
<description>Peripheral Multiplexer Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PULLEN</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRVSTR</name>
|
|
<description>Output Driver Strength Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUX</name>
|
|
<description>Peripheral Multiplexing</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRPMUX</name>
|
|
<description>Write PMUX</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRPINCFG</name>
|
|
<description>Write PINCFG</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HWSEL</name>
|
|
<description>Half-Word Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Input Control</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PID0</name>
|
|
<description>PORT Event Pin Identifier 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT0</name>
|
|
<description>PORT Event Action 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACT0Select</name>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Event output to pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output register of pin on event</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR</name>
|
|
<description>Clear output register of pin on event</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TGL</name>
|
|
<description>Toggle output register of pin on event</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI0</name>
|
|
<description>PORT Event Input Enable 0</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID1</name>
|
|
<description>PORT Event Pin Identifier 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT1</name>
|
|
<description>PORT Event Action 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI1</name>
|
|
<description>PORT Event Input Enable 1</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID2</name>
|
|
<description>PORT Event Pin Identifier 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT2</name>
|
|
<description>PORT Event Action 2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI2</name>
|
|
<description>PORT Event Input Enable 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID3</name>
|
|
<description>PORT Event Pin Identifier 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT3</name>
|
|
<description>PORT Event Action 3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI3</name>
|
|
<description>PORT Event Input Enable 3</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>PMUX[%s]</name>
|
|
<description>Peripheral Multiplexing</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMUXE</name>
|
|
<description>Peripheral Multiplexing for Even-Numbered Pin</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUXO</name>
|
|
<description>Peripheral Multiplexing for Odd-Numbered Pin</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>PINCFG[%s]</name>
|
|
<description>Pin Configuration</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMUXEN</name>
|
|
<description>Peripheral Multiplexer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PULLEN</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRVSTR</name>
|
|
<description>Output Driver Strength Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Non-Secure Check</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NONSEC</name>
|
|
<description>Security Attribution</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NONSEC</name>
|
|
<description>Port Security Attribution</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NSCHK</name>
|
|
<description>Security Attribution Check</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NSCHK</name>
|
|
<description>Port Security Attribution Check</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT">
|
|
<name>PORT_SEC</name>
|
|
<prependToName>PORT_SEC_</prependToName>
|
|
<baseAddress>0x40003200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT">
|
|
<name>PORT_IOBUS</name>
|
|
<prependToName>PORT_IOBUS_</prependToName>
|
|
<baseAddress>0x60000000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT">
|
|
<name>PORT_IOBUS_SEC</name>
|
|
<prependToName>PORT_IOBUS_SEC_</prependToName>
|
|
<baseAddress>0x60000200</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PTC</name>
|
|
<version>U22155.0.0</version>
|
|
<description>Peripheral Touch Controller</description>
|
|
<groupName>PTC</groupName>
|
|
<prependToName>PTC_</prependToName>
|
|
<baseAddress>0x42002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PTC</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RSTC</name>
|
|
<version>U22393.0.0</version>
|
|
<description>Reset Controller</description>
|
|
<groupName>RSTC</groupName>
|
|
<prependToName>RSTC_</prependToName>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RCAUSE</name>
|
|
<description>Reset Cause</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power On Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BODCORE</name>
|
|
<description>Brown Out CORE Detector Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BODVDD</name>
|
|
<description>Brown Out VDD Detector Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Watchdog Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYST</name>
|
|
<description>System Reset Request</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<version>U22503.0.0</version>
|
|
<description>Real-Time Counter</description>
|
|
<groupName>RTC</groupName>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x40002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>MODE0</name>
|
|
<description>32-bit Counter with Single 32-bit Compare</description>
|
|
<headerStructName>RtcMode0</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE0 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCHCLR</name>
|
|
<description>Clear on Match</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE0 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Frequency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEPTO</name>
|
|
<description>Separate Tamper Outputs</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE0 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO0</name>
|
|
<description>Compare 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERDEO</name>
|
|
<description>Periodic Interval Daily Event Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE0 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE0 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE0 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE0 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>COUNT Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>MODE0 Counter Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>COMP[%s]</name>
|
|
<description>MODE0 Compare n Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE0 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRLB</name>
|
|
<description>Tamper Control B</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALSI0</name>
|
|
<description>Active Layer Select Internal 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI1</name>
|
|
<description>Active Layer Select Internal 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI2</name>
|
|
<description>Active Layer Select Internal 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI3</name>
|
|
<description>Active Layer Select Internal 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>MODE1</name>
|
|
<description>16-bit Counter with Two 16-bit Compares</description>
|
|
<alternateCluster>MODE0</alternateCluster>
|
|
<headerStructName>RtcMode1</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE1 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE1 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Frequency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEPTO</name>
|
|
<description>Separate Tamper Outputs</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE1 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO0</name>
|
|
<description>Compare 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO1</name>
|
|
<description>Compare 1 Event Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERDEO</name>
|
|
<description>Periodic Interval Daily Event Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE1 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE1 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE1 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE1 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Bit Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>COUNT Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>COMP 1 Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>MODE1 Counter Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>MODE1 Counter Period</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Counter Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>COMP[%s]</name>
|
|
<description>MODE1 Compare n Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE1 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRLB</name>
|
|
<description>Tamper Control B</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALSI0</name>
|
|
<description>Active Layer Select Internal 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI1</name>
|
|
<description>Active Layer Select Internal 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI2</name>
|
|
<description>Active Layer Select Internal 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI3</name>
|
|
<description>Active Layer Select Internal 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>MODE2</name>
|
|
<description>Clock/Calendar with Alarm</description>
|
|
<alternateCluster>MODE0</alternateCluster>
|
|
<headerStructName>RtcMode2</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE2 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKREP</name>
|
|
<description>Clock Representation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHCLR</name>
|
|
<description>Clear on Match</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCKSYNC</name>
|
|
<description>Clock Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE2 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Frequency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEPTO</name>
|
|
<description>Separate Tamper Outputs</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE2 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARMEO0</name>
|
|
<description>Alarm 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERDEO</name>
|
|
<description>Periodic Interval Daily Event Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE2 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE2 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE2 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE2 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Bit Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCK</name>
|
|
<description>CLOCK Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>ALARM 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASK0</name>
|
|
<description>MASK 0 Register Busy</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCKSYNC</name>
|
|
<description>Clock Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK</name>
|
|
<description>MODE2 Clock Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>1</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<name>MODE2_ALARM[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x20</addressOffset>
|
|
<register>
|
|
<name>ALARM</name>
|
|
<description>MODE2_ALARM Alarm n Value</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HOURSelect</name>
|
|
<enumeratedValue>
|
|
<name>AM</name>
|
|
<description>Morning hour</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM</name>
|
|
<description>Afternoon hour</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK</name>
|
|
<description>MODE2_ALARM Alarm n Mask</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Alarm Mask Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Alarm Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SS</name>
|
|
<description>Match seconds only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMSS</name>
|
|
<description>Match seconds and minutes only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HHMMSS</name>
|
|
<description>Match seconds, minutes, and hours only</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, and days only</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, and months only</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YYMMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, months, and years</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake and set Tamper flag</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp and set Tamper flag</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE2 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute Timestamp Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour Timestamp Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day Timestamp Value</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month Timestamp Value</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year Timestamp Value</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRLB</name>
|
|
<description>Tamper Control B</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALSI0</name>
|
|
<description>Active Layer Select Internal 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI1</name>
|
|
<description>Active Layer Select Internal 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI2</name>
|
|
<description>Active Layer Select Internal 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALSI3</name>
|
|
<description>Active Layer Select Internal 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SERCOM0</name>
|
|
<version>U22014.1.0</version>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>SERCOM</groupName>
|
|
<prependToName>SERCOM_</prependToName>
|
|
<baseAddress>0x42000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x31</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SERCOM0_0</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_1</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_2</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_OTHER</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>I2CM</name>
|
|
<description>I2C Master Mode</description>
|
|
<headerStructName>SercomI2cm</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>I2CM Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINOUT</name>
|
|
<description>Pin Usage</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDAHOLD</name>
|
|
<description>SDA Hold Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEXTTOEN</name>
|
|
<description>Master SCL Low Extend Timeout</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOEN</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Transfer Speed</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLSM</name>
|
|
<description>SCL Clock Stretch Mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INACTOUT</name>
|
|
<description>Inactive Time-Out</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUTEN</name>
|
|
<description>SCL Low Timeout Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>I2CM Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEN</name>
|
|
<description>Smart Mode Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QCEN</name>
|
|
<description>Quick Command Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKACT</name>
|
|
<description>Acknowledge Action</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>I2CM Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BAUDLOW</name>
|
|
<description>Baud Rate Value Low</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSBAUD</name>
|
|
<description>High Speed Baud Rate Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSBAUDLOW</name>
|
|
<description>High Speed Baud Rate Value Low</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>I2CM Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>I2CM Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>I2CM Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>I2CM Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNACK</name>
|
|
<description>Received Not Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSSTATE</name>
|
|
<description>Bus State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUT</name>
|
|
<description>SCL Low Timeout</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEXTTOUT</name>
|
|
<description>Master SCL Low Extend Timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOUT</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENERR</name>
|
|
<description>Length Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>I2CM Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSOP</name>
|
|
<description>System Operation Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>I2CM Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Length Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>High Speed Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TENBITEN</name>
|
|
<description>Ten Bit Addressing Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>I2CM Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>I2CM Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>I2CS</name>
|
|
<description>I2C Slave Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomI2cs</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>I2CS Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINOUT</name>
|
|
<description>Pin Usage</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDAHOLD</name>
|
|
<description>SDA Hold Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOEN</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Transfer Speed</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLSM</name>
|
|
<description>SCL Clock Stretch Mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUTEN</name>
|
|
<description>SCL Low Timeout Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>I2CS Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEN</name>
|
|
<description>Smart Mode Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCMD</name>
|
|
<description>PMBus Group Command</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AACKEN</name>
|
|
<description>Automatic Address Acknowledge</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMODE</name>
|
|
<description>Address Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKACT</name>
|
|
<description>Acknowledge Action</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>I2CS Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>I2CS Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>I2CS Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>I2CS Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLL</name>
|
|
<description>Transmit Collision</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNACK</name>
|
|
<description>Received Not Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Read/Write Direction</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Repeated Start</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUT</name>
|
|
<description>SCL Low Timeout</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOUT</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>High Speed</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>I2CS Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>I2CS Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GENCEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TENBITEN</name>
|
|
<description>Ten Bit Addressing Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRMASK</name>
|
|
<description>Address Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>I2CS Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>SPI</name>
|
|
<description>SPI Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomSpi</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>SPI Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOPO</name>
|
|
<description>Data Out Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIPO</name>
|
|
<description>Data In Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>SPI Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLOADEN</name>
|
|
<description>Data Preload Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSDE</name>
|
|
<description>Slave Select Low Detect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSSEN</name>
|
|
<description>Master Slave Select Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMODE</name>
|
|
<description>Address Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>SPI Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>SPI Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>SPI Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>SPI Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>SPI Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>SPI Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>SPI Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRMASK</name>
|
|
<description>Address Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>SPI Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>SPI Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>USART</name>
|
|
<description>USART Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomUsart</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>USART Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Invert</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Invert</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPR</name>
|
|
<description>Sample</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXPO</name>
|
|
<description>Transmit Data Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXPO</name>
|
|
<description>Receive Data Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPA</name>
|
|
<description>Sample Adjustment</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMODE</name>
|
|
<description>Communication Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>USART Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMODE</name>
|
|
<description>Stop Bit Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLDEN</name>
|
|
<description>Collision Detection Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFDE</name>
|
|
<description>Start of Frame Detection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENC</name>
|
|
<description>Encoding Format</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Parity Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINCMD</name>
|
|
<description>LIN Command</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>USART Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GTIME</name>
|
|
<description>Guard Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKLEN</name>
|
|
<description>LIN Master Break Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDRDLY</name>
|
|
<description>LIN Master Header Delay</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INACK</name>
|
|
<description>Inhibit Not Acknowledge</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSNACK</name>
|
|
<description>Disable Successive NACK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAXITER</name>
|
|
<description>Maximum Iterations</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>USART Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRAC_MODE</name>
|
|
<description>USART Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRACFP_MODE</name>
|
|
<description>USART Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_USARTFP_MODE</name>
|
|
<description>USART Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPL</name>
|
|
<description>USART Receive Pulse Length</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPL</name>
|
|
<description>Receive Pulse Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>USART Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>USART Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>USART Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Frame Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Inconsistent Sync Field</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLL</name>
|
|
<description>Collision Detected</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmitter Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Maximum Number of Repetitions Reached</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>USART Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXERRCNT</name>
|
|
<description>RXERRCNT Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXERRCNT</name>
|
|
<description>USART Receive Error Count</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>USART Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>USART Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM1</name>
|
|
<baseAddress>0x42000800</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM1_0</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_1</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_2</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_OTHER</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SUPC</name>
|
|
<version>U21174.0.0</version>
|
|
<description>Supply Controller</description>
|
|
<groupName>SUPC</groupName>
|
|
<prependToName>SUPC_</prependToName>
|
|
<baseAddress>0x40001800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12RDY</name>
|
|
<description>BOD12 Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12DET</name>
|
|
<description>BOD12 Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B12SRDY</name>
|
|
<description>BOD12 Synchronization Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULPVREFRDY</name>
|
|
<description>ULPVREF Voltage Reference Ready</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12RDY</name>
|
|
<description>BOD12 Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12DET</name>
|
|
<description>BOD12 Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B12SRDY</name>
|
|
<description>BOD12 Synchronization Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULPVREFRDY</name>
|
|
<description>ULPVREF Voltage Reference Ready</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12RDY</name>
|
|
<description>BOD12 Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12DET</name>
|
|
<description>BOD12 Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B12SRDY</name>
|
|
<description>BOD12 Synchronization Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULPVREFRDY</name>
|
|
<description>ULPVREF Voltage Reference Ready</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Power and Clocks Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12RDY</name>
|
|
<description>BOD12 Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12DET</name>
|
|
<description>BOD12 Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B12SRDY</name>
|
|
<description>BOD12 Synchronization Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULPVREFRDY</name>
|
|
<description>Low Power Voltage Reference Ready</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ULPBIASRDY</name>
|
|
<description>Low Power Voltage Bias Ready</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOD33</name>
|
|
<description>BOD33 Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTION</name>
|
|
<description>Action when Threshold Crossed</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTIONSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>The BOD33 generates a reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>The BOD33 generates an interrupt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BKUP</name>
|
|
<description>The BOD33 puts the device in backup sleep mode if VMON=0</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDBYCFG</name>
|
|
<description>Configuration in Standby mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTCFG</name>
|
|
<description>Configuration in Active mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>BOD33 Voltage Reference Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>SEL_VREFDETREF</name>
|
|
<description>Selects VREFDETREF for the BOD33</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEL_ULPVREF</name>
|
|
<description>Selects ULPVREF for the BOD33</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Prescaler Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide clock by 2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide clock by 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide clock by 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide clock by 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide clock by 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide clock by 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide clock by 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide clock by 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>Divide clock by 512</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Divide clock by 1024</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2048</name>
|
|
<description>Divide clock by 2048</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4096</name>
|
|
<description>Divide clock by 4096</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8192</name>
|
|
<description>Divide clock by 8192</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16384</name>
|
|
<description>Divide clock by 16384</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32768</name>
|
|
<description>Divide clock by 32768</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV65536</name>
|
|
<description>Divide clock by 65536</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Threshold Level for VDD</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOD12</name>
|
|
<description>BOD12 Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTION</name>
|
|
<description>Action when Threshold Crossed</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTIONSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>The BOD12 generates a reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>The BOD12 generates an interrupt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDBYCFG</name>
|
|
<description>Configuration in Standby mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTCFG</name>
|
|
<description>Configuration in Active mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Prescaler Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide clock by 2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide clock by 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide clock by 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide clock by 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide clock by 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide clock by 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide clock by 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide clock by 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>Divide clock by 512</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Divide clock by 1024</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2048</name>
|
|
<description>Divide clock by 2048</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4096</name>
|
|
<description>Divide clock by 4096</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8192</name>
|
|
<description>Divide clock by 8192</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16384</name>
|
|
<description>Divide clock by 16384</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32768</name>
|
|
<description>Divide clock by 32768</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV65536</name>
|
|
<description>Divide clock by 65536</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Threshold Level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREG</name>
|
|
<description>VREG Control</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Voltage Regulator Selection in active mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>LDO</name>
|
|
<description>LDO selection</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCK</name>
|
|
<description>Buck selection</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDBYPL0</name>
|
|
<description>Standby in PL0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPEFF</name>
|
|
<description>Low Power efficiency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREFSEL</name>
|
|
<description>Voltage Regulator Voltage Reference Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSVSTEP</name>
|
|
<description>Voltage Scaling Voltage Step</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSPER</name>
|
|
<description>Voltage Scaling Period</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREF</name>
|
|
<description>VREF Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Temperature Sensor Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREFOE</name>
|
|
<description>Voltage Reference Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSSEL</name>
|
|
<description>Temperature Sensor Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>1V0</name>
|
|
<description>1.0V voltage reference typical value</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V1</name>
|
|
<description>1.1V voltage reference typical value</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V2</name>
|
|
<description>1.2V voltage reference typical value</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>1.25V voltage reference typical value</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V0</name>
|
|
<description>2.0V voltage reference typical value</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V2</name>
|
|
<description>2.2V voltage reference typical value</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V4</name>
|
|
<description>2.4V voltage reference typical value</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>2.5V voltage reference typical value</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33DETEO</name>
|
|
<description>BOD33 Detection Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD12DETEO</name>
|
|
<description>BOD12 Detection Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREGSUSP</name>
|
|
<description>VREG Suspend Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VREGSEN</name>
|
|
<description>Enable Voltage Regulator Suspend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TC0</name>
|
|
<version>U22493.1.0</version>
|
|
<description>Basic Timer Counter</description>
|
|
<groupName>TC</groupName>
|
|
<prependToName>TC_</prependToName>
|
|
<baseAddress>0x42001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TC0</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>COUNT8</name>
|
|
<description>8-bit Counter Mode</description>
|
|
<headerStructName>TcCount8</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT8 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>COUNT8 Period</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT8 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF</name>
|
|
<description>COUNT8 Period Buffer</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT8 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>COUNT16</name>
|
|
<description>16-bit Counter Mode</description>
|
|
<alternateCluster>COUNT8</alternateCluster>
|
|
<headerStructName>TcCount16</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT16 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>COUNT16 Period</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT16 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF</name>
|
|
<description>COUNT16 Period Buffer</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT16 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>COUNT32</name>
|
|
<description>32-bit Counter Mode</description>
|
|
<alternateCluster>COUNT8</alternateCluster>
|
|
<headerStructName>TcCount32</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT32 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>COUNT32 Period</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT32 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF</name>
|
|
<description>COUNT32 Period Buffer</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT32 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC1</name>
|
|
<baseAddress>0x42001400</baseAddress>
|
|
<interrupt>
|
|
<name>TC1</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC2</name>
|
|
<baseAddress>0x42001800</baseAddress>
|
|
<interrupt>
|
|
<name>TC2</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRAM</name>
|
|
<version>U28011.0.0</version>
|
|
<description>TrustRAM</description>
|
|
<groupName>TRAM</groupName>
|
|
<prependToName>TRAM_</prependToName>
|
|
<baseAddress>0x42003400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x290</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRAM</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPERS</name>
|
|
<description>Tamper Erase</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>Data Remanence Prevention</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SILACC</name>
|
|
<description>Silent Access</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>TrustRAM Readout Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>Data Remanence Prevention Ended Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>TrustRAM Readout Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>Data Remanence Prevention Ended Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>TrustRAM Readout Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>Data Remanence Prevention Ended</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAMINV</name>
|
|
<description>RAM Inversion Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>Data Remanence Prevention Ongoing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCC</name>
|
|
<description>Data Scramble Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DSCKEY</name>
|
|
<description>Data Scramble Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSCEN</name>
|
|
<description>Data Scramble Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERMW</name>
|
|
<description>Permutation Write</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Permutation Scrambler Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERMR</name>
|
|
<description>Permutation Read</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Permutation Scrambler Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>64</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>RAM[%s]</name>
|
|
<description>TrustRAM</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Trust RAM Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<version>U22421.2.0</version>
|
|
<description>True Random Generator</description>
|
|
<groupName>TRNG</groupName>
|
|
<prependToName>TRNG_</prependToName>
|
|
<baseAddress>0x42002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDYEO</name>
|
|
<description>Data Ready Event Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<version>U22512.0.0</version>
|
|
<description>Watchdog Timer</description>
|
|
<groupName>WDT</groupName>
|
|
<prependToName>WDT_</prependToName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xD</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDT</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WEN</name>
|
|
<description>Watchdog Timer Window Mode Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run During Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALWAYSON</name>
|
|
<description>Always-On</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xBB</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Time-Out Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PERSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Window Mode Time-Out Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WINDOWSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EWCTRL</name>
|
|
<description>Early Warning Interrupt Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWOFFSET</name>
|
|
<description>Early Warning Interrupt Time Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EWOFFSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WEN</name>
|
|
<description>Window Enable Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run During Standby Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALWAYSON</name>
|
|
<description>Always-On Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Clear Synchronization Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Watchdog Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLEARSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Clear Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CoreDebug</name>
|
|
<description>Debug Control Block</description>
|
|
<groupName>CoreDebug</groupName>
|
|
<prependToName>CoreDebug_</prependToName>
|
|
<baseAddress>0xE000EDF0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DHCSR</name>
|
|
<description>Debug Halting Control and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>C_DEBUGEN</name>
|
|
<description>Enable Halting debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_HALT</name>
|
|
<description>Halt processor</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_STEP</name>
|
|
<description>Enable single step</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_MASKINTS</name>
|
|
<description>Mask PendSV, SysTick and external configurable interrupts</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_SNAPSTALL</name>
|
|
<description>Snap stall control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_REGRDY</name>
|
|
<description>Register ready status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_HALT</name>
|
|
<description>Halted status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_SLEEP</name>
|
|
<description>Sleeping status</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_LOCKUP</name>
|
|
<description>Lockup status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_SDE</name>
|
|
<description>Secure debug enabled</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_RETIRE_ST</name>
|
|
<description>Retire sticky status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_RESET_ST</name>
|
|
<description>Reset sticky status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_RESTART_ST</name>
|
|
<description>Restart sticky status</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRSR</name>
|
|
<description>Debug Core Register Select Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>REGSEL</name>
|
|
<description>Register selector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REGWnR</name>
|
|
<description>Register write/not-read access</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEMCR</name>
|
|
<description>Debug Exception and Monitor Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VC_CORERESET</name>
|
|
<description>Core reset Halting debug vector catch enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_MMERR</name>
|
|
<description>MemManage exception Halting debug vector catch enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_NOCPERR</name>
|
|
<description>UsageFault exception coprocessor access Halting debug vector catch enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_CHKERR</name>
|
|
<description>UsageFault exception checking error Halting debug vector catch enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_STATERR</name>
|
|
<description>UsageFault exception state information error Halting debug vector catch enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_BUSERR</name>
|
|
<description>BusFault exception Halting debug vector catch enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_INTERR</name>
|
|
<description>Excception entry and return faults Halting debug vector catch enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_HARDERR</name>
|
|
<description>HardFault exception Halting debug vector catch enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_SFERR</name>
|
|
<description>SecureFault exception Halting debug vector catch enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_EN</name>
|
|
<description>DebugMonitor enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_PEND</name>
|
|
<description>DebugMonitor pending state</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_STEP</name>
|
|
<description>Enable DebugMonitor stepping</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_REQ</name>
|
|
<description>DebugMonitor semaphore bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDME</name>
|
|
<description>Secure DebugMonitor enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCENA</name>
|
|
<description>Global DWT and ITM features enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAUTHCTRL</name>
|
|
<description>Debug Authentication Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SPIDENSEL</name>
|
|
<description>Secure invasive debug enable select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTSPIDEN</name>
|
|
<description>Internal Secure invasive debug enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPNIDENSEL</name>
|
|
<description>Secure non-invasive debug enable select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTSPNIDEN</name>
|
|
<description>Internal Secure non-invasive debug enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCSR</name>
|
|
<description>Debug Security Control and Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SBRSELEN</name>
|
|
<description>Secure Banked register select enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBRSEL</name>
|
|
<description>Secure Banked register select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDS</name>
|
|
<description>Current domain Secure</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDSKEY</name>
|
|
<description>CDS field write-enable key</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CoreDebug">
|
|
<name>CoreDebug_NS</name>
|
|
<baseAddress>0xE002EDF0</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DIB</name>
|
|
<description>Debug Identification Block</description>
|
|
<groupName>DIB</groupName>
|
|
<prependToName>DIB_</prependToName>
|
|
<baseAddress>0xE000EFB0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x50</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DLAR</name>
|
|
<description>SCS Software Lock Access Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Lock access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>UNLOCK</name>
|
|
<description>Unlock key value</description>
|
|
<value>0xC5ACCE55</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLSR</name>
|
|
<description>SCS Software Lock Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>Software Lock implemented</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLK</name>
|
|
<description>Software Lock status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nTT</name>
|
|
<description>Not thirty-two bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAUTHSTATUS</name>
|
|
<description>Debug Authentication Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>NSID</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NSIDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Non-secure invasive debug prohibited</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Non-secure invasive debug allowed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSNID</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NSNIDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Non-secure non-invasive debug prohibited</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Non-secure non-invasive debug allowed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SID</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SIDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOSEC</name>
|
|
<description>Security Extension not implemented</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Secure invasive debug prohibited</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Secure invasive debug allowed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNID</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SNIDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOSEC</name>
|
|
<description>Security Extension not implemented</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Secure non-invasive debug prohibited</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Secure non-invasive debug allowed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DDEVARCH</name>
|
|
<description>SCS Device Architecture Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x47702A04</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARCHPART</name>
|
|
<description>Architecture Part</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHVER</name>
|
|
<description>Architecture Version</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT</name>
|
|
<description>DEVARCH Present</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHITECT</name>
|
|
<description>Architect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DDEVTYPE</name>
|
|
<description>SCS Device Type Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUB</name>
|
|
<description>Sub-type</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR4</name>
|
|
<description>SCS Peripheral Identification Register 4</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_2</name>
|
|
<description>JEP106 continuation code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>4KB count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR5</name>
|
|
<description>SCS Peripheral Identification Register 5</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR6</name>
|
|
<description>SCS Peripheral Identification Register 6</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR7</name>
|
|
<description>SCS Peripheral Identification Register 7</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR0</name>
|
|
<description>SCS Peripheral Identification Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_0</name>
|
|
<description>Part number bits[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR1</name>
|
|
<description>SCS Peripheral Identification Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_1</name>
|
|
<description>Part number bits[11:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DES_0</name>
|
|
<description>JEP106 identification code bits [3:0]</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR2</name>
|
|
<description>SCS Peripheral Identification Register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_1</name>
|
|
<description>JEP106 identification code bits[6:4]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEDEC</name>
|
|
<description>JEDEC assignee value is used</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Component revision</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPIDR3</name>
|
|
<description>SCS Peripheral Identification Register 3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>Customer Modified</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>RevAnd</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIDR0</name>
|
|
<description>SCS Component Identification Register 0</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_0</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIDR1</name>
|
|
<description>SCS Component Identification Register 1</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_1</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLASS</name>
|
|
<description>CoreSight component class</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIDR2</name>
|
|
<description>SCS Component Identification Register 2</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_2</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIDR3</name>
|
|
<description>SCS Component Identification Register 3</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_3</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DIB">
|
|
<name>DIB_NS</name>
|
|
<baseAddress>0xE002EFB0</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DWT</name>
|
|
<description>Data Watchpoint and Trace</description>
|
|
<groupName>DWT</groupName>
|
|
<prependToName>DWT_</prependToName>
|
|
<baseAddress>0xE0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DWT_CTRL</name>
|
|
<description>DWT Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x0B000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CYCCNTENA</name>
|
|
<description>CYCCNT enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POSTPRESET</name>
|
|
<description>POSTCNT preset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POSTINIT</name>
|
|
<description>POSTCNT initial</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCTAP</name>
|
|
<description>Cycle count tap</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCTAP</name>
|
|
<description>Synchronization tap</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCSAMPLENA</name>
|
|
<description>PC sample enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXCTRCENA</name>
|
|
<description>Exception trace enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPIEVTENA</name>
|
|
<description>CPI event enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXCEVTENA</name>
|
|
<description>Exception event enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPEVTENA</name>
|
|
<description>Sleep event enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSUEVTENA</name>
|
|
<description>LSU event enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FOLDEVTENA</name>
|
|
<description>Fold event enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCEVTENA</name>
|
|
<description>Cycle event enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCDISS</name>
|
|
<description>Cycle counter disabled secure</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOPRFCNT</name>
|
|
<description>No profile counters</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOCYCCNT</name>
|
|
<description>No cycle count</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOEXTTRIG</name>
|
|
<description>No external triggers</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOTRCPKT</name>
|
|
<description>No trace packets</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NUMCOMP</name>
|
|
<description>Number of comparators</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PCSR</name>
|
|
<description>DWT Program Counter Sample Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EIASAMPLE</name>
|
|
<description>Executed instruction address sample</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<name>COMPARATOR[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x020</addressOffset>
|
|
<register>
|
|
<name>DWT_COMP</name>
|
|
<description>DWT Comparator Register n</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Cycle/PC/data value or data address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_FUNCTION</name>
|
|
<description>DWT Function Register x</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Match type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTION</name>
|
|
<description>Action on match</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Data value size</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>Comparator matched</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Identify capability</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<register>
|
|
<name>DWT_LAR</name>
|
|
<description>DWT Software Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Lock access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>UNLOCK</name>
|
|
<description>Unlock key value</description>
|
|
<value>0xC5ACCE55</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_LSR</name>
|
|
<description>DWT Software Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>Software Lock implemented</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLK</name>
|
|
<description>Software Lock status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nTT</name>
|
|
<description>Not thirty-two bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_DEVARCH</name>
|
|
<description>DWT Device Architecture Register</description>
|
|
<addressOffset>0xFBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x47701A02</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARCHPART</name>
|
|
<description>Architecture Part</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHVER</name>
|
|
<description>Architecture Version</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT</name>
|
|
<description>DEVARCH Present</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHITECT</name>
|
|
<description>Architect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_DEVTYPE</name>
|
|
<description>DWT Device Type Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUB</name>
|
|
<description>Sub-type</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR4</name>
|
|
<description>DWT Peripheral Identification Register 4</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_2</name>
|
|
<description>JEP106 continuation code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>4KB count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR5</name>
|
|
<description>DWT Peripheral Identification Register 5</description>
|
|
<addressOffset>0xFD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR6</name>
|
|
<description>DWT Peripheral Identification Register 6</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR7</name>
|
|
<description>DWT Peripheral Identification Register 7</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR0</name>
|
|
<description>DWT Peripheral Identification Register 0</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_0</name>
|
|
<description>Part number bits[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR1</name>
|
|
<description>DWT Peripheral Identification Register 1</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_1</name>
|
|
<description>Part number bits[11:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DES_0</name>
|
|
<description>JEP106 identification code bits [3:0]</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR2</name>
|
|
<description>DWT Peripheral Identification Register 2</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_1</name>
|
|
<description>JEP106 identification code bits[6:4]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEDEC</name>
|
|
<description>JEDEC assignee value is used</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Component revision</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_PIDR3</name>
|
|
<description>DWT Peripheral Identification Register 3</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>Customer Modified</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>RevAnd</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CIDR0</name>
|
|
<description>DWT Component Identification Register 0</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_0</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CIDR1</name>
|
|
<description>DWT Component Identification Register 1</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_1</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLASS</name>
|
|
<description>CoreSight component class</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CIDR2</name>
|
|
<description>DWT Component Identification Register 2</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_2</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DWT_CIDR3</name>
|
|
<description>DWT Component Identification Register 3</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_3</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FPB</name>
|
|
<description>Flash Patch and Breakpoint</description>
|
|
<groupName>FPB</groupName>
|
|
<prependToName>FPB_</prependToName>
|
|
<baseAddress>0xE0002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FP_CTRL</name>
|
|
<description>Flash Patch Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Flash Patch global enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>FP_CTRL write-enable key</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NUM_CODE</name>
|
|
<description>Number of implemented code comparators bits [3:0]</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NUM_LIT</name>
|
|
<description>Number of literal comparators</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NUM_CODE_1</name>
|
|
<description>Number of implemented code comparators bits [6:4]</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REV</name>
|
|
<description>Revision</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_REMAP</name>
|
|
<description>Flash Patch Remap Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>REMAP</name>
|
|
<description>Remap address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMPSPT</name>
|
|
<description>Remap supported</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>FP_COMP[%s]</name>
|
|
<description>Flash Patch Comparator Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>Breakpoint enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPADDR</name>
|
|
<description>Flash Patch address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Flash Patch enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>FP_COMP_BREAKPOINT_MODE[%s]</name>
|
|
<description>Flash Patch Comparator Register n</description>
|
|
<alternateRegister>FP_COMP[%s]</alternateRegister>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>Breakpoint enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPADDR</name>
|
|
<description>Breakpoint address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_LAR</name>
|
|
<description>FPB Software Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Lock access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>UNLOCK</name>
|
|
<description>Unlock key value</description>
|
|
<value>0xC5ACCE55</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_LSR</name>
|
|
<description>FPB Software Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>Software Lock implemented</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLK</name>
|
|
<description>Software Lock status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nTT</name>
|
|
<description>Not thirty-two bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_DEVARCH</name>
|
|
<description>FPB Device Architecture Register</description>
|
|
<addressOffset>0xFBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x47701A03</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARCHPART</name>
|
|
<description>Architecture Part</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHVER</name>
|
|
<description>Architecture Version</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT</name>
|
|
<description>DEVARCH Present</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARCHITECT</name>
|
|
<description>Architect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_DEVTYPE</name>
|
|
<description>FPB Device Type Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUB</name>
|
|
<description>Sub-type</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR4</name>
|
|
<description>FP Peripheral Identification Register 4</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_2</name>
|
|
<description>JEP106 continuation code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>4KB count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR5</name>
|
|
<description>FP Peripheral Identification Register 5</description>
|
|
<addressOffset>0xFD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR6</name>
|
|
<description>FP Peripheral Identification Register 6</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR7</name>
|
|
<description>FP Peripheral Identification Register 7</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR0</name>
|
|
<description>FP Peripheral Identification Register 0</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_0</name>
|
|
<description>Part number bits[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR1</name>
|
|
<description>FP Peripheral Identification Register 1</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PART_1</name>
|
|
<description>Part number bits[11:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DES_0</name>
|
|
<description>JEP106 identification code bits [3:0]</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR2</name>
|
|
<description>FP Peripheral Identification Register 2</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>DES_1</name>
|
|
<description>JEP106 identification code bits[6:4]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEDEC</name>
|
|
<description>JEDEC assignee value is used</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Component revision</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_PIDR3</name>
|
|
<description>FP Peripheral Identification Register 3</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>Customer Modified</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>RevAnd</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_CIDR0</name>
|
|
<description>FP Component Identification Register 0</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_0</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_CIDR1</name>
|
|
<description>FP Component Identification Register 1</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_1</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLASS</name>
|
|
<description>CoreSight component class</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_CIDR2</name>
|
|
<description>FP Component Identification Register 2</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_2</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FP_CIDR3</name>
|
|
<description>FP Component Identification Register 3</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRMBL_3</name>
|
|
<description>CoreSight component identification preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ICB</name>
|
|
<description>Implementation Control Block</description>
|
|
<groupName>ICB</groupName>
|
|
<prependToName>ICB_</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ICTR</name>
|
|
<description>Interrupt Controller Type Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>INTLINESNUM</name>
|
|
<description>Interrupt line set number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<description>Auxiliary Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ICB">
|
|
<name>ICB_NS</name>
|
|
<baseAddress>0xE002E000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MPU</name>
|
|
<description>Memory Protection Unit</description>
|
|
<groupName>MPU</groupName>
|
|
<prependToName>MPU_</prependToName>
|
|
<baseAddress>0xE000ED90</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MPU_TYPE</name>
|
|
<description>MPU Type Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instructions and data address regions</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DREGION</name>
|
|
<description>Number of MPU data regions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_CTRL</name>
|
|
<description>MPU Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>MPU enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFNMIENA</name>
|
|
<description>HardFault, NMI enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIVDEFENA</name>
|
|
<description>Privileged default enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RNR</name>
|
|
<description>MPU Region Number Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Selected region number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RBAR</name>
|
|
<description>MPU Region Base Address Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Execute Never</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access permissions</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>APSelect</name>
|
|
<enumeratedValue>
|
|
<name>RWPRIV</name>
|
|
<description>Read/write by privileged code only</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RWANY</name>
|
|
<description>Read/write by any privilege level</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RPRIV</name>
|
|
<description>Read-only by privileged code only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANY</name>
|
|
<description>Read-only by any privilege level</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SH</name>
|
|
<description>Shareability</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SHSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Non-shareable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTER</name>
|
|
<description>Outer shareable</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INNER</name>
|
|
<description>Inner shareable</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BASE</name>
|
|
<description>Base address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_RLAR</name>
|
|
<description>MPU Region Limit Address Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Region enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AttrInd</name>
|
|
<description>Attribute Index</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LIMIT</name>
|
|
<description>Limit address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_MAIR0</name>
|
|
<description>MPU Memory Attribute Indirection Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>Attr0</name>
|
|
<description>Attribute of MPU region 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Attr1</name>
|
|
<description>Attribute of MPU region 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Attr2</name>
|
|
<description>Attribute of MPU region 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Attr3</name>
|
|
<description>Attribute of MPU region 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_MAIR1</name>
|
|
<description>MPU Memory Attribute Indirection Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="MPU">
|
|
<name>MPU_NS</name>
|
|
<baseAddress>0xE002ED90</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<prependToName>NVIC_</prependToName>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x348</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_ISER[%s]</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Set enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_ICER[%s]</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Clear enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_ISPR[%s]</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Set pending</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_ICPR[%s]</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Clear pending</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_IABR[%s]</name>
|
|
<description>Interrupt Active Bit Register n</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Active state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_ITNS[%s]</name>
|
|
<description>Interrupt Target Non-secure Register n</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ITNS</name>
|
|
<description>Interrupt Targets Non-secure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>NVIC_IPR[%s]</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_N0</name>
|
|
<description>Priority of interrupt number 4n+0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_N1</name>
|
|
<description>Priority of interrupt number 4n+1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_N2</name>
|
|
<description>Priority of interrupt number 4n+2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_N3</name>
|
|
<description>Priority of interrupt number 4n+3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="NVIC">
|
|
<name>NVIC_NS</name>
|
|
<baseAddress>0xE002E100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCB</name>
|
|
<description>System Control Block</description>
|
|
<groupName>SCB</groupName>
|
|
<prependToName>SCB_</prependToName>
|
|
<baseAddress>0xE000ED00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPUID base register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>Revision</name>
|
|
<description>Revision number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PartNo</name>
|
|
<description>Part number, 0xD20=Cortex-M23</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Architecture</name>
|
|
<description>Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Variant</name>
|
|
<description>Variant number</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Implementer</name>
|
|
<description>Implementer code, ARM=0x41</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<description>Interrupt Control and State Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Vector active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>Return to base</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Vector pending</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>Interrupt pending</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISRPREEMPT</name>
|
|
<description>Interrupt preempt</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>Pend SysTick clear</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSTCLRSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Removes the pending state from the SysTick exception</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>Pend SysTick set</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSTSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: SysTick exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>Pend PendSV clear</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSVCLRSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Removes the pending state from the PendSV exception</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>Pend PendSV set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSVSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: PendSV exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDNMICLR</name>
|
|
<description>Pend NMI clear</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDNMISET</name>
|
|
<description>Pend NMI set</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDNMISETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: NMI exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes NMI exception state to pending; read: NMI exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<description>Application Interrupt and Reset Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>Debug: Clear Active State</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>VECTCLRACTIVESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Do not clear active state</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Clear active state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>System Reset Request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SYSRESETREQSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Do not request a system reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Request a system reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQS</name>
|
|
<description>System Reset Request Secure only</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SYSRESETREQSSelect</name>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>SYSRESETREQ functionality is available to both Security states</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECURE</name>
|
|
<description>SYSRESETREQ functionality is only available to Secure state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMINS</name>
|
|
<description>BusFault, HardFault and NMI Non-secure enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BFHFNMINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>SECURE</name>
|
|
<description>BusFault, HardFault, and NMI are Secure</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NON_SECURE</name>
|
|
<description>BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRIS</name>
|
|
<description>Prioritize Secure Exceptions</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRISSelect</name>
|
|
<enumeratedValue>
|
|
<name>SAME</name>
|
|
<description>Priority ranges of Secure and Non-secure exceptions are identical</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NS_DEPRIO</name>
|
|
<description>Non-secure exceptions are de-prioritized</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANNESS</name>
|
|
<description>Data Endianness, 0=little, 1=big</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ENDIANNESSSelect</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE</name>
|
|
<description>Little-endian</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG</name>
|
|
<description>Big-endian</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register Key (0x05FA)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>Sleep on exit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPONEXITSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>O not sleep when returning to Thread mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Enter sleep, or deep sleep, on return from an ISR</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>Sleep deep</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPDEEPSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Sleep</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Deep sleep</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEPS</name>
|
|
<description>Sleep deep secure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>Send Event on Pending bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SEVONPENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Configuration and Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>User set main pending</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Unaligned trap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>UNALIGN_TRPSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Do not trap unaligned halfword and word accesses</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Trap unaligned halfword and word accesses</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>Divide by zero trap</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>BusFault in HardFault or NMI ignore</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STKOFHFNMIGN</name>
|
|
<description>Stack overflow in HardFault and NMI ignore</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Data cache enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>Instruction cache enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BP</name>
|
|
<description>Branch prediction enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<description>System Handler Priority Register 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11, SVCall</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<description>System Handler Priority Register 3</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_12</name>
|
|
<description>Priority of system handler 12, DebugMonitor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14, PendSV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15, SysTick</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>HARDFAULTACT</name>
|
|
<description>HardFault exception active state</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMIACT</name>
|
|
<description>NMI exception active state</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>SVCall exception active state</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>PendSV exception active state</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>SysTick exception active state</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>SVCall exception pended state</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HARDFAULTPENDED</name>
|
|
<description>HardFault exception pended state</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<description>Halt or step event</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<description>Breakpoint event</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<description>Watchpoint event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<description>Vector Catch event</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<description>External event</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<description>Auxiliary Fault Status Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>CLIDR</name>
|
|
<description>Cache Level ID Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>Ctype1</name>
|
|
<description>Cache type at level 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype1Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype2</name>
|
|
<description>Cache type at level 2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype2Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype3</name>
|
|
<description>Cache type at level 3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype3Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype4</name>
|
|
<description>Cache type at level 4</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype4Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype5</name>
|
|
<description>Cache type at level 5</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype5Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype6</name>
|
|
<description>Cache type at level 6</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype6Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Ctype7</name>
|
|
<description>Cache type at level 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>Ctype7Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC</name>
|
|
<description>Instruction cache only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC</name>
|
|
<description>Data cache only</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIFIED</name>
|
|
<description>Unified cache</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LoUIS</name>
|
|
<description>Level of Unification Inner Shareable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LoC</name>
|
|
<description>Level of Coherence</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LoUU</name>
|
|
<description>Level of Unification Uniprocessor</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICB</name>
|
|
<description>Inner cache boundary</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ICBSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not disclosed in this mechanism</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L1</name>
|
|
<description>L1 cache is the highest inner level</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L2</name>
|
|
<description>L2 cache is the highest inner level</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L3</name>
|
|
<description>L3 cache is the highest inner level</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTR</name>
|
|
<description>Cache Type Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>IminLine</name>
|
|
<description>Instruction cache minimum line length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DminLine</name>
|
|
<description>Data cache minimum line length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERG</name>
|
|
<description>Exclusives Reservation Granule</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWG</name>
|
|
<description>Cache Write-back Granule</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Format</name>
|
|
<description>Cache Type Register format</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FormatSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No cache type information provided</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Cache type information is provided</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCSIDR</name>
|
|
<description>Current Cache Size ID register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>LineSize</name>
|
|
<description>log2(number of words per line) - 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Associativity</name>
|
|
<description>Associativity - 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NumSets</name>
|
|
<description>Number of sets - 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WA</name>
|
|
<description>Write-Allocate</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Read-Allocate</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WB</name>
|
|
<description>Write-Back</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WT</name>
|
|
<description>Write-Through</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSSELR</name>
|
|
<description>Cache Size Selection Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>InD</name>
|
|
<description>Instruction not Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Level</name>
|
|
<description>Cache level - 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCB">
|
|
<name>SCB_NS</name>
|
|
<baseAddress>0xE002ED00</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SysTick</name>
|
|
<description>SysTick Timer</description>
|
|
<groupName>SysTick</groupName>
|
|
<prependToName>SysTick_</prependToName>
|
|
<baseAddress>0xE000E010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYST_CSR</name>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SysTick enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<description>Tick interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>Clock source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>Count flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYST_RVR</name>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Counter reload value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYST_CVR</name>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current counter value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYST_CALIB</name>
|
|
<description>SysTick Calibration Value Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Ten milliseconds</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>Skew</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>No reference</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SysTick">
|
|
<name>SysTick_NS</name>
|
|
<baseAddress>0xE002E010</baseAddress>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|