41230 lines
1.7 MiB
41230 lines
1.7 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2017 Microchip Technology Inc.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
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schemaVersion="1.1"
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xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>Microchip Technology</vendor>
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<vendorID>MCHP</vendorID>
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<name>ATSAMD51N19A</name>
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<series>SAMD51</series>
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<version>0</version>
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<description>Microchip ATSAMD51N19A Microcontroller</description>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>selectable</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<nvicPrioBits>3</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>AC</name>
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<version>U25011.0.0</version>
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<description>Analog Comparators</description>
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<groupName>AC</groupName>
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<prependToName>AC_</prependToName>
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<baseAddress>0x42002000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x26</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>AC</name>
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<value>122</value>
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</interrupt>
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<registers>
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<register>
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<name>CTRLA</name>
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<description>Control A</description>
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<addressOffset>0x0</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>SWRST</name>
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<description>Software Reset</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ENABLE</name>
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<description>Enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CTRLB</name>
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<description>Control B</description>
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<addressOffset>0x1</addressOffset>
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<size>8</size>
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<access>write-only</access>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>START0</name>
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<description>Comparator 0 Start Comparison</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>START1</name>
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<description>Comparator 1 Start Comparison</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>EVCTRL</name>
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<description>Event Control</description>
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<addressOffset>0x2</addressOffset>
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<size>16</size>
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<resetValue>0x0000</resetValue>
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<fields>
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<field>
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<name>COMPEO0</name>
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<description>Comparator 0 Event Output Enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMPEO1</name>
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<description>Comparator 1 Event Output Enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WINEO0</name>
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<description>Window 0 Event Output Enable</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMPEI0</name>
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<description>Comparator 0 Event Input Enable</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMPEI1</name>
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<description>Comparator 1 Event Input Enable</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>INVEI0</name>
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<description>Comparator 0 Input Event Invert Enable</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>INVEI1</name>
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<description>Comparator 1 Input Event Invert Enable</description>
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<bitOffset>13</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>INTENCLR</name>
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<description>Interrupt Enable Clear</description>
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<addressOffset>0x4</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>COMP0</name>
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<description>Comparator 0 Interrupt Enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMP1</name>
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<description>Comparator 1 Interrupt Enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WIN0</name>
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<description>Window 0 Interrupt Enable</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>INTENSET</name>
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<description>Interrupt Enable Set</description>
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<addressOffset>0x5</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>COMP0</name>
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<description>Comparator 0 Interrupt Enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMP1</name>
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<description>Comparator 1 Interrupt Enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WIN0</name>
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<description>Window 0 Interrupt Enable</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>INTFLAG</name>
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<description>Interrupt Flag Status and Clear</description>
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<addressOffset>0x6</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>COMP0</name>
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<description>Comparator 0</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>COMP1</name>
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<description>Comparator 1</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WIN0</name>
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<description>Window 0</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>STATUSA</name>
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<description>Status A</description>
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<addressOffset>0x7</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>STATE0</name>
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<description>Comparator 0 Current State</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>STATE1</name>
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<description>Comparator 1 Current State</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WSTATE0</name>
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<description>Window 0 Current State</description>
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<bitOffset>4</bitOffset>
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<bitWidth>2</bitWidth>
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<enumeratedValues>
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<name>WSTATE0Select</name>
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<enumeratedValue>
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<name>ABOVE</name>
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<description>Signal is above window</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>INSIDE</name>
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<description>Signal is inside window</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>BELOW</name>
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<description>Signal is below window</description>
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<value>2</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>STATUSB</name>
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<description>Status B</description>
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<addressOffset>0x8</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>READY0</name>
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<description>Comparator 0 Ready</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>READY1</name>
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<description>Comparator 1 Ready</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>DBGCTRL</name>
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<description>Debug Control</description>
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<addressOffset>0x9</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>DBGRUN</name>
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<description>Debug Run</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>WINCTRL</name>
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<description>Window Control</description>
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<addressOffset>0xA</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>WEN0</name>
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<description>Window 0 Mode Enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WINTSEL0</name>
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<description>Window 0 Interrupt Selection</description>
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<bitOffset>1</bitOffset>
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<bitWidth>2</bitWidth>
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<enumeratedValues>
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<name>WINTSEL0Select</name>
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<enumeratedValue>
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<name>ABOVE</name>
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<description>Interrupt on signal above window</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>INSIDE</name>
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<description>Interrupt on signal inside window</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>BELOW</name>
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<description>Interrupt on signal below window</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>OUTSIDE</name>
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<description>Interrupt on signal outside window</description>
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<value>3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<dim>2</dim>
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<dimIncrement>1</dimIncrement>
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<name>SCALER[%s]</name>
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<description>Scaler n</description>
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<addressOffset>0xC</addressOffset>
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<size>8</size>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>VALUE</name>
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<description>Scaler Value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>6</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<dim>2</dim>
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<dimIncrement>4</dimIncrement>
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<name>COMPCTRL[%s]</name>
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<description>Comparator Control n</description>
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<addressOffset>0x10</addressOffset>
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<size>32</size>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ENABLE</name>
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<description>Enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SINGLE</name>
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<description>Single-Shot Mode</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>INTSEL</name>
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<description>Interrupt Selection</description>
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<bitOffset>3</bitOffset>
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<bitWidth>2</bitWidth>
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<enumeratedValues>
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<name>INTSELSelect</name>
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<enumeratedValue>
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<name>TOGGLE</name>
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<description>Interrupt on comparator output toggle</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING</name>
|
|
<description>Interrupt on comparator output rising</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING</name>
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<description>Interrupt on comparator output falling</description>
|
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EOC</name>
|
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<description>Interrupt on end of comparison (single-shot mode only)</description>
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<value>3</value>
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</enumeratedValue>
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</enumeratedValues>
|
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</field>
|
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<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
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<bitWidth>1</bitWidth>
|
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</field>
|
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<field>
|
|
<name>MUXNEG</name>
|
|
<description>Negative Input Mux Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXNEGSelect</name>
|
|
<enumeratedValue>
|
|
<name>PIN0</name>
|
|
<description>I/O pin 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN1</name>
|
|
<description>I/O pin 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN2</name>
|
|
<description>I/O pin 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN3</name>
|
|
<description>I/O pin 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GND</name>
|
|
<description>Ground</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSCALE</name>
|
|
<description>VDD scaler</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BANDGAP</name>
|
|
<description>Internal bandgap voltage</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC output</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXPOS</name>
|
|
<description>Positive Input Mux Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXPOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>PIN0</name>
|
|
<description>I/O pin 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN1</name>
|
|
<description>I/O pin 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN2</name>
|
|
<description>I/O pin 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN3</name>
|
|
<description>I/O pin 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSCALE</name>
|
|
<description>VDD Scaler</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap Inputs and Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPEEDSelect</name>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High speed</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYSTEN</name>
|
|
<description>Hysteresis Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis Level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HYSTSelect</name>
|
|
<enumeratedValue>
|
|
<name>HYST50</name>
|
|
<description>50mV</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST100</name>
|
|
<description>100mV</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST150</name>
|
|
<description>150mV</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEN</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FLENSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>No filtering</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJ3</name>
|
|
<description>3-bit majority function (2 of 3)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJ5</name>
|
|
<description>5-bit majority function (3 of 5)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Output</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>OUTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>The output of COMPn is not routed to the COMPn I/O port</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINCTRL</name>
|
|
<description>WINCTRL Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPCTRL0</name>
|
|
<description>COMPCTRL 0 Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMPCTRL1</name>
|
|
<description>COMPCTRL 1 Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>Calibration</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIAS0</name>
|
|
<description>COMP0/1 Bias Scaling</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<version>U25001.0.0</version>
|
|
<description>Analog Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC_</prependToName>
|
|
<baseAddress>0x43001C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4A</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0_OTHER</name>
|
|
<value>118</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC0_RESRDY</name>
|
|
<value>119</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALSEL</name>
|
|
<description>Dual Mode Trigger Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DUALSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Start event or software trigger will start a conversion on both ADCs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERLEAVE</name>
|
|
<description>START event or software trigger will alternatingly start a conversion on ADC0 and ADC1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLAVEEN</name>
|
|
<description>Slave Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Peripheral clock divided by 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Peripheral clock divided by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Peripheral clock divided by 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Peripheral clock divided by 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Peripheral clock divided by 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Peripheral clock divided by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Peripheral clock divided by 128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Peripheral clock divided by 256</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R2R</name>
|
|
<description>Rail to Rail Operation Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLUSHEI</name>
|
|
<description>Flush Event Input Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTEI</name>
|
|
<description>Start Conversion Event Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLUSHINV</name>
|
|
<description>Flush Event Invert Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTINV</name>
|
|
<description>Start Conversion Event Invert Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDYEO</name>
|
|
<description>Result Ready Event Out</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMONEO</name>
|
|
<description>Window Monitor Event Out</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUTCTRL</name>
|
|
<description>Input Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUXPOS</name>
|
|
<description>Positive Mux Input Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXPOSSelect</name>
|
|
<enumeratedValue>
|
|
<name>AIN0</name>
|
|
<description>ADC AIN0 Pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN1</name>
|
|
<description>ADC AIN1 Pin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN2</name>
|
|
<description>ADC AIN2 Pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN3</name>
|
|
<description>ADC AIN3 Pin</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN4</name>
|
|
<description>ADC AIN4 Pin</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN5</name>
|
|
<description>ADC AIN5 Pin</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN6</name>
|
|
<description>ADC AIN6 Pin</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN7</name>
|
|
<description>ADC AIN7 Pin</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN8</name>
|
|
<description>ADC AIN8 Pin</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN9</name>
|
|
<description>ADC AIN9 Pin</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN10</name>
|
|
<description>ADC AIN10 Pin</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN11</name>
|
|
<description>ADC AIN11 Pin</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN12</name>
|
|
<description>ADC AIN12 Pin</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN13</name>
|
|
<description>ADC AIN13 Pin</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN14</name>
|
|
<description>ADC AIN14 Pin</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN15</name>
|
|
<description>ADC AIN15 Pin</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN16</name>
|
|
<description>ADC AIN16 Pin</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN17</name>
|
|
<description>ADC AIN17 Pin</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN18</name>
|
|
<description>ADC AIN18 Pin</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN19</name>
|
|
<description>ADC AIN19 Pin</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN20</name>
|
|
<description>ADC AIN20 Pin</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN21</name>
|
|
<description>ADC AIN21 Pin</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN22</name>
|
|
<description>ADC AIN22 Pin</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN23</name>
|
|
<description>ADC AIN23 Pin</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDCOREVCC</name>
|
|
<description>1/4 Scaled Core Supply</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDVBAT</name>
|
|
<description>1/4 Scaled VBAT Supply</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCALEDIOVCC</name>
|
|
<description>1/4 Scaled I/O Supply</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BANDGAP</name>
|
|
<description>Bandgap Voltage</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTAT</name>
|
|
<description>Temperature Sensor</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTAT</name>
|
|
<description>Temperature Sensor</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC Output</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC</name>
|
|
<description>PTC output (only on ADC0)</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIFFMODE</name>
|
|
<description>Differential Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXNEG</name>
|
|
<description>Negative Mux Input Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MUXNEGSelect</name>
|
|
<enumeratedValue>
|
|
<name>AIN0</name>
|
|
<description>ADC AIN0 Pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN1</name>
|
|
<description>ADC AIN1 Pin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN2</name>
|
|
<description>ADC AIN2 Pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN3</name>
|
|
<description>ADC AIN3 Pin</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN4</name>
|
|
<description>ADC AIN4 Pin</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN5</name>
|
|
<description>ADC AIN5 Pin</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN6</name>
|
|
<description>ADC AIN6 Pin</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIN7</name>
|
|
<description>ADC AIN7 Pin</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GND</name>
|
|
<description>Internal Ground</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSEQSTOP</name>
|
|
<description>Stop DMA Sequencing</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEFTADJ</name>
|
|
<description>Left-Adjusted Result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREERUN</name>
|
|
<description>Free Running Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CORREN</name>
|
|
<description>Digital Correction Logic Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESSEL</name>
|
|
<description>Conversion Result Resolution</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RESSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>12BIT</name>
|
|
<description>12-bit result</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>For averaging mode output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BIT</name>
|
|
<description>10-bit result</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>8-bit result</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WINMODE</name>
|
|
<description>Window Monitor Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WINMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No window mode (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>RESULT > WINLT</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>RESULT < WINUT</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>WINLT < RESULT < WINUT</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE4</name>
|
|
<description>!(WINLT < RESULT < WINUT)</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WINSS</name>
|
|
<description>Window Single Sample</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFCTRL</name>
|
|
<description>Reference Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>INTREF</name>
|
|
<description>Internal Bandgap Reference</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTVCC0</name>
|
|
<description>1/2 VDDANA</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTVCC1</name>
|
|
<description>VDDANA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AREFA</name>
|
|
<description>External Reference</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AREFB</name>
|
|
<description>External Reference</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AREFC</name>
|
|
<description>External Reference (only on ADC1)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFCOMP</name>
|
|
<description>Reference Buffer Offset Compensation Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AVGCTRL</name>
|
|
<description>Average Control</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLENUM</name>
|
|
<description>Number of Samples to be Collected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SAMPLENUMSelect</name>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1 sample</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>2 samples</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>4 samples</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 samples</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 samples</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 samples</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 samples</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128</name>
|
|
<description>128 samples</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256</name>
|
|
<description>256 samples</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 samples</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 samples</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADJRES</name>
|
|
<description>Adjusting Result / Division Coefficient</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMPCTRL</name>
|
|
<description>Sample Time Control</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLEN</name>
|
|
<description>Sampling Time Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFCOMP</name>
|
|
<description>Comparator Offset Compensation Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINLT</name>
|
|
<description>Window Monitor Lower Threshold</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>Window Lower Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINUT</name>
|
|
<description>Window Monitor Upper Threshold</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>Window Upper Threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLUSH</name>
|
|
<description>ADC Conversion Flush</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start ADC Conversion</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x2D</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESRDY</name>
|
|
<description>Result Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMON</name>
|
|
<description>Window Monitor Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCBUSY</name>
|
|
<description>ADC Busy Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCC</name>
|
|
<description>Window Comparator Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>SWRST Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>ENABLE Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INPUTCTRL</name>
|
|
<description>Input Control Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>Control B Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCTRL</name>
|
|
<description>Reference Control Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AVGCTRL</name>
|
|
<description>Average Control Synchronization Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPCTRL</name>
|
|
<description>Sampling Time Control Synchronization Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>Window Monitor Lower Threshold Synchronization Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>Window Monitor Upper Threshold Synchronization Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction Synchronization Busy</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction Synchronization Busy</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger Synchronization Busy</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSEQDATA</name>
|
|
<description>DMA Sequencial Data</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DMA Sequential Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSEQCTRL</name>
|
|
<description>DMA Sequential Control</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INPUTCTRL</name>
|
|
<description>Input Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCTRL</name>
|
|
<description>Reference Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AVGCTRL</name>
|
|
<description>Average Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPCTRL</name>
|
|
<description>Sampling Time Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>Window Monitor Lower Threshold</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>Window Monitor Upper Threshold</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSTART</name>
|
|
<description>ADC Auto-Start Conversion</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSEQSTAT</name>
|
|
<description>DMA Sequencial Status</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INPUTCTRL</name>
|
|
<description>Input Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCTRL</name>
|
|
<description>Reference Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AVGCTRL</name>
|
|
<description>Average Control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPCTRL</name>
|
|
<description>Sampling Time Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINLT</name>
|
|
<description>Window Monitor Lower Threshold</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINUT</name>
|
|
<description>Window Monitor Upper Threshold</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GAINCORR</name>
|
|
<description>Gain Correction</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETCORR</name>
|
|
<description>Offset Correction</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>DMA Sequencing Busy</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESULT</name>
|
|
<description>Result Conversion Value</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>Result Conversion Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESS</name>
|
|
<description>Last Sample Result</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESS</name>
|
|
<description>Last ADC conversion result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>Calibration</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIASCOMP</name>
|
|
<description>Bias Comparator Scaling</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIASR2R</name>
|
|
<description>Bias R2R Ampli scaling</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIASREFBUF</name>
|
|
<description>Bias Reference Buffer Scaling</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<baseAddress>0x43002000</baseAddress>
|
|
<interrupt>
|
|
<name>ADC1_OTHER</name>
|
|
<value>120</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC1_RESRDY</name>
|
|
<value>121</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES</name>
|
|
<version>U22382.2.0</version>
|
|
<description>Advanced Encryption Standard</description>
|
|
<groupName>AES</groupName>
|
|
<prependToName>AES_</prependToName>
|
|
<baseAddress>0x42002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>AES</name>
|
|
<value>130</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AESMODE</name>
|
|
<description>AES Modes of operation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>AESMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>ECB</name>
|
|
<description>Electronic code book mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CBC</name>
|
|
<description>Cipher block chaining mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFB</name>
|
|
<description>Output feedback mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CFB</name>
|
|
<description>Cipher feedback mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER</name>
|
|
<description>Counter mode</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CCM</name>
|
|
<description>CCM mode</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCM</name>
|
|
<description>Galois counter mode</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFBS</name>
|
|
<description>Cipher Feedback Block Size</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CFBSSelect</name>
|
|
<enumeratedValue>
|
|
<name>128BIT</name>
|
|
<description>128-bit Input data block for Encryption/Decryption in Cipher Feedback mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64BIT</name>
|
|
<description>64-bit Input data block for Encryption/Decryption in Cipher Feedback mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT</name>
|
|
<description>32-bit Input data block for Encryption/Decryption in Cipher Feedback mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>16-bit Input data block for Encryption/Decryption in Cipher Feedback mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>8-bit Input data block for Encryption/Decryption in Cipher Feedback mode</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYSIZE</name>
|
|
<description>Encryption Key Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>128BIT</name>
|
|
<description>128-bit Key for Encryption / Decryption</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>192BIT</name>
|
|
<description>192-bit Key for Encryption / Decryption</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256BIT</name>
|
|
<description>256-bit Key for Encryption / Decryption</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIPHER</name>
|
|
<description>Cipher Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CIPHERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DEC</name>
|
|
<description>Decryption</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENC</name>
|
|
<description>Encryption</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTMODE</name>
|
|
<description>Start Mode Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STARTMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>MANUAL</name>
|
|
<description>Start Encryption / Decryption in Manual mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO</name>
|
|
<description>Start Encryption / Decryption in Auto mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOD</name>
|
|
<description>Last Output Data Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LODSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No effect</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LAST</name>
|
|
<description>Start encryption in Last Output Data mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYGEN</name>
|
|
<description>Last Key Generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No effect</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LAST</name>
|
|
<description>Start Computation of the last NK words of the expanded key</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XORKEY</name>
|
|
<description>XOR Key Operation</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>XORKEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No effect</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOR</name>
|
|
<description>The user keyword gets XORed with the previous keyword register content.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTYPE</name>
|
|
<description>Counter Measure Type</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Encryption/Decryption</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NEWMSG</name>
|
|
<description>New message</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOM</name>
|
|
<description>End of message</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GFMUL</name>
|
|
<description>GF Multiplication</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENCCMP</name>
|
|
<description>Encryption Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GFMCMP</name>
|
|
<description>GF Multiplication Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENCCMP</name>
|
|
<description>Encryption Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GFMCMP</name>
|
|
<description>GF Multiplication Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENCCMP</name>
|
|
<description>Encryption Complete</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GFMCMP</name>
|
|
<description>GF Multiplication Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATABUFPTR</name>
|
|
<description>Data buffer pointer</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INDATAPTR</name>
|
|
<description>Input Data Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug control</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>KEYWORD[%s]</name>
|
|
<description>Keyword n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>INDATA</name>
|
|
<description>Indata</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>INTVECTV[%s]</name>
|
|
<description>Initialisation Vector n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>HASHKEY[%s]</name>
|
|
<description>Hash key n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GHASH[%s]</name>
|
|
<description>Galois Hash n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CIPLEN</name>
|
|
<description>Cipher Length</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>RANDSEED</name>
|
|
<description>Random Seed</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCL</name>
|
|
<version>U22251.1.0</version>
|
|
<description>Configurable Custom Logic</description>
|
|
<groupName>CCL</groupName>
|
|
<prependToName>CCL_</prependToName>
|
|
<baseAddress>0x42003800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>SEQCTRL[%s]</name>
|
|
<description>SEQ Control x</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEQSEL</name>
|
|
<description>Sequential Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SEQSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Sequential logic is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DFF</name>
|
|
<description>D flip flop</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>JK</name>
|
|
<description>JK flip flop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCH</name>
|
|
<description>D latch</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RS</name>
|
|
<description>RS latch</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>LUTCTRL[%s]</name>
|
|
<description>LUT Control x</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>LUT Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTSEL</name>
|
|
<description>Filter Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FILTSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Filter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCH</name>
|
|
<description>Synchronizer enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER</name>
|
|
<description>Filter enabled</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGESEL</name>
|
|
<description>Edge Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSEL0</name>
|
|
<description>Input Selection 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL0Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL1</name>
|
|
<description>Input Selection 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL1Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL2</name>
|
|
<description>Input Selection 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INSEL2Select</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Masked input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK</name>
|
|
<description>Feedback input source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINK</name>
|
|
<description>Linked LUT input source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>Event input source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O pin input source</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AC</name>
|
|
<description>AC input source</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC</name>
|
|
<description>TC input source</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTTC</name>
|
|
<description>Alternate TC input source</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCC</name>
|
|
<description>TCC input source</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCOM</name>
|
|
<description>SERCOM input source</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVEI</name>
|
|
<description>Inverted Event Input Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUTEI</name>
|
|
<description>LUT Event Input Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUTEO</name>
|
|
<description>LUT Event Output Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRUTH</name>
|
|
<description>Truth Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMCC</name>
|
|
<version>U20156.0.0</version>
|
|
<description>Cortex M Cache Controller</description>
|
|
<groupName>CMCC</groupName>
|
|
<prependToName>CMCC_</prependToName>
|
|
<baseAddress>0x41006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TYPE</name>
|
|
<description>Cache Type Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000012D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCLK</name>
|
|
<description>dynamic Clock Gating supported</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRP</name>
|
|
<description>Round Robin Policy supported</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAYNUM</name>
|
|
<description>Number of Way</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAYNUMSelect</name>
|
|
<enumeratedValue>
|
|
<name>DMAPPED</name>
|
|
<description>Direct Mapped Cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARCH2WAY</name>
|
|
<description>2-WAY set associative</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARCH4WAY</name>
|
|
<description>4-WAY set associative</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCKDOWN</name>
|
|
<description>Lock Down supported</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSIZE</name>
|
|
<description>Cache Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>CSIZE_1KB</name>
|
|
<description>Cache Size is 1 KB</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_2KB</name>
|
|
<description>Cache Size is 2 KB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_4KB</name>
|
|
<description>Cache Size is 4 KB</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_8KB</name>
|
|
<description>Cache Size is 8 KB</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_16KB</name>
|
|
<description>Cache Size is 16 KB</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_32KB</name>
|
|
<description>Cache Size is 32 KB</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSIZE_64KB</name>
|
|
<description>Cache Size is 64 KB</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLSIZE</name>
|
|
<description>Cache Line Size</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_4B</name>
|
|
<description>Cache Line Size is 4 bytes</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_8B</name>
|
|
<description>Cache Line Size is 8 bytes</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_16B</name>
|
|
<description>Cache Line Size is 16 bytes</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_32B</name>
|
|
<description>Cache Line Size is 32 bytes</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_64B</name>
|
|
<description>Cache Line Size is 64 bytes</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLSIZE_128B</name>
|
|
<description>Cache Line Size is 128 bytes</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Cache Configuration Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000020</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ICDIS</name>
|
|
<description>Instruction Cache Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDIS</name>
|
|
<description>Data Cache Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSIZESW</name>
|
|
<description>Cache size configured by software</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CSIZESWSelect</name>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_1KB</name>
|
|
<description>The Cache Size is configured to 1KB</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_2KB</name>
|
|
<description>The Cache Size is configured to 2KB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_4KB</name>
|
|
<description>The Cache Size is configured to 4KB</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_8KB</name>
|
|
<description>The Cache Size is configured to 8KB</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_16KB</name>
|
|
<description>The Cache Size is configured to 16KB</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_32KB</name>
|
|
<description>The Cache Size is configured to 32KB</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONF_CSIZE_64KB</name>
|
|
<description>The Cache Size is configured to 64KB</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Cache Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Cache Controller Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Cache Status Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSTS</name>
|
|
<description>Cache Controller Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKWAY</name>
|
|
<description>Cache Lock per Way Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKWAY</name>
|
|
<description>Lockdown way Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINT0</name>
|
|
<description>Cache Maintenance Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVALL</name>
|
|
<description>Cache Controller invalidate All</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINT1</name>
|
|
<description>Cache Maintenance Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INDEX</name>
|
|
<description>Invalidate Index</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAY</name>
|
|
<description>Invalidate Way</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAYSelect</name>
|
|
<enumeratedValue>
|
|
<name>WAY0</name>
|
|
<description>Way 0 is selection for index invalidation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAY1</name>
|
|
<description>Way 1 is selection for index invalidation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAY2</name>
|
|
<description>Way 2 is selection for index invalidation</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAY3</name>
|
|
<description>Way 3 is selection for index invalidation</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFG</name>
|
|
<description>Cache Monitor Configuration Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Cache Controller Monitor Counter Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>CYCLE_COUNT</name>
|
|
<description>Cycle counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IHIT_COUNT</name>
|
|
<description>Instruction hit counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DHIT_COUNT</name>
|
|
<description>Data hit counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEN</name>
|
|
<description>Cache Monitor Enable Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MENABLE</name>
|
|
<description>Cache Controller Monitor Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCTRL</name>
|
|
<description>Cache Monitor Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Cache Controller Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Cache Monitor Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVENT_CNT</name>
|
|
<description>Monitor Event Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<version>U25021.0.0</version>
|
|
<description>Digital-to-Analog Converter</description>
|
|
<groupName>DAC</groupName>
|
|
<prependToName>DAC_</prependToName>
|
|
<baseAddress>0x43002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC_OTHER</name>
|
|
<value>123</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC_EMPTY_0</name>
|
|
<value>124</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC_EMPTY_1</name>
|
|
<value>125</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC_RESRDY_0</name>
|
|
<value>126</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC_RESRDY_1</name>
|
|
<value>127</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable DAC Controller</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x02</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Differential mode enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Selection for DAC0/1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>VREFPU</name>
|
|
<description>External reference unbuffered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDANA</name>
|
|
<description>Analog supply</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREFPB</name>
|
|
<description>External reference buffered</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTREF</name>
|
|
<description>Internal bandgap reference</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STARTEI0</name>
|
|
<description>Start Conversion Event Input DAC 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTEI1</name>
|
|
<description>Start Conversion Event Input DAC 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTYEO0</name>
|
|
<description>Data Buffer Empty Event Output DAC 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTYEO1</name>
|
|
<description>Data Buffer Empty Event Output DAC 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEI0</name>
|
|
<description>Enable Invertion of DAC 0 input event</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEI1</name>
|
|
<description>Enable Invertion of DAC 1 input event</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDYEO0</name>
|
|
<description>Result Ready Event Output 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDYEO1</name>
|
|
<description>Result Ready Event Output 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN0</name>
|
|
<description>Underrun 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNDERRUN1</name>
|
|
<description>Underrun 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY0</name>
|
|
<description>Data Buffer 0 Empty Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY1</name>
|
|
<description>Data Buffer 1 Empty Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY0</name>
|
|
<description>Result 0 Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY1</name>
|
|
<description>Result 1 Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN0</name>
|
|
<description>Overrun 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN1</name>
|
|
<description>Overrun 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN0</name>
|
|
<description>Underrun 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNDERRUN1</name>
|
|
<description>Underrun 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY0</name>
|
|
<description>Data Buffer 0 Empty Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY1</name>
|
|
<description>Data Buffer 1 Empty Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY0</name>
|
|
<description>Result 0 Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY1</name>
|
|
<description>Result 1 Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN0</name>
|
|
<description>Overrun 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN1</name>
|
|
<description>Overrun 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UNDERRUN0</name>
|
|
<description>Result 0 Underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNDERRUN1</name>
|
|
<description>Result 1 Underrun</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY0</name>
|
|
<description>Data Buffer 0 Empty</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY1</name>
|
|
<description>Data Buffer 1 Empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY0</name>
|
|
<description>Result 0 Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESRDY1</name>
|
|
<description>Result 1 Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN0</name>
|
|
<description>Result 0 Overrun</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN1</name>
|
|
<description>Result 1 Overrun</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READY0</name>
|
|
<description>DAC 0 Startup Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY1</name>
|
|
<description>DAC 1 Startup Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>DAC 0 End of Conversion</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>DAC 1 End of Conversion</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DAC Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Data DAC 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data DAC 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATABUF0</name>
|
|
<description>Data Buffer DAC 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATABUF1</name>
|
|
<description>Data Buffer DAC 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>DACCTRL[%s]</name>
|
|
<description>DAC n Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEFTADJ</name>
|
|
<description>Left Adjusted Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable DAC0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCTRL</name>
|
|
<description>Current Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CCTRLSelect</name>
|
|
<enumeratedValue>
|
|
<name>CC100K</name>
|
|
<description>100kSPS</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1M</name>
|
|
<description>500kSPS</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC12M</name>
|
|
<description>1MSPS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEXT</name>
|
|
<description>Standalone Filter</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFRESH</name>
|
|
<description>Refresh period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFRESHSelect</name>
|
|
<enumeratedValue>
|
|
<name>REFRESH_0</name>
|
|
<description>Do not Refresh</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_1</name>
|
|
<description>Refresh every 30 us</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_2</name>
|
|
<description>Refresh every 60 us</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_3</name>
|
|
<description>Refresh every 90 us</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_4</name>
|
|
<description>Refresh every 120 us</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_5</name>
|
|
<description>Refresh every 150 us</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_6</name>
|
|
<description>Refresh every 180 us</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_7</name>
|
|
<description>Refresh every 210 us</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_8</name>
|
|
<description>Refresh every 240 us</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_9</name>
|
|
<description>Refresh every 270 us</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_10</name>
|
|
<description>Refresh every 300 us</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_11</name>
|
|
<description>Refresh every 330 us</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_12</name>
|
|
<description>Refresh every 360 us</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_13</name>
|
|
<description>Refresh every 390 us</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_14</name>
|
|
<description>Refresh every 420 us</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFRESH_15</name>
|
|
<description>Refresh every 450 us</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Sampling Rate</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>OSRSelect</name>
|
|
<enumeratedValue>
|
|
<name>OSR_1</name>
|
|
<description>No Over Sampling</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_2</name>
|
|
<description>2x Over Sampling Ratio</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_4</name>
|
|
<description>4x Over Sampling Ratio</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_8</name>
|
|
<description>8x Over Sampling Ratio</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_16</name>
|
|
<description>16x Over Sampling Ratio</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_32</name>
|
|
<description>32x Over Sampling Ratio</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>DATA[%s]</name>
|
|
<description>DAC n Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DAC0 Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>DATABUF[%s]</name>
|
|
<description>DAC n Data Buffer</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATABUF</name>
|
|
<description>DAC0 Data Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>RESULT[%s]</name>
|
|
<description>Filter Result</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>Filter Result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAC</name>
|
|
<version>U25031.0.1</version>
|
|
<description>Direct Memory Access Controller</description>
|
|
<groupName>DMAC</groupName>
|
|
<prependToName>DMAC_</prependToName>
|
|
<baseAddress>0x4100A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x360</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMAC_0</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_1</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_2</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_3</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMAC_OTHER</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAENABLE</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN0</name>
|
|
<description>Priority Level 0 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN1</name>
|
|
<description>Priority Level 1 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN2</name>
|
|
<description>Priority Level 2 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEN3</name>
|
|
<description>Priority Level 3 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCCTRL</name>
|
|
<description>CRC Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCBEATSIZE</name>
|
|
<description>CRC Beat Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCBEATSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>BYTE</name>
|
|
<description>8-bit bus transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HWORD</name>
|
|
<description>16-bit bus transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD</name>
|
|
<description>32-bit bus transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>CRC Polynomial Type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCPOLYSelect</name>
|
|
<enumeratedValue>
|
|
<name>CRC16</name>
|
|
<description>CRC-16 (CRC-CCITT)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC32</name>
|
|
<description>CRC32 (IEEE 802.3)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCSRC</name>
|
|
<description>CRC Input Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCSRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CRC Disabled</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>I/O interface</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCMODE</name>
|
|
<description>CRC Operating Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CRCMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default operating mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRCMON</name>
|
|
<description>Memory CRC monitor operating mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRCGEN</name>
|
|
<description>Memory CRC generation operating mode</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDATAIN</name>
|
|
<description>CRC Data Input</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDATAIN</name>
|
|
<description>CRC Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCCHKSUM</name>
|
|
<description>CRC Checksum</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCCHKSUM</name>
|
|
<description>CRC Checksum</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCSTATUS</name>
|
|
<description>CRC Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCBUSY</name>
|
|
<description>CRC Module Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCZERO</name>
|
|
<description>CRC Zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRIGCTRL</name>
|
|
<description>Software Trigger Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRIG0</name>
|
|
<description>Channel 0 Software Trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG1</name>
|
|
<description>Channel 1 Software Trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG2</name>
|
|
<description>Channel 2 Software Trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG3</name>
|
|
<description>Channel 3 Software Trigger</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG4</name>
|
|
<description>Channel 4 Software Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG5</name>
|
|
<description>Channel 5 Software Trigger</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG6</name>
|
|
<description>Channel 6 Software Trigger</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG7</name>
|
|
<description>Channel 7 Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG8</name>
|
|
<description>Channel 8 Software Trigger</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG9</name>
|
|
<description>Channel 9 Software Trigger</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG10</name>
|
|
<description>Channel 10 Software Trigger</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG11</name>
|
|
<description>Channel 11 Software Trigger</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG12</name>
|
|
<description>Channel 12 Software Trigger</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG13</name>
|
|
<description>Channel 13 Software Trigger</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG14</name>
|
|
<description>Channel 14 Software Trigger</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG15</name>
|
|
<description>Channel 15 Software Trigger</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG16</name>
|
|
<description>Channel 16 Software Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG17</name>
|
|
<description>Channel 17 Software Trigger</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG18</name>
|
|
<description>Channel 18 Software Trigger</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG19</name>
|
|
<description>Channel 19 Software Trigger</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG20</name>
|
|
<description>Channel 20 Software Trigger</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG21</name>
|
|
<description>Channel 21 Software Trigger</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG22</name>
|
|
<description>Channel 22 Software Trigger</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG23</name>
|
|
<description>Channel 23 Software Trigger</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG24</name>
|
|
<description>Channel 24 Software Trigger</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG25</name>
|
|
<description>Channel 25 Software Trigger</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG26</name>
|
|
<description>Channel 26 Software Trigger</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG27</name>
|
|
<description>Channel 27 Software Trigger</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG28</name>
|
|
<description>Channel 28 Software Trigger</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG29</name>
|
|
<description>Channel 29 Software Trigger</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG30</name>
|
|
<description>Channel 30 Software Trigger</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG31</name>
|
|
<description>Channel 31 Software Trigger</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRICTRL0</name>
|
|
<description>Priority Control 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x40404040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LVLPRI0</name>
|
|
<description>Level 0 Channel Priority Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QOS0</name>
|
|
<description>Level 0 Quality of Service</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>QOS0Select</name>
|
|
<enumeratedValue>
|
|
<name>REGULAR</name>
|
|
<description>Regular delivery</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHORTAGE</name>
|
|
<description>Bandwidth shortage</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENSITIVE</name>
|
|
<description>Latency sensitive</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRITICAL</name>
|
|
<description>Latency critical</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN0</name>
|
|
<description>Level 0 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI1</name>
|
|
<description>Level 1 Channel Priority Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QOS1</name>
|
|
<description>Level 1 Quality of Service</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>QOS1Select</name>
|
|
<enumeratedValue>
|
|
<name>REGULAR</name>
|
|
<description>Regular delivery</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHORTAGE</name>
|
|
<description>Bandwidth shortage</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENSITIVE</name>
|
|
<description>Latency sensitive</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRITICAL</name>
|
|
<description>Latency critical</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN1</name>
|
|
<description>Level 1 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI2</name>
|
|
<description>Level 2 Channel Priority Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QOS2</name>
|
|
<description>Level 2 Quality of Service</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>QOS2Select</name>
|
|
<enumeratedValue>
|
|
<name>REGULAR</name>
|
|
<description>Regular delivery</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHORTAGE</name>
|
|
<description>Bandwidth shortage</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENSITIVE</name>
|
|
<description>Latency sensitive</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRITICAL</name>
|
|
<description>Latency critical</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN2</name>
|
|
<description>Level 2 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLPRI3</name>
|
|
<description>Level 3 Channel Priority Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QOS3</name>
|
|
<description>Level 3 Quality of Service</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>QOS3Select</name>
|
|
<enumeratedValue>
|
|
<name>REGULAR</name>
|
|
<description>Regular delivery</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHORTAGE</name>
|
|
<description>Bandwidth shortage</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENSITIVE</name>
|
|
<description>Latency sensitive</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRITICAL</name>
|
|
<description>Latency critical</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRLVLEN3</name>
|
|
<description>Level 3 Round-Robin Scheduling Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTPEND</name>
|
|
<description>Interrupt Pending</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Transfer Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Transfer Complete</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Fetch Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEND</name>
|
|
<description>Pending</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHINT0</name>
|
|
<description>Channel 0 Pending Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT1</name>
|
|
<description>Channel 1 Pending Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT2</name>
|
|
<description>Channel 2 Pending Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT3</name>
|
|
<description>Channel 3 Pending Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT4</name>
|
|
<description>Channel 4 Pending Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT5</name>
|
|
<description>Channel 5 Pending Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT6</name>
|
|
<description>Channel 6 Pending Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT7</name>
|
|
<description>Channel 7 Pending Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT8</name>
|
|
<description>Channel 8 Pending Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT9</name>
|
|
<description>Channel 9 Pending Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT10</name>
|
|
<description>Channel 10 Pending Interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT11</name>
|
|
<description>Channel 11 Pending Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT12</name>
|
|
<description>Channel 12 Pending Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT13</name>
|
|
<description>Channel 13 Pending Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT14</name>
|
|
<description>Channel 14 Pending Interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT15</name>
|
|
<description>Channel 15 Pending Interrupt</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT16</name>
|
|
<description>Channel 16 Pending Interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT17</name>
|
|
<description>Channel 17 Pending Interrupt</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT18</name>
|
|
<description>Channel 18 Pending Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT19</name>
|
|
<description>Channel 19 Pending Interrupt</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT20</name>
|
|
<description>Channel 20 Pending Interrupt</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT21</name>
|
|
<description>Channel 21 Pending Interrupt</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT22</name>
|
|
<description>Channel 22 Pending Interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT23</name>
|
|
<description>Channel 23 Pending Interrupt</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT24</name>
|
|
<description>Channel 24 Pending Interrupt</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT25</name>
|
|
<description>Channel 25 Pending Interrupt</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT26</name>
|
|
<description>Channel 26 Pending Interrupt</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT27</name>
|
|
<description>Channel 27 Pending Interrupt</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT28</name>
|
|
<description>Channel 28 Pending Interrupt</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT29</name>
|
|
<description>Channel 29 Pending Interrupt</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT30</name>
|
|
<description>Channel 30 Pending Interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT31</name>
|
|
<description>Channel 31 Pending Interrupt</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channels</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYCH0</name>
|
|
<description>Busy Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH1</name>
|
|
<description>Busy Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH2</name>
|
|
<description>Busy Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH3</name>
|
|
<description>Busy Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH4</name>
|
|
<description>Busy Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH5</name>
|
|
<description>Busy Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH6</name>
|
|
<description>Busy Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH7</name>
|
|
<description>Busy Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH8</name>
|
|
<description>Busy Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH9</name>
|
|
<description>Busy Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH10</name>
|
|
<description>Busy Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH11</name>
|
|
<description>Busy Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH12</name>
|
|
<description>Busy Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH13</name>
|
|
<description>Busy Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH14</name>
|
|
<description>Busy Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH15</name>
|
|
<description>Busy Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH16</name>
|
|
<description>Busy Channel 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH17</name>
|
|
<description>Busy Channel 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH18</name>
|
|
<description>Busy Channel 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH19</name>
|
|
<description>Busy Channel 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH20</name>
|
|
<description>Busy Channel 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH21</name>
|
|
<description>Busy Channel 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH22</name>
|
|
<description>Busy Channel 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH23</name>
|
|
<description>Busy Channel 23</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH24</name>
|
|
<description>Busy Channel 24</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH25</name>
|
|
<description>Busy Channel 25</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH26</name>
|
|
<description>Busy Channel 26</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH27</name>
|
|
<description>Busy Channel 27</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH28</name>
|
|
<description>Busy Channel 28</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH29</name>
|
|
<description>Busy Channel 29</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH30</name>
|
|
<description>Busy Channel 30</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH31</name>
|
|
<description>Busy Channel 31</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PENDCH</name>
|
|
<description>Pending Channels</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PENDCH0</name>
|
|
<description>Pending Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH1</name>
|
|
<description>Pending Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH2</name>
|
|
<description>Pending Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH3</name>
|
|
<description>Pending Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH4</name>
|
|
<description>Pending Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH5</name>
|
|
<description>Pending Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH6</name>
|
|
<description>Pending Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH7</name>
|
|
<description>Pending Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH8</name>
|
|
<description>Pending Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH9</name>
|
|
<description>Pending Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH10</name>
|
|
<description>Pending Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH11</name>
|
|
<description>Pending Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH12</name>
|
|
<description>Pending Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH13</name>
|
|
<description>Pending Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH14</name>
|
|
<description>Pending Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH15</name>
|
|
<description>Pending Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH16</name>
|
|
<description>Pending Channel 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH17</name>
|
|
<description>Pending Channel 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH18</name>
|
|
<description>Pending Channel 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH19</name>
|
|
<description>Pending Channel 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH20</name>
|
|
<description>Pending Channel 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH21</name>
|
|
<description>Pending Channel 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH22</name>
|
|
<description>Pending Channel 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH23</name>
|
|
<description>Pending Channel 23</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH24</name>
|
|
<description>Pending Channel 24</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH25</name>
|
|
<description>Pending Channel 25</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH26</name>
|
|
<description>Pending Channel 26</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH27</name>
|
|
<description>Pending Channel 27</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH28</name>
|
|
<description>Pending Channel 28</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH29</name>
|
|
<description>Pending Channel 29</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH30</name>
|
|
<description>Pending Channel 30</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDCH31</name>
|
|
<description>Pending Channel 31</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTIVE</name>
|
|
<description>Active Channel and Levels</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LVLEX0</name>
|
|
<description>Level 0 Channel Trigger Request Executing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX1</name>
|
|
<description>Level 1 Channel Trigger Request Executing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX2</name>
|
|
<description>Level 2 Channel Trigger Request Executing</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVLEX3</name>
|
|
<description>Level 3 Channel Trigger Request Executing</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Active Channel ID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABUSY</name>
|
|
<description>Active Channel Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTCNT</name>
|
|
<description>Active Channel Block Transfer Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASEADDR</name>
|
|
<description>Descriptor Memory Section Base Address</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BASEADDR</name>
|
|
<description>Descriptor Memory Base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRBADDR</name>
|
|
<description>Write-Back Memory Section Base Address</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRBADDR</name>
|
|
<description>Write-Back Memory Base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<name>CHANNEL[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x40</addressOffset>
|
|
<register>
|
|
<name>CHCTRLA</name>
|
|
<description>Channel n Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Channel Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Channel Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIGSRC</name>
|
|
<description>Trigger Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRIGSRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Only software/event triggers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGACT</name>
|
|
<description>Trigger Action</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRIGACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>BLOCK</name>
|
|
<description>One trigger required for each block transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST</name>
|
|
<description>One trigger required for each burst transfer</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSACTION</name>
|
|
<description>One trigger required for each transaction</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BURSTLEN</name>
|
|
<description>Burst Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BURSTLENSelect</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single-beat burst length</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2BEAT</name>
|
|
<description>2-beats burst length</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3BEAT</name>
|
|
<description>3-beats burst length</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BEAT</name>
|
|
<description>4-beats burst length</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5BEAT</name>
|
|
<description>5-beats burst length</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6BEAT</name>
|
|
<description>6-beats burst length</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7BEAT</name>
|
|
<description>7-beats burst length</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BEAT</name>
|
|
<description>8-beats burst length</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9BEAT</name>
|
|
<description>9-beats burst length</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BEAT</name>
|
|
<description>10-beats burst length</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11BEAT</name>
|
|
<description>11-beats burst length</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12BEAT</name>
|
|
<description>12-beats burst length</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13BEAT</name>
|
|
<description>13-beats burst length</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14BEAT</name>
|
|
<description>14-beats burst length</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15BEAT</name>
|
|
<description>15-beats burst length</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BEAT</name>
|
|
<description>16-beats burst length</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRESHOLD</name>
|
|
<description>FIFO Threshold</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>THRESHOLDSelect</name>
|
|
<enumeratedValue>
|
|
<name>1BEAT</name>
|
|
<description>Destination write starts after each beat source address read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2BEATS</name>
|
|
<description>Destination write starts after 2-beats source address read</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BEATS</name>
|
|
<description>Destination write starts after 4-beats source address read</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BEATS</name>
|
|
<description>Destination write starts after 8-beats source address read</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTRLB</name>
|
|
<description>Channel n Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Software Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOACT</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>Channel suspend operation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>Channel resume operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPRILVL</name>
|
|
<description>Channel n Priority Level</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRILVL</name>
|
|
<description>Channel Priority Level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRILVLSelect</name>
|
|
<enumeratedValue>
|
|
<name>LVL0</name>
|
|
<description>Channel Priority Level 0 (Lowest Level)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LVL1</name>
|
|
<description>Channel Priority Level 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LVL2</name>
|
|
<description>Channel Priority Level 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LVL3</name>
|
|
<description>Channel Priority Level 3 (Highest Level)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHEVCTRL</name>
|
|
<description>Channel n Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Channel Event Input Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOACT</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG</name>
|
|
<description>Transfer and periodic transfer trigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTRIG</name>
|
|
<description>Conditional transfer trigger</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CBLOCK</name>
|
|
<description>Conditional block transfer</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>Channel suspend operation</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>Channel resume operation</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSKIP</name>
|
|
<description>Skip next block suspend action</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCPRI</name>
|
|
<description>Increase priority</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVOMODE</name>
|
|
<description>Channel Event Output Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVOMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Block event output selection. Refer to BTCTRL.EVOSEL for available selections.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGACT</name>
|
|
<description>Ongoing trigger action</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVIE</name>
|
|
<description>Channel Event Input Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVOE</name>
|
|
<description>Channel Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENCLR</name>
|
|
<description>Channel n Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENSET</name>
|
|
<description>Channel n Interrupt Enable Set</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTFLAG</name>
|
|
<description>Channel n Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERR</name>
|
|
<description>Channel Transfer Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMPL</name>
|
|
<description>Channel Transfer Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Channel Suspend</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSTATUS</name>
|
|
<description>Channel n Status</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEND</name>
|
|
<description>Channel Pending</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Channel Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Channel Fetch Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>Channel CRC Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DSU</name>
|
|
<version>U24101.0.0</version>
|
|
<description>Device Service Unit</description>
|
|
<groupName>DSU</groupName>
|
|
<prependToName>DSU_</prependToName>
|
|
<baseAddress>0x41002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>32-bit Cyclic Redundancy Code</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBIST</name>
|
|
<description>Memory built-in self-test</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Chip-Erase</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auxiliary Row Read</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMSA</name>
|
|
<description>Start Memory Stream Access</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSA</name>
|
|
<description>Status A</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRSTEXT</name>
|
|
<description>CPU Reset Phase Extension</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAIL</name>
|
|
<description>Failure</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Protection Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSB</name>
|
|
<description>Status B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PROT</name>
|
|
<description>Protected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGPRES</name>
|
|
<description>Debugger Present</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCD0</name>
|
|
<description>Debug Communication Channel 0 Dirty</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCD1</name>
|
|
<description>Debug Communication Channel 1 Dirty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPE</name>
|
|
<description>Hot-Plugging Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CELCK</name>
|
|
<description>Chip Erase Locked</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCCD0</name>
|
|
<description>Test Debug Communication Channel 0 Dirty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCCD1</name>
|
|
<description>Test Debug Communication Channel 1 Dirty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AMOD</name>
|
|
<description>Access Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>Length</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>DCC[%s]</name>
|
|
<description>Debug Communication Channel n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DID</name>
|
|
<description>Device Identification</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x60060203</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIE</name>
|
|
<description>Die Number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERIES</name>
|
|
<description>Series</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SERIESSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cortex-M0+ processor, basic feature set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cortex-M0+ processor, USB</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAMILY</name>
|
|
<description>Family</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FAMILYSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General purpose microcontroller</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PicoPower</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROCESSOR</name>
|
|
<description>Processor</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PROCESSORSelect</name>
|
|
<enumeratedValue>
|
|
<name>CM0P</name>
|
|
<description>Cortex-M0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM23</name>
|
|
<description>Cortex-M23</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM3</name>
|
|
<description>Cortex-M3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM4</name>
|
|
<description>Cortex-M4</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM4F</name>
|
|
<description>Cortex-M4 with FPU</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM33</name>
|
|
<description>Cortex-M33</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LQOS</name>
|
|
<description>Latency Quality Of Service</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCCDMALEVEL</name>
|
|
<description>DMA Trigger Level</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DCCDMALEVELSelect</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Trigger rises when DCC is empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>Trigger rises when DCC is full</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETBRAMEN</name>
|
|
<description>Trace Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>DCFG[%s]</name>
|
|
<description>Device Configuration</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCFG</name>
|
|
<description>Device Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENTRY0</name>
|
|
<description>CoreSight ROM Table Entry 0</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x9F0FC002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPRES</name>
|
|
<description>Entry Present</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMT</name>
|
|
<description>Format</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDOFF</name>
|
|
<description>Address Offset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENTRY1</name>
|
|
<description>CoreSight ROM Table Entry 1</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>END</name>
|
|
<description>CoreSight ROM Table End</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>END</name>
|
|
<description>End Marker</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEMTYPE</name>
|
|
<description>CoreSight ROM Table Memory Type</description>
|
|
<addressOffset>0x1FCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEMP</name>
|
|
<description>System Memory Present</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID4</name>
|
|
<description>Peripheral Identification 4</description>
|
|
<addressOffset>0x1FD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JEPCC</name>
|
|
<description>JEP-106 Continuation Code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FKBC</name>
|
|
<description>4KB count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID5</name>
|
|
<description>Peripheral Identification 5</description>
|
|
<addressOffset>0x1FD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID6</name>
|
|
<description>Peripheral Identification 6</description>
|
|
<addressOffset>0x1FD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID7</name>
|
|
<description>Peripheral Identification 7</description>
|
|
<addressOffset>0x1FDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PID0</name>
|
|
<description>Peripheral Identification 0</description>
|
|
<addressOffset>0x1FE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNBL</name>
|
|
<description>Part Number Low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID1</name>
|
|
<description>Peripheral Identification 1</description>
|
|
<addressOffset>0x1FE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000FC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNBH</name>
|
|
<description>Part Number High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEPIDCL</name>
|
|
<description>Low part of the JEP-106 Identity Code</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID2</name>
|
|
<description>Peripheral Identification 2</description>
|
|
<addressOffset>0x1FE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000009</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JEPIDCH</name>
|
|
<description>JEP-106 Identity Code High</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEPU</name>
|
|
<description>JEP-106 Identity Code is used</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID3</name>
|
|
<description>Peripheral Identification 3</description>
|
|
<addressOffset>0x1FEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CUSMOD</name>
|
|
<description>ARM CUSMOD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>Revision Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID0</name>
|
|
<description>Component Identification 0</description>
|
|
<addressOffset>0x1FF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB0</name>
|
|
<description>Preamble Byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID1</name>
|
|
<description>Component Identification 1</description>
|
|
<addressOffset>0x1FF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLE</name>
|
|
<description>Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLASS</name>
|
|
<description>Component Class</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID2</name>
|
|
<description>Component Identification 2</description>
|
|
<addressOffset>0x1FF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB2</name>
|
|
<description>Preamble Byte 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID3</name>
|
|
<description>Component Identification 3</description>
|
|
<addressOffset>0x1FFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMBLEB3</name>
|
|
<description>Preamble Byte 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EIC</name>
|
|
<version>U22543.0.0</version>
|
|
<description>External Interrupt Controller</description>
|
|
<groupName>EIC</groupName>
|
|
<prependToName>EIC_</prependToName>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_0</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_1</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_2</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_3</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_4</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_5</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_6</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_7</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_8</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_9</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_10</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_11</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_12</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_13</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_14</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EIC_EXTINT_15</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>Clock Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>CLK_GCLK</name>
|
|
<description>Clocked by GCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_ULP32K</name>
|
|
<description>Clocked by ULP32K</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMICTRL</name>
|
|
<description>Non-Maskable Interrupt Control</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NMISENSE</name>
|
|
<description>Non-Maskable Interrupt Sense Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NMISENSESelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising-edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling-edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both-edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High-level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low-level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIFILTEN</name>
|
|
<description>Non-Maskable Interrupt Filter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMIASYNCH</name>
|
|
<description>Asynchronous Edge Detection Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NMIASYNCHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>Edge detection is clock synchronously operated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>Edge detection is clock asynchronously operated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMIFLAG</name>
|
|
<description>Non-Maskable Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>Non-Maskable Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINTEO</name>
|
|
<description>External Interrupt Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASYNCH</name>
|
|
<description>External Interrupt Asynchronous Mode</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCH</name>
|
|
<description>Asynchronous Edge Detection Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ASYNCHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>Edge detection is clock synchronously operated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>Edge detection is clock asynchronously operated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CONFIG[%s]</name>
|
|
<description>External Interrupt Sense Configuration</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SENSE0</name>
|
|
<description>Input Sense Configuration 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE0Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN0</name>
|
|
<description>Filter Enable 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE1</name>
|
|
<description>Input Sense Configuration 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE1Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN1</name>
|
|
<description>Filter Enable 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE2</name>
|
|
<description>Input Sense Configuration 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE2Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN2</name>
|
|
<description>Filter Enable 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE3</name>
|
|
<description>Input Sense Configuration 3</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE3Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN3</name>
|
|
<description>Filter Enable 3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE4</name>
|
|
<description>Input Sense Configuration 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE4Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN4</name>
|
|
<description>Filter Enable 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE5</name>
|
|
<description>Input Sense Configuration 5</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE5Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN5</name>
|
|
<description>Filter Enable 5</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE6</name>
|
|
<description>Input Sense Configuration 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE6Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN6</name>
|
|
<description>Filter Enable 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SENSE7</name>
|
|
<description>Input Sense Configuration 7</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SENSE7Select</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rising edge detection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Falling edge detection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High level detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low level detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN7</name>
|
|
<description>Filter Enable 7</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBOUNCEN</name>
|
|
<description>Debouncer Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEBOUNCEN</name>
|
|
<description>Debouncer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPRESCALER</name>
|
|
<description>Debouncer Prescaler</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER0</name>
|
|
<description>Debouncer Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALER0Select</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>EIC clock divided by 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>EIC clock divided by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>EIC clock divided by 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>EIC clock divided by 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>EIC clock divided by 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>EIC clock divided by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>EIC clock divided by 128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>EIC clock divided by 256</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATES0</name>
|
|
<description>Debouncer number of states</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STATES0Select</name>
|
|
<enumeratedValue>
|
|
<name>LFREQ3</name>
|
|
<description>3 low frequency samples</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFREQ7</name>
|
|
<description>7 low frequency samples</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER1</name>
|
|
<description>Debouncer Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALER1Select</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>EIC clock divided by 2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>EIC clock divided by 4</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>EIC clock divided by 8</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>EIC clock divided by 16</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>EIC clock divided by 32</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>EIC clock divided by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>EIC clock divided by 128</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>EIC clock divided by 256</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATES1</name>
|
|
<description>Debouncer number of states</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STATES1Select</name>
|
|
<enumeratedValue>
|
|
<name>LFREQ3</name>
|
|
<description>3 low frequency samples</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFREQ7</name>
|
|
<description>7 low frequency samples</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TICKON</name>
|
|
<description>Pin Sampler frequency selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TICKONSelect</name>
|
|
<enumeratedValue>
|
|
<name>CLK_GCLK_EIC</name>
|
|
<description>Clocked by GCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_LFREQ</name>
|
|
<description>Clocked by Low Frequency Clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINSTATE</name>
|
|
<description>Pin State</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PINSTATE</name>
|
|
<description>Pin State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EVSYS</name>
|
|
<version>U25041.0.0</version>
|
|
<description>Event System Interface</description>
|
|
<groupName>EVSYS</groupName>
|
|
<prependToName>EVSYS_</prependToName>
|
|
<baseAddress>0x4100E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2BC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EVSYS_0</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_1</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_2</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_3</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EVSYS_OTHER</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVT</name>
|
|
<description>Software Event</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL0</name>
|
|
<description>Channel 0 Software Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL1</name>
|
|
<description>Channel 1 Software Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL2</name>
|
|
<description>Channel 2 Software Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL3</name>
|
|
<description>Channel 3 Software Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL4</name>
|
|
<description>Channel 4 Software Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL5</name>
|
|
<description>Channel 5 Software Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL6</name>
|
|
<description>Channel 6 Software Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL7</name>
|
|
<description>Channel 7 Software Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL8</name>
|
|
<description>Channel 8 Software Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL9</name>
|
|
<description>Channel 9 Software Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL10</name>
|
|
<description>Channel 10 Software Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL11</name>
|
|
<description>Channel 11 Software Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL12</name>
|
|
<description>Channel 12 Software Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL13</name>
|
|
<description>Channel 13 Software Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL14</name>
|
|
<description>Channel 14 Software Selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL15</name>
|
|
<description>Channel 15 Software Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL16</name>
|
|
<description>Channel 16 Software Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL17</name>
|
|
<description>Channel 17 Software Selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL18</name>
|
|
<description>Channel 18 Software Selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL19</name>
|
|
<description>Channel 19 Software Selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL20</name>
|
|
<description>Channel 20 Software Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL21</name>
|
|
<description>Channel 21 Software Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL22</name>
|
|
<description>Channel 22 Software Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL23</name>
|
|
<description>Channel 23 Software Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL24</name>
|
|
<description>Channel 24 Software Selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL25</name>
|
|
<description>Channel 25 Software Selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL26</name>
|
|
<description>Channel 26 Software Selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL27</name>
|
|
<description>Channel 27 Software Selection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL28</name>
|
|
<description>Channel 28 Software Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL29</name>
|
|
<description>Channel 29 Software Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL30</name>
|
|
<description>Channel 30 Software Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL31</name>
|
|
<description>Channel 31 Software Selection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRICTRL</name>
|
|
<description>Priority Control</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Channel Priority Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RREN</name>
|
|
<description>Round-Robin Scheduling Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTPEND</name>
|
|
<description>Channel Pending Interrupt</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x4000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Channel ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READY</name>
|
|
<description>Ready</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHINT0</name>
|
|
<description>Channel 0 Pending Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT1</name>
|
|
<description>Channel 1 Pending Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT2</name>
|
|
<description>Channel 2 Pending Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT3</name>
|
|
<description>Channel 3 Pending Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT4</name>
|
|
<description>Channel 4 Pending Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT5</name>
|
|
<description>Channel 5 Pending Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT6</name>
|
|
<description>Channel 6 Pending Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT7</name>
|
|
<description>Channel 7 Pending Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT8</name>
|
|
<description>Channel 8 Pending Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT9</name>
|
|
<description>Channel 9 Pending Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT10</name>
|
|
<description>Channel 10 Pending Interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHINT11</name>
|
|
<description>Channel 11 Pending Interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channels</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYCH0</name>
|
|
<description>Busy Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH1</name>
|
|
<description>Busy Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH2</name>
|
|
<description>Busy Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH3</name>
|
|
<description>Busy Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH4</name>
|
|
<description>Busy Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH5</name>
|
|
<description>Busy Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH6</name>
|
|
<description>Busy Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH7</name>
|
|
<description>Busy Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH8</name>
|
|
<description>Busy Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH9</name>
|
|
<description>Busy Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH10</name>
|
|
<description>Busy Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH11</name>
|
|
<description>Busy Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READYUSR</name>
|
|
<description>Ready Users</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READYUSR0</name>
|
|
<description>Ready User for Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR1</name>
|
|
<description>Ready User for Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR2</name>
|
|
<description>Ready User for Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR3</name>
|
|
<description>Ready User for Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR4</name>
|
|
<description>Ready User for Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR5</name>
|
|
<description>Ready User for Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR6</name>
|
|
<description>Ready User for Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR7</name>
|
|
<description>Ready User for Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR8</name>
|
|
<description>Ready User for Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR9</name>
|
|
<description>Ready User for Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR10</name>
|
|
<description>Ready User for Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>READYUSR11</name>
|
|
<description>Ready User for Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<name>CHANNEL[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x020</addressOffset>
|
|
<register>
|
|
<name>CHANNEL</name>
|
|
<description>Channel n Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVGEN</name>
|
|
<description>Event Generator Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PATH</name>
|
|
<description>Path Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PATHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS</name>
|
|
<description>Synchronous path</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNCHRONIZED</name>
|
|
<description>Resynchronized path</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS</name>
|
|
<description>Asynchronous path</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGSEL</name>
|
|
<description>Edge Detection Selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EDGSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO_EVT_OUTPUT</name>
|
|
<description>No event output when using the resynchronized or synchronous path</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in standby</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Generic Clock On Demand</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENCLR</name>
|
|
<description>Channel n Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTENSET</name>
|
|
<description>Channel n Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHINTFLAG</name>
|
|
<description>Channel n Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Channel Overrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVD</name>
|
|
<description>Channel Event Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSTATUS</name>
|
|
<description>Channel n Status</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDYUSR</name>
|
|
<description>Ready User</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSYCH</name>
|
|
<description>Busy Channel</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<register>
|
|
<dim>67</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>USER[%s]</name>
|
|
<description>User Multiplexer n</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL</name>
|
|
<description>Channel Event Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FREQM</name>
|
|
<version>U22571.1.0</version>
|
|
<description>Frequency Meter</description>
|
|
<groupName>FREQM</groupName>
|
|
<prependToName>FREQM_</prependToName>
|
|
<baseAddress>0x40002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FREQM</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGA</name>
|
|
<description>Config A register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REFNUM</name>
|
|
<description>Number of Reference Clock Cycles</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set Register</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>FREQM Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Sticky Count Value Overflow</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VALUE</name>
|
|
<description>Count Value Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Measurement Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GCLK</name>
|
|
<version>U21221.2.0</version>
|
|
<description>Generic Clock Generator</description>
|
|
<groupName>GCLK</groupName>
|
|
<prependToName>GCLK_</prependToName>
|
|
<baseAddress>0x40001C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1A0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchroniation Busy bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCTRL</name>
|
|
<description>Generic Clock Generator Control n Synchronization Busy bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<enumeratedValues>
|
|
<name>GENCTRLSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK0</name>
|
|
<description>Generic clock generator 0</description>
|
|
<value>0x0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK1</name>
|
|
<description>Generic clock generator 1</description>
|
|
<value>0x0002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK2</name>
|
|
<description>Generic clock generator 2</description>
|
|
<value>0x0004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK3</name>
|
|
<description>Generic clock generator 3</description>
|
|
<value>0x0008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK4</name>
|
|
<description>Generic clock generator 4</description>
|
|
<value>0x0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK5</name>
|
|
<description>Generic clock generator 5</description>
|
|
<value>0x0020</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK6</name>
|
|
<description>Generic clock generator 6</description>
|
|
<value>0x0040</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK7</name>
|
|
<description>Generic clock generator 7</description>
|
|
<value>0x0080</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK8</name>
|
|
<description>Generic clock generator 8</description>
|
|
<value>0x0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK9</name>
|
|
<description>Generic clock generator 9</description>
|
|
<value>0x0200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK10</name>
|
|
<description>Generic clock generator 10</description>
|
|
<value>0x0400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK11</name>
|
|
<description>Generic clock generator 11</description>
|
|
<value>0x0800</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GENCTRL[%s]</name>
|
|
<description>Generic Clock Generator Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRC</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>XOSC0</name>
|
|
<description>XOSC0 oscillator output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC1</name>
|
|
<description>XOSC1 oscillator output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLKIN</name>
|
|
<description>Generator input pad</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLKGEN1</name>
|
|
<description>Generic clock generator 1 output</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSCULP32K</name>
|
|
<description>OSCULP32K oscillator output</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC32K</name>
|
|
<description>XOSC32K oscillator output</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DFLL</name>
|
|
<description>DFLL output</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPLL0</name>
|
|
<description>DPLL0 output</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPLL1</name>
|
|
<description>DPLL1 output</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GENEN</name>
|
|
<description>Generic Clock Generator Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDC</name>
|
|
<description>Improve Duty Cycle</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OOV</name>
|
|
<description>Output Off Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIVSEL</name>
|
|
<description>Divide Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIVSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Divide input directly by divider factor</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide input by 2^(divider factor+ 1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Division Factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>48</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PCHCTRL[%s]</name>
|
|
<description>Peripheral Clock Control</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GEN</name>
|
|
<description>Generic Clock Generator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>GENSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK0</name>
|
|
<description>Generic clock generator 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK1</name>
|
|
<description>Generic clock generator 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK2</name>
|
|
<description>Generic clock generator 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK3</name>
|
|
<description>Generic clock generator 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK4</name>
|
|
<description>Generic clock generator 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK5</name>
|
|
<description>Generic clock generator 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK6</name>
|
|
<description>Generic clock generator 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK7</name>
|
|
<description>Generic clock generator 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK8</name>
|
|
<description>Generic clock generator 8</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK9</name>
|
|
<description>Generic clock generator 9</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK10</name>
|
|
<description>Generic clock generator 10</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCLK11</name>
|
|
<description>Generic clock generator 11</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HMATRIX</name>
|
|
<version>I76382.1.4</version>
|
|
<description>HSB Matrix</description>
|
|
<groupName>HMATRIXB</groupName>
|
|
<prependToName>HMATRIXB_</prependToName>
|
|
<baseAddress>0x4100C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xB0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<cluster>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<name>PRS[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x080</addressOffset>
|
|
<register>
|
|
<name>PRAS</name>
|
|
<description>Priority A for Slave</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PRBS</name>
|
|
<description>Priority B for Slave</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ICM</name>
|
|
<version>U20101.2.0</version>
|
|
<description>Integrity Check Monitor</description>
|
|
<groupName>ICM</groupName>
|
|
<prependToName>ICM_</prependToName>
|
|
<baseAddress>0x42002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x58</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ICM</name>
|
|
<value>132</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WBDIS</name>
|
|
<description>Write Back Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOMDIS</name>
|
|
<description>End of Monitoring Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLBDIS</name>
|
|
<description>Secondary List Branching Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBC</name>
|
|
<description>Bus Burden Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASCD</name>
|
|
<description>Automatic Switch To Compare Digest</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALBUFF</name>
|
|
<description>Dual Input Buffer</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIHASH</name>
|
|
<description>User Initial Hash Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UALGO</name>
|
|
<description>User SHA Algorithm</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>UALGOSelect</name>
|
|
<enumeratedValue>
|
|
<name>SHA1</name>
|
|
<description>SHA1 Algorithm</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHA256</name>
|
|
<description>SHA256 Algorithm</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHA224</name>
|
|
<description>SHA224 Algorithm</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAPROT</name>
|
|
<description>Region Hash Area Protection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAPROT</name>
|
|
<description>Region Descriptor Area Protection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>ICM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>ICM Disable Register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REHASH</name>
|
|
<description>Recompute Internal Hash</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMDIS</name>
|
|
<description>Region Monitoring Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Region Monitoring Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>ICM Controller Enable Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAWRMDIS</name>
|
|
<description>RAW Region Monitoring Disabled Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMDIS</name>
|
|
<description>Region Monitoring Disabled Status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RHC</name>
|
|
<description>Region Hash Completed Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDM</name>
|
|
<description>Region Digest Mismatch Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBE</name>
|
|
<description>Region Bus Error Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWC</name>
|
|
<description>Region Wrap Condition detected Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Region End bit Condition Detected Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSU</name>
|
|
<description>Region Status Updated Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URAD</name>
|
|
<description>Undefined Register Access Detection Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RHC</name>
|
|
<description>Region Hash Completed Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDM</name>
|
|
<description>Region Digest Mismatch Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBE</name>
|
|
<description>Region Bus Error Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWC</name>
|
|
<description>Region Wrap Condition Detected Interrupt Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Region End bit Condition detected Interrupt Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSU</name>
|
|
<description>Region Status Updated Interrupt Disable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URAD</name>
|
|
<description>Undefined Register Access Detection Interrupt Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RHC</name>
|
|
<description>Region Hash Completed Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDM</name>
|
|
<description>Region Digest Mismatch Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBE</name>
|
|
<description>Region Bus Error Interrupt Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWC</name>
|
|
<description>Region Wrap Condition Detected Interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Region End bit Condition Detected Interrupt Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSU</name>
|
|
<description>Region Status Updated Interrupt Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URAD</name>
|
|
<description>Undefined Register Access Detection Interrupt Mask</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RHC</name>
|
|
<description>Region Hash Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDM</name>
|
|
<description>Region Digest Mismatch</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBE</name>
|
|
<description>Region Bus Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWC</name>
|
|
<description>Region Wrap Condition Detected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Region End bit Condition Detected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSU</name>
|
|
<description>Region Status Updated Detected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URAD</name>
|
|
<description>Undefined Register Access Detection Status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UASR</name>
|
|
<description>Undefined Access Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>URAT</name>
|
|
<description>Undefined Register Access Trace</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>URATSelect</name>
|
|
<enumeratedValue>
|
|
<name>UNSPEC_STRUCT_MEMBER</name>
|
|
<description>Unspecified structure member set to one detected when the descriptor is loaded</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CFG_MODIFIED</name>
|
|
<description>CFG modified during active monitoring</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSCR_MODIFIED</name>
|
|
<description>DSCR modified during active monitoring</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HASH_MODIFIED</name>
|
|
<description>HASH modified during active monitoring</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ_ACCESS</name>
|
|
<description>Write-only register read access</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCR</name>
|
|
<description>Region Descriptor Area Start Address</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DASA</name>
|
|
<description>Descriptor Area Start Address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>26</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HASH</name>
|
|
<description>Region Hash Area Start Address</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HASA</name>
|
|
<description>Hash Area Start Address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>UIHVAL[%s]</name>
|
|
<description>User Initial Hash Value n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Initial Hash Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2S</name>
|
|
<version>U22242.0.0</version>
|
|
<description>Inter-IC Sound Interface</description>
|
|
<groupName>I2S</groupName>
|
|
<prependToName>I2S_</prependToName>
|
|
<baseAddress>0x43002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2S</name>
|
|
<value>128</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN0</name>
|
|
<description>Clock Unit 0 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN1</name>
|
|
<description>Clock Unit 1 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Tx Serializer Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Rx Serializer Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CLKCTRL[%s]</name>
|
|
<description>Clock Unit n Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLOTSIZE</name>
|
|
<description>Slot Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLOTSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8-bit Slot for Clock Unit n</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16-bit Slot for Clock Unit n</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>24-bit Slot for Clock Unit n</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32-bit Slot for Clock Unit n</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NBSLOTS</name>
|
|
<description>Number of Slots in Frame</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSWIDTH</name>
|
|
<description>Frame Sync Width</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSWIDTHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SLOT</name>
|
|
<description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>Frame Sync Pulse is half a Frame wide</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT</name>
|
|
<description>Frame Sync Pulse is 1 Bit wide</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST</name>
|
|
<description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITDELAY</name>
|
|
<description>Data Delay from Frame Sync</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BITDELAYSelect</name>
|
|
<enumeratedValue>
|
|
<name>LJ</name>
|
|
<description>Left Justified (0 Bit Delay)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S</name>
|
|
<description>I2S (1 Bit Delay)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSSEL</name>
|
|
<description>Frame Sync Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>SCKDIV</name>
|
|
<description>Divided Serial Clock n is used as Frame Sync n source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSPIN</name>
|
|
<description>FSn input pin is used as Frame Sync n source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSINV</name>
|
|
<description>Frame Sync Invert</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSOUTINV</name>
|
|
<description>Frame Sync Output Invert</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCKSEL</name>
|
|
<description>Serial Clock Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SCKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>MCKDIV</name>
|
|
<description>Divided Master Clock n is used as Serial Clock n source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCKPIN</name>
|
|
<description>SCKn input pin is used as Serial Clock n source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKOUTINV</name>
|
|
<description>Serial Clock Output Invert</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKSEL</name>
|
|
<description>Master Clock Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MCKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>GCLK_I2S_n is used as Master Clock n source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCKPIN</name>
|
|
<description>MCKn input pin is used as Master Clock n source</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCKEN</name>
|
|
<description>Master Clock Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKOUTINV</name>
|
|
<description>Master Clock Output Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKDIV</name>
|
|
<description>Master Clock Division Factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKOUTDIV</name>
|
|
<description>Master Clock Output Division Factor</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY0</name>
|
|
<description>Receive Ready 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY1</name>
|
|
<description>Receive Ready 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR0</name>
|
|
<description>Receive Overrun 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR1</name>
|
|
<description>Receive Overrun 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY0</name>
|
|
<description>Transmit Ready 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY1</name>
|
|
<description>Transmit Ready 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR0</name>
|
|
<description>Transmit Underrun 0 Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR1</name>
|
|
<description>Transmit Underrun 1 Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY0</name>
|
|
<description>Receive Ready 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY1</name>
|
|
<description>Receive Ready 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR0</name>
|
|
<description>Receive Overrun 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR1</name>
|
|
<description>Receive Overrun 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY0</name>
|
|
<description>Transmit Ready 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY1</name>
|
|
<description>Transmit Ready 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR0</name>
|
|
<description>Transmit Underrun 0 Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR1</name>
|
|
<description>Transmit Underrun 1 Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY0</name>
|
|
<description>Receive Ready 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXRDY1</name>
|
|
<description>Receive Ready 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR0</name>
|
|
<description>Receive Overrun 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOR1</name>
|
|
<description>Receive Overrun 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY0</name>
|
|
<description>Transmit Ready 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY1</name>
|
|
<description>Transmit Ready 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR0</name>
|
|
<description>Transmit Underrun 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUR1</name>
|
|
<description>Transmit Underrun 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN0</name>
|
|
<description>Clock Unit 0 Enable Synchronization Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN1</name>
|
|
<description>Clock Unit 1 Enable Synchronization Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Tx Serializer Enable Synchronization Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Rx Serializer Enable Synchronization Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Tx Data Synchronization Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>Rx Data Synchronization Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCTRL</name>
|
|
<description>Tx Serializer Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SERMODE</name>
|
|
<description>Serializer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SERMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>RX</name>
|
|
<description>Receive</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TX</name>
|
|
<description>Transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM2</name>
|
|
<description>Receive one PDM data on each serial clock edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDEFAULT</name>
|
|
<description>Line Default Line when Slot Disabled</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TXDEFAULTSelect</name>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Output Default Value is 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>Output Default Value is 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Output Default Value is high impedance</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXSAME</name>
|
|
<description>Transmit Data when Underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TXSAMESelect</name>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Zero data transmitted in case of underrun</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAME</name>
|
|
<description>Last data transmitted in case of underrun</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Unit Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>CLK0</name>
|
|
<description>Use Clock Unit 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK1</name>
|
|
<description>Use Clock Unit 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOTADJ</name>
|
|
<description>Data Slot Formatting Adjust</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLOTADJSelect</name>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right adjusted in slot</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left adjusted in slot</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATASIZE</name>
|
|
<description>Data Word Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATASIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>24 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>20</name>
|
|
<description>20 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>18</name>
|
|
<description>18 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 bits</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16C</name>
|
|
<description>16 bits compact stereo</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8C</name>
|
|
<description>8 bits compact stereo</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WORDADJ</name>
|
|
<description>Data Word Formatting Adjust</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WORDADJSelect</name>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right adjusted in word</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left adjusted in word</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTEND</name>
|
|
<description>Data Formatting Bit Extension</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EXTENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Extend with zeroes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>Extend with ones</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSBIT</name>
|
|
<description>Extend with Most Significant Bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSBIT</name>
|
|
<description>Extend with Least Significant Bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITREV</name>
|
|
<description>Data Formatting Bit Reverse</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BITREVSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSBIT</name>
|
|
<description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSBIT</name>
|
|
<description>Transfer Data Least Significant Bit (LSB) first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS0</name>
|
|
<description>Slot 0 Disabled for this Serializer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS1</name>
|
|
<description>Slot 1 Disabled for this Serializer</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS2</name>
|
|
<description>Slot 2 Disabled for this Serializer</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS3</name>
|
|
<description>Slot 3 Disabled for this Serializer</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS4</name>
|
|
<description>Slot 4 Disabled for this Serializer</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS5</name>
|
|
<description>Slot 5 Disabled for this Serializer</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS6</name>
|
|
<description>Slot 6 Disabled for this Serializer</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS7</name>
|
|
<description>Slot 7 Disabled for this Serializer</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Mono Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MONOSelect</name>
|
|
<enumeratedValue>
|
|
<name>STEREO</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONO</name>
|
|
<description>Left channel data is duplicated to right channel</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>Single or Multiple DMA Channels</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMASelect</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single DMA channel</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIPLE</name>
|
|
<description>One DMA channel per data channel</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCTRL</name>
|
|
<description>Rx Serializer Control</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SERMODE</name>
|
|
<description>Serializer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SERMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>RX</name>
|
|
<description>Receive</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDM2</name>
|
|
<description>Receive one PDM data on each serial clock edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Unit Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>CLK0</name>
|
|
<description>Use Clock Unit 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK1</name>
|
|
<description>Use Clock Unit 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOTADJ</name>
|
|
<description>Data Slot Formatting Adjust</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLOTADJSelect</name>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right adjusted in slot</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left adjusted in slot</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATASIZE</name>
|
|
<description>Data Word Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATASIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>24 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>20</name>
|
|
<description>20 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>18</name>
|
|
<description>18 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 bits</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16C</name>
|
|
<description>16 bits compact stereo</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8C</name>
|
|
<description>8 bits compact stereo</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WORDADJ</name>
|
|
<description>Data Word Formatting Adjust</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WORDADJSelect</name>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right adjusted in word</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left adjusted in word</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTEND</name>
|
|
<description>Data Formatting Bit Extension</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EXTENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Extend with zeroes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>Extend with ones</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSBIT</name>
|
|
<description>Extend with Most Significant Bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSBIT</name>
|
|
<description>Extend with Least Significant Bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITREV</name>
|
|
<description>Data Formatting Bit Reverse</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BITREVSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSBIT</name>
|
|
<description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSBIT</name>
|
|
<description>Transfer Data Least Significant Bit (LSB) first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS0</name>
|
|
<description>Slot 0 Disabled for this Serializer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS1</name>
|
|
<description>Slot 1 Disabled for this Serializer</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS2</name>
|
|
<description>Slot 2 Disabled for this Serializer</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS3</name>
|
|
<description>Slot 3 Disabled for this Serializer</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS4</name>
|
|
<description>Slot 4 Disabled for this Serializer</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS5</name>
|
|
<description>Slot 5 Disabled for this Serializer</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS6</name>
|
|
<description>Slot 6 Disabled for this Serializer</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTDIS7</name>
|
|
<description>Slot 7 Disabled for this Serializer</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Mono Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MONOSelect</name>
|
|
<enumeratedValue>
|
|
<name>STEREO</name>
|
|
<description>Normal mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONO</name>
|
|
<description>Left channel data is duplicated to right channel</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>Single or Multiple DMA Channels</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMASelect</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single DMA channel</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIPLE</name>
|
|
<description>One DMA channel per data channel</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXLOOP</name>
|
|
<description>Loop-back Test Mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Tx Data</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Sample Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Rx Data</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Sample Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCLK</name>
|
|
<version>U24081.0.0</version>
|
|
<description>Main Clock</description>
|
|
<groupName>MCLK</groupName>
|
|
<prependToName>MCLK_</prependToName>
|
|
<baseAddress>0x40000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MCLK</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKRDY</name>
|
|
<description>Clock Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSDIV</name>
|
|
<description>HS Clock Division</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>CPU Clock Division Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIVSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUDIV</name>
|
|
<description>CPU Clock Division</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Low-Power Clock Division Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIVSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide by 128</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBMASK</name>
|
|
<description>AHB Mask</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00FFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPB0_</name>
|
|
<description>HPB0 AHB Clock Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB1_</name>
|
|
<description>HPB1 AHB Clock Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB2_</name>
|
|
<description>HPB2 AHB Clock Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB3_</name>
|
|
<description>HPB3 AHB Clock Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU AHB Clock Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HMATRIX_</name>
|
|
<description>HMATRIX AHB Clock Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL AHB Clock Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSRAM_</name>
|
|
<description>HSRAM AHB Clock Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCC_</name>
|
|
<description>CMCC AHB Clock Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC AHB Clock Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USB_</name>
|
|
<description>USB AHB Clock Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKUPRAM_</name>
|
|
<description>BKUPRAM AHB Clock Mask</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC AHB Clock Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_</name>
|
|
<description>QSPI AHB Clock Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDHC0_</name>
|
|
<description>SDHC0 AHB Clock Mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDHC1_</name>
|
|
<description>SDHC1 AHB Clock Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICM_</name>
|
|
<description>ICM AHB Clock Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUKCC_</name>
|
|
<description>PUKCC AHB Clock Mask</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_2X_</name>
|
|
<description>QSPI_2X AHB Clock Mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_SMEEPROM_</name>
|
|
<description>NVMCTRL_SMEEPROM AHB Clock Mask</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_CACHE_</name>
|
|
<description>NVMCTRL_CACHE AHB Clock Mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBAMASK</name>
|
|
<description>APBA Mask</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x000007FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC APB Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL APB Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT APB Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 APB Clock Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 APB Clock Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 APB Clock Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 APB Clock Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBBMASK</name>
|
|
<description>APBB Mask</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00018056</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USB_</name>
|
|
<description>USB APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HMATRIX_</name>
|
|
<description>HMATRIX APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM2_</name>
|
|
<description>SERCOM2 APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM3_</name>
|
|
<description>SERCOM3 APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC0_</name>
|
|
<description>TCC0 APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC1_</name>
|
|
<description>TCC1 APB Clock Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 APB Clock Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC3_</name>
|
|
<description>TC3 APB Clock Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMECC_</name>
|
|
<description>RAMECC APB Clock Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBCMASK</name>
|
|
<description>APBC Mask</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00002000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCC2_</name>
|
|
<description>TCC2 APB Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC3_</name>
|
|
<description>TCC3 APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC4_</name>
|
|
<description>TC4 APB Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC5_</name>
|
|
<description>TC5 APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDEC_</name>
|
|
<description>PDEC APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC APB Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AES_</name>
|
|
<description>AES APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICM_</name>
|
|
<description>ICM APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_</name>
|
|
<description>QSPI APB Clock Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL APB Clock Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBDMASK</name>
|
|
<description>APBD Mask</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SERCOM4_</name>
|
|
<description>SERCOM4 APB Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM5_</name>
|
|
<description>SERCOM5 APB Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM6_</name>
|
|
<description>SERCOM6 APB Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM7_</name>
|
|
<description>SERCOM7 APB Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC4_</name>
|
|
<description>TCC4 APB Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC6_</name>
|
|
<description>TC6 APB Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC7_</name>
|
|
<description>TC7 APB Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_</name>
|
|
<description>ADC0 APB Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_</name>
|
|
<description>ADC1 APB Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC APB Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2S_</name>
|
|
<description>I2S APB Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCC_</name>
|
|
<description>PCC APB Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVMCTRL</name>
|
|
<version>U24091.0.0</version>
|
|
<description>Non-Volatile Memory Controller</description>
|
|
<groupName>NVMCTRL</groupName>
|
|
<prependToName>NVMCTRL_</prependToName>
|
|
<baseAddress>0x41004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>NVMCTRL_0</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>NVMCTRL_1</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOWS</name>
|
|
<description>Auto Wait State Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSPEN</name>
|
|
<description>Suspend Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WMODE</name>
|
|
<description>Write Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>MAN</name>
|
|
<description>Manual Write</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADW</name>
|
|
<description>Automatic Double Word Write</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AQW</name>
|
|
<description>Automatic Quad Word</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AP</name>
|
|
<description>Automatic Page Write</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRM</name>
|
|
<description>Power Reduction Mode during Sleep</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRMSelect</name>
|
|
<enumeratedValue>
|
|
<name>SEMIAUTO</name>
|
|
<description>NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULLAUTO</name>
|
|
<description>NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MANUAL</name>
|
|
<description>NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWS</name>
|
|
<description>NVM Read Wait States</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHBNS0</name>
|
|
<description>Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHBNS1</name>
|
|
<description>Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CACHEDIS0</name>
|
|
<description>AHB0 Cache Disable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CACHEDIS1</name>
|
|
<description>AHB1 Cache Disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>EP</name>
|
|
<description>Erase Page - Only supported in the USER and AUX pages.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EB</name>
|
|
<description>Erase Block - Erases the block addressed by the ADDR register, not supported in the user page</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WP</name>
|
|
<description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WQW</name>
|
|
<description>Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWRST</name>
|
|
<description>Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LR</name>
|
|
<description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UR</name>
|
|
<description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPRM</name>
|
|
<description>Sets the power reduction mode.</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPRM</name>
|
|
<description>Clears the power reduction mode.</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PBC</name>
|
|
<description>Page Buffer Clear - Clears the page buffer.</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSB</name>
|
|
<description>Set Security Bit</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BKSWRST</name>
|
|
<description>Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CELCK</name>
|
|
<description>Chip Erase Lock - DSU.CE command is not available</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEULCK</name>
|
|
<description>Chip Erase Unlock - DSU.CE command is available</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBPDIS</name>
|
|
<description>Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CBPDIS</name>
|
|
<description>Clears STATUS.BPDIS, Boot loader protection is not discarded</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASEES0</name>
|
|
<description>Activate SmartEEPROM Sector 0, deactivate Sector 1</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASEES1</name>
|
|
<description>Activate SmartEEPROM Sector 1, deactivate Sector 0</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEERALOC</name>
|
|
<description>Starts SmartEEPROM sector reallocation algorithm</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEEFLUSH</name>
|
|
<description>Flush SMEE data when in buffered mode</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSEE</name>
|
|
<description>Lock access to SmartEEPROM data from any mean</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USEE</name>
|
|
<description>Unlock access to SmartEEPROM data</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSEER</name>
|
|
<description>Lock access to the SmartEEPROM Register Address Space (above 64KB)</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USEER</name>
|
|
<description>Unlock access to the SmartEEPROM Register Address Space (above 64KB)</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEX</name>
|
|
<description>Command Execution</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDEXSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Execution Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>NVM Parameter</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00060000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NVMP</name>
|
|
<description>NVM Pages</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSZ</name>
|
|
<description>Page Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PSZSelect</name>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 bytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 bytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128</name>
|
|
<description>128 bytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256</name>
|
|
<description>256 bytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 bytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 bytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEE</name>
|
|
<description>SmartEEPROM Supported</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SEESelect</name>
|
|
<enumeratedValue>
|
|
<name>A</name>
|
|
<description>163840 bytes</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9</name>
|
|
<description>147456 bytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>131072 bytes</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7</name>
|
|
<description>114688 bytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>98304 bytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5</name>
|
|
<description>81920 bytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>65536 bytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>49152 bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>32768 bytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>16384 bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>0 bytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Command Done Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRE</name>
|
|
<description>Address Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCSE</name>
|
|
<description>ECC Single Error Interrupt Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCDE</name>
|
|
<description>ECC Dual Error Interrupt Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error Interrupt Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspended Write Or Erase Interrupt Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESFULL</name>
|
|
<description>Active SEES Full Interrupt Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESOVF</name>
|
|
<description>Active SEES Overflow Interrupt Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEEWRC</name>
|
|
<description>SEE Write Completed Interrupt Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Command Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRE</name>
|
|
<description>Address Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCSE</name>
|
|
<description>ECC Single Error Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCDE</name>
|
|
<description>ECC Dual Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspended Write Or Erase Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESFULL</name>
|
|
<description>Active SEES Full Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESOVF</name>
|
|
<description>Active SEES Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEEWRC</name>
|
|
<description>SEE Write Completed Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Command Done</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRE</name>
|
|
<description>Address Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROGE</name>
|
|
<description>Programming Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKE</name>
|
|
<description>Lock Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCSE</name>
|
|
<description>ECC Single Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCDE</name>
|
|
<description>ECC Dual Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVME</name>
|
|
<description>NVM Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspended Write Or Erase Operation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESFULL</name>
|
|
<description>Active SEES Full</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEESOVF</name>
|
|
<description>Active SEES Overflow</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEEWRC</name>
|
|
<description>SEE Write Completed</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>READY</name>
|
|
<description>Ready to accept a command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRM</name>
|
|
<description>Power Reduction Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>NVM Page Buffer Active Loading</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>NVM Write Or Erase Operation Is Suspended</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFIRST</name>
|
|
<description>BANKA First</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPDIS</name>
|
|
<description>Boot Loader Protection Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOOTPROT</name>
|
|
<description>Boot Loader Protection Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BOOTPROTSelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>0 kbytes</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8 kbytes</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>16 kbytes</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>24 kbytes</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>32 kbytes</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40</name>
|
|
<description>40 kbytes</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>48</name>
|
|
<description>48 kbytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>56</name>
|
|
<description>56 kbytes</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64</name>
|
|
<description>64 kbytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>72</name>
|
|
<description>72 kbytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80</name>
|
|
<description>80 kbytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>88</name>
|
|
<description>88 kbytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>96</name>
|
|
<description>96 kbytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>104</name>
|
|
<description>104 kbytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>112</name>
|
|
<description>112 kbytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>120</name>
|
|
<description>120 kbytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>NVM Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RUNLOCK</name>
|
|
<description>Lock Section</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RUNLOCK</name>
|
|
<description>Region Un-Lock Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PBLDATA[%s]</name>
|
|
<description>Page Buffer Load Data x</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Page Buffer Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCERR</name>
|
|
<description>ECC Error Status Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Error Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPEL</name>
|
|
<description>Low Double-Word Error Type</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TYPELSelect</name>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>No Error Detected Since Last Read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Single</name>
|
|
<description>At Least One Single Error Detected Since last Read</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Dual</name>
|
|
<description>At Least One Dual Error Detected Since Last Read</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TYPEH</name>
|
|
<description>High Double-Word Error Type</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TYPEHSelect</name>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>No Error Detected Since Last Read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Single</name>
|
|
<description>At Least One Single Error Detected Since last Read</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Dual</name>
|
|
<description>At Least One Dual Error Detected Since Last Read</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCDIS</name>
|
|
<description>Debugger ECC Read Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCELOG</name>
|
|
<description>Debugger ECC Error Tracking Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEECFG</name>
|
|
<description>SmartEEPROM Configuration Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WMODE</name>
|
|
<description>Write Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>UNBUFFERED</name>
|
|
<description>A NVM write command is issued after each write in the pagebuffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFFERED</name>
|
|
<description>A NVM write command is issued when a write to a new page is requested</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>APRDIS</name>
|
|
<description>Automatic Page Reallocation Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEESTAT</name>
|
|
<description>SmartEEPROM Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASEES</name>
|
|
<description>Active SmartEEPROM Sector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>Page Buffer Loaded</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>SmartEEPROM Write Access Is Locked</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RLOCK</name>
|
|
<description>SmartEEPROM Write Access To Register Address Space Is Locked</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBLK</name>
|
|
<description>Blocks Number In a Sector</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSZ</name>
|
|
<description>SmartEEPROM Page Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSCCTRL</name>
|
|
<version>U24011.0.0</version>
|
|
<description>Oscillators Control</description>
|
|
<groupName>OSCCTRL</groupName>
|
|
<prependToName>OSCCTRL_</prependToName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x58</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>OSCCTRL_XOSC0</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>OSCCTRL_XOSC1</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>OSCCTRL_DFLL</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>OSCCTRL_DPLL0</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>OSCCTRL_DPLL1</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEO0</name>
|
|
<description>Clock 0 Failure Detector Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CFDEO1</name>
|
|
<description>Clock 1 Failure Detector Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY0</name>
|
|
<description>XOSC 0 Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCRDY1</name>
|
|
<description>XOSC 1 Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL0</name>
|
|
<description>XOSC 0 Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL1</name>
|
|
<description>XOSC 1 Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRDY</name>
|
|
<description>DFLL Ready Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLOOB</name>
|
|
<description>DFLL Out Of Bounds Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKF</name>
|
|
<description>DFLL Lock Fine Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKC</name>
|
|
<description>DFLL Lock Coarse Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRCS</name>
|
|
<description>DFLL Reference Clock Stopped Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKR</name>
|
|
<description>DPLL0 Lock Rise Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKF</name>
|
|
<description>DPLL0 Lock Fall Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LTO</name>
|
|
<description>DPLL0 Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LDRTO</name>
|
|
<description>DPLL0 Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKR</name>
|
|
<description>DPLL1 Lock Rise Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKF</name>
|
|
<description>DPLL1 Lock Fall Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LTO</name>
|
|
<description>DPLL1 Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LDRTO</name>
|
|
<description>DPLL1 Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY0</name>
|
|
<description>XOSC 0 Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCRDY1</name>
|
|
<description>XOSC 1 Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL0</name>
|
|
<description>XOSC 0 Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL1</name>
|
|
<description>XOSC 1 Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRDY</name>
|
|
<description>DFLL Ready Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLOOB</name>
|
|
<description>DFLL Out Of Bounds Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKF</name>
|
|
<description>DFLL Lock Fine Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKC</name>
|
|
<description>DFLL Lock Coarse Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRCS</name>
|
|
<description>DFLL Reference Clock Stopped Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKR</name>
|
|
<description>DPLL0 Lock Rise Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKF</name>
|
|
<description>DPLL0 Lock Fall Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LTO</name>
|
|
<description>DPLL0 Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LDRTO</name>
|
|
<description>DPLL0 Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKR</name>
|
|
<description>DPLL1 Lock Rise Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKF</name>
|
|
<description>DPLL1 Lock Fall Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LTO</name>
|
|
<description>DPLL1 Lock Timeout Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LDRTO</name>
|
|
<description>DPLL1 Loop Divider Ratio Update Complete Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY0</name>
|
|
<description>XOSC 0 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCRDY1</name>
|
|
<description>XOSC 1 Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL0</name>
|
|
<description>XOSC 0 Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL1</name>
|
|
<description>XOSC 1 Clock Failure Detector</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRDY</name>
|
|
<description>DFLL Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLOOB</name>
|
|
<description>DFLL Out Of Bounds</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKF</name>
|
|
<description>DFLL Lock Fine</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKC</name>
|
|
<description>DFLL Lock Coarse</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRCS</name>
|
|
<description>DFLL Reference Clock Stopped</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKR</name>
|
|
<description>DPLL0 Lock Rise</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKF</name>
|
|
<description>DPLL0 Lock Fall</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LTO</name>
|
|
<description>DPLL0 Lock Timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LDRTO</name>
|
|
<description>DPLL0 Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKR</name>
|
|
<description>DPLL1 Lock Rise</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKF</name>
|
|
<description>DPLL1 Lock Fall</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LTO</name>
|
|
<description>DPLL1 Lock Timeout</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LDRTO</name>
|
|
<description>DPLL1 Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSCRDY0</name>
|
|
<description>XOSC 0 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCRDY1</name>
|
|
<description>XOSC 1 Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL0</name>
|
|
<description>XOSC 0 Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCFAIL1</name>
|
|
<description>XOSC 1 Clock Failure Detector</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCCKSW0</name>
|
|
<description>XOSC 0 Clock Switch</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSCCKSW1</name>
|
|
<description>XOSC 1 Clock Switch</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRDY</name>
|
|
<description>DFLL Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLOOB</name>
|
|
<description>DFLL Out Of Bounds</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKF</name>
|
|
<description>DFLL Lock Fine</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLLCKC</name>
|
|
<description>DFLL Lock Coarse</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLRCS</name>
|
|
<description>DFLL Reference Clock Stopped</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKR</name>
|
|
<description>DPLL0 Lock Rise</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LCKF</name>
|
|
<description>DPLL0 Lock Fall</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0TO</name>
|
|
<description>DPLL0 Timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL0LDRTO</name>
|
|
<description>DPLL0 Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKR</name>
|
|
<description>DPLL1 Lock Rise</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LCKF</name>
|
|
<description>DPLL1 Lock Fall</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1TO</name>
|
|
<description>DPLL1 Timeout</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLL1LDRTO</name>
|
|
<description>DPLL1 Loop Divider Ratio Update Complete</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>XOSCCTRL[%s]</name>
|
|
<description>External Multipurpose Crystal Oscillator Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XTALEN</name>
|
|
<description>Crystal Oscillator Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWBUFGAIN</name>
|
|
<description>Low Buffer Gain Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPTAT</name>
|
|
<description>Oscillator Current Reference</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IMULT</name>
|
|
<description>Oscillator Current Multiplier</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENALC</name>
|
|
<description>Automatic Loop Control Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CFDEN</name>
|
|
<description>Clock Failure Detector Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWBEN</name>
|
|
<description>Xosc Clock Switch Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Start-Up Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STARTUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYCLE1</name>
|
|
<description>31 us</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE2</name>
|
|
<description>61 us</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE4</name>
|
|
<description>122 us</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE8</name>
|
|
<description>244 us</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE16</name>
|
|
<description>488 us</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE32</name>
|
|
<description>977 us</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE64</name>
|
|
<description>1953 us</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE128</name>
|
|
<description>3906 us</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE256</name>
|
|
<description>7813 us</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE512</name>
|
|
<description>15625 us</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE1024</name>
|
|
<description>31250 us</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE2048</name>
|
|
<description>62500 us</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE4096</name>
|
|
<description>125000 us</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE8192</name>
|
|
<description>250000 us</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE16384</name>
|
|
<description>500000 us</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE32768</name>
|
|
<description>1000000 us</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFDPRESC</name>
|
|
<description>Clock Failure Detector Prescaler</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CFDPRESCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>48 MHz</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>24 MHz</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>12 MHz</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>6 MHz</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>3 MHz</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>1.5 MHz</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>0.75 MHz</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>0.3125 MHz</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLCTRLA</name>
|
|
<description>DFLL48M Control A</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x82</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DFLL Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLCTRLB</name>
|
|
<description>DFLL48M Control B</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STABLE</name>
|
|
<description>Stable DFLL Frequency</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LLAW</name>
|
|
<description>Lose Lock After Wake</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBCRM</name>
|
|
<description>USB Clock Recovery Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCDIS</name>
|
|
<description>Chill Cycle Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QLDIS</name>
|
|
<description>Quick Lock Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPLCKC</name>
|
|
<description>Bypass Coarse Lock</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITLOCK</name>
|
|
<description>Wait Lock</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLVAL</name>
|
|
<description>DFLL48M Value</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FINE</name>
|
|
<description>Fine Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COARSE</name>
|
|
<description>Coarse Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Multiplication Ratio Difference</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLMUL</name>
|
|
<description>DFLL48M Multiplier</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUL</name>
|
|
<description>DFLL Multiply Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSTEP</name>
|
|
<description>Fine Maximum Step</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSTEP</name>
|
|
<description>Coarse Maximum Step</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFLLSYNC</name>
|
|
<description>DFLL48M Synchronization</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>ENABLE Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLCTRLB</name>
|
|
<description>DFLLCTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLVAL</name>
|
|
<description>DFLLVAL Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFLLMUL</name>
|
|
<description>DFLLMUL Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x14</dimIncrement>
|
|
<name>DPLL[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x30</addressOffset>
|
|
<register>
|
|
<name>DPLLCTRLA</name>
|
|
<description>DPLL Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x80</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DPLL Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLRATIO</name>
|
|
<description>DPLL Ratio Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LDR</name>
|
|
<description>Loop Divider Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDRFRAC</name>
|
|
<description>Loop Divider Ratio Fractional Part</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLCTRLB</name>
|
|
<description>DPLL Control B</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000020</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Proportional Integral Filter Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FILTERSelect</name>
|
|
<enumeratedValue>
|
|
<name>FILTER1</name>
|
|
<description>Bandwidth = 92.7Khz and Damping Factor = 0.76</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER2</name>
|
|
<description>Bandwidth = 131Khz and Damping Factor = 1.08</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER3</name>
|
|
<description>Bandwidth = 46.4Khz and Damping Factor = 0.38</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER4</name>
|
|
<description>Bandwidth = 65.6Khz and Damping Factor = 0.54</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER5</name>
|
|
<description>Bandwidth = 131Khz and Damping Factor = 0.56</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER6</name>
|
|
<description>Bandwidth = 185Khz and Damping Factor = 0.79</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER7</name>
|
|
<description>Bandwidth = 65.6Khz and Damping Factor = 0.28</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER8</name>
|
|
<description>Bandwidth = 92.7Khz and Damping Factor = 0.39</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER9</name>
|
|
<description>Bandwidth = 46.4Khz and Damping Factor = 1.49</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER10</name>
|
|
<description>Bandwidth = 65.6Khz and Damping Factor = 2.11</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER11</name>
|
|
<description>Bandwidth = 23.2Khz and Damping Factor = 0.75</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER12</name>
|
|
<description>Bandwidth = 32.8Khz and Damping Factor = 1.06</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER13</name>
|
|
<description>Bandwidth = 65.6Khz and Damping Factor = 1.07</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER14</name>
|
|
<description>Bandwidth = 92.7Khz and Damping Factor = 1.51</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER15</name>
|
|
<description>Bandwidth = 32.8Khz and Damping Factor = 0.53</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER16</name>
|
|
<description>Bandwidth = 46.4Khz and Damping Factor = 0.75</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>Wake Up Fast</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCLK</name>
|
|
<description>Reference Clock Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>REFCLKSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Dedicated GCLK clock reference</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC32</name>
|
|
<description>XOSC32K clock reference</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC0</name>
|
|
<description>XOSC0 clock reference</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC1</name>
|
|
<description>XOSC1 clock reference</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LTIME</name>
|
|
<description>Lock Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LTIMESelect</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>No time-out. Automatic lock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>800US</name>
|
|
<description>Time-out if no lock within 800us</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>900US</name>
|
|
<description>Time-out if no lock within 900us</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1MS</name>
|
|
<description>Time-out if no lock within 1ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P1MS</name>
|
|
<description>Time-out if no lock within 1.1ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBYPASS</name>
|
|
<description>Lock Bypass</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCOFILTER</name>
|
|
<description>Sigma-Delta DCO Filter Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DCOFILTERSelect</name>
|
|
<enumeratedValue>
|
|
<name>FILTER1</name>
|
|
<description>Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER2</name>
|
|
<description>Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER3</name>
|
|
<description>Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER4</name>
|
|
<description>Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER5</name>
|
|
<description>Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER6</name>
|
|
<description>Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER7</name>
|
|
<description>Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER8</name>
|
|
<description>Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCOEN</name>
|
|
<description>DCO Filter Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLSYNCBUSY</name>
|
|
<description>DPLL Synchronization Busy</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DPLL Enable Synchronization Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPLLRATIO</name>
|
|
<description>DPLL Loop Divider Ratio Synchronization Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPLLSTATUS</name>
|
|
<description>DPLL Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>DPLL Lock Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKRDY</name>
|
|
<description>DPLL Clock Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC32KCTRL</name>
|
|
<version>U24001.0.0</version>
|
|
<description>32kHz Oscillators Control</description>
|
|
<groupName>OSC32KCTRL</groupName>
|
|
<prependToName>OSC32KCTRL_</prependToName>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>OSC32KCTRL</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSC32KFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSC32KFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSC32KFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Power and Clocks Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XOSC32KRDY</name>
|
|
<description>XOSC32K Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSC32KFAIL</name>
|
|
<description>XOSC32K Clock Failure Detector</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XOSC32KSW</name>
|
|
<description>XOSC32K Clock switch</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCCTRL</name>
|
|
<description>RTC Clock Selection</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTCSEL</name>
|
|
<description>RTC Clock Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RTCSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>ULP1K</name>
|
|
<description>1.024kHz from 32kHz internal ULP oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULP32K</name>
|
|
<description>32.768kHz from 32kHz internal ULP oscillator</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC1K</name>
|
|
<description>1.024kHz from 32.768kHz internal oscillator</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOSC32K</name>
|
|
<description>32.768kHz from 32.768kHz external crystal oscillator</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XOSC32K</name>
|
|
<description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x2080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XTALEN</name>
|
|
<description>Crystal Oscillator Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN32K</name>
|
|
<description>32kHz Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN1K</name>
|
|
<description>1kHz Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STARTUP</name>
|
|
<description>Oscillator Start-Up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STARTUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYCLE2048</name>
|
|
<description>62.6 ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE4096</name>
|
|
<description>125 ms</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE16384</name>
|
|
<description>500 ms</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE32768</name>
|
|
<description>1000 ms</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE65536</name>
|
|
<description>2000 ms</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE131072</name>
|
|
<description>4000 ms</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYCLE262144</name>
|
|
<description>8000 ms</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CGM</name>
|
|
<description>Control Gain Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CGMSelect</name>
|
|
<enumeratedValue>
|
|
<name>XT</name>
|
|
<description>Standard mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HS</name>
|
|
<description>High Speed mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFDCTRL</name>
|
|
<description>Clock Failure Detector Control</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEN</name>
|
|
<description>Clock Failure Detector Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWBACK</name>
|
|
<description>Clock Switch Back</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CFDPRESC</name>
|
|
<description>Clock Failure Detector Prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFDEO</name>
|
|
<description>Clock Failure Detector Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCULP32K</name>
|
|
<description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN32K</name>
|
|
<description>Enable Out 32k</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN1K</name>
|
|
<description>Enable Out 1k</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALIB</name>
|
|
<description>Oscillator Calibration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRTLOCK</name>
|
|
<description>Write Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PAC</name>
|
|
<version>U21201.2.0</version>
|
|
<description>Peripheral Access Controller</description>
|
|
<groupName>PAC</groupName>
|
|
<prependToName>PAC_</prependToName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x44</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PAC</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WRCTRL</name>
|
|
<description>Write control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERID</name>
|
|
<description>Peripheral identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Peripheral access control key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>KEYSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR</name>
|
|
<description>Clear protection</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set protection</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETLCK</name>
|
|
<description>Set and lock protection</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERREO</name>
|
|
<description>Peripheral acess error event output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt enable clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Peripheral access error interrupt disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt enable set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Peripheral access error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGAHB</name>
|
|
<description>Bridge interrupt flag status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_</name>
|
|
<description>FLASH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ALT_</name>
|
|
<description>FLASH_ALT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEEPROM_</name>
|
|
<description>SEEPROM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMCM4S_</name>
|
|
<description>RAMCM4S</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMPPPDSU_</name>
|
|
<description>RAMPPPDSU</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMDMAWR_</name>
|
|
<description>RAMDMAWR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMDMACICM_</name>
|
|
<description>RAMDMACICM</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB0_</name>
|
|
<description>HPB0</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB1_</name>
|
|
<description>HPB1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB2_</name>
|
|
<description>HPB2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPB3_</name>
|
|
<description>HPB3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUKCC_</name>
|
|
<description>PUKCC</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDHC0_</name>
|
|
<description>SDHC0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDHC1_</name>
|
|
<description>SDHC1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_</name>
|
|
<description>QSPI</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKUPRAM_</name>
|
|
<description>BKUPRAM</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGA</name>
|
|
<description>Peripheral interrupt flag status - Bridge A</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGB</name>
|
|
<description>Peripheral interrupt flag status - Bridge B</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USB_</name>
|
|
<description>USB</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCC_</name>
|
|
<description>CMCC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HMATRIX_</name>
|
|
<description>HMATRIX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM2_</name>
|
|
<description>SERCOM2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM3_</name>
|
|
<description>SERCOM3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC0_</name>
|
|
<description>TCC0</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC1_</name>
|
|
<description>TCC1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC3_</name>
|
|
<description>TC3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMECC_</name>
|
|
<description>RAMECC</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGC</name>
|
|
<description>Peripheral interrupt flag status - Bridge C</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCC2_</name>
|
|
<description>TCC2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC3_</name>
|
|
<description>TCC3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC4_</name>
|
|
<description>TC4</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC5_</name>
|
|
<description>TC5</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDEC_</name>
|
|
<description>PDEC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AES_</name>
|
|
<description>AES</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICM_</name>
|
|
<description>ICM</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUKCC_</name>
|
|
<description>PUKCC</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_</name>
|
|
<description>QSPI</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAGD</name>
|
|
<description>Peripheral interrupt flag status - Bridge D</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SERCOM4_</name>
|
|
<description>SERCOM4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM5_</name>
|
|
<description>SERCOM5</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM6_</name>
|
|
<description>SERCOM6</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM7_</name>
|
|
<description>SERCOM7</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC4_</name>
|
|
<description>TCC4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC6_</name>
|
|
<description>TC6</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC7_</name>
|
|
<description>TC7</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_</name>
|
|
<description>ADC0</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_</name>
|
|
<description>ADC1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2S_</name>
|
|
<description>I2S</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCC_</name>
|
|
<description>PCC</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSA</name>
|
|
<description>Peripheral write protection status - Bridge A</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00010000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAC_</name>
|
|
<description>PAC APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM_</name>
|
|
<description>PM APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCLK_</name>
|
|
<description>MCLK APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC_</name>
|
|
<description>RSTC APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSCCTRL_</name>
|
|
<description>OSCCTRL APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSC32KCTRL_</name>
|
|
<description>OSC32KCTRL APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUPC_</name>
|
|
<description>SUPC APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCLK_</name>
|
|
<description>GCLK APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT_</name>
|
|
<description>WDT APB Protect Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_</name>
|
|
<description>RTC APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIC_</name>
|
|
<description>EIC APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQM_</name>
|
|
<description>FREQM APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM0_</name>
|
|
<description>SERCOM0 APB Protect Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM1_</name>
|
|
<description>SERCOM1 APB Protect Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC0_</name>
|
|
<description>TC0 APB Protect Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1_</name>
|
|
<description>TC1 APB Protect Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSB</name>
|
|
<description>Peripheral write protection status - Bridge B</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USB_</name>
|
|
<description>USB APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSU_</name>
|
|
<description>DSU APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVMCTRL_</name>
|
|
<description>NVMCTRL APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCC_</name>
|
|
<description>CMCC APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORT_</name>
|
|
<description>PORT APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAC_</name>
|
|
<description>DMAC APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HMATRIX_</name>
|
|
<description>HMATRIX APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVSYS_</name>
|
|
<description>EVSYS APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM2_</name>
|
|
<description>SERCOM2 APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM3_</name>
|
|
<description>SERCOM3 APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC0_</name>
|
|
<description>TCC0 APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC1_</name>
|
|
<description>TCC1 APB Protect Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2_</name>
|
|
<description>TC2 APB Protect Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC3_</name>
|
|
<description>TC3 APB Protect Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMECC_</name>
|
|
<description>RAMECC APB Protect Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSC</name>
|
|
<description>Peripheral write protection status - Bridge C</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCC2_</name>
|
|
<description>TCC2 APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC3_</name>
|
|
<description>TCC3 APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC4_</name>
|
|
<description>TC4 APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC5_</name>
|
|
<description>TC5 APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDEC_</name>
|
|
<description>PDEC APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AC_</name>
|
|
<description>AC APB Protect Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AES_</name>
|
|
<description>AES APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_</name>
|
|
<description>TRNG APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICM_</name>
|
|
<description>ICM APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUKCC_</name>
|
|
<description>PUKCC APB Protect Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QSPI_</name>
|
|
<description>QSPI APB Protect Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCL_</name>
|
|
<description>CCL APB Protect Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUSD</name>
|
|
<description>Peripheral write protection status - Bridge D</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SERCOM4_</name>
|
|
<description>SERCOM4 APB Protect Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM5_</name>
|
|
<description>SERCOM5 APB Protect Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM6_</name>
|
|
<description>SERCOM6 APB Protect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SERCOM7_</name>
|
|
<description>SERCOM7 APB Protect Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCC4_</name>
|
|
<description>TCC4 APB Protect Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC6_</name>
|
|
<description>TC6 APB Protect Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC7_</name>
|
|
<description>TC7 APB Protect Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_</name>
|
|
<description>ADC0 APB Protect Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_</name>
|
|
<description>ADC1 APB Protect Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC_</name>
|
|
<description>DAC APB Protect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2S_</name>
|
|
<description>I2S APB Protect Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCC_</name>
|
|
<description>PCC APB Protect Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCC</name>
|
|
<version>U20171.1.0</version>
|
|
<description>Parallel Capture Controller</description>
|
|
<groupName>PCC</groupName>
|
|
<prependToName>PCC_</prependToName>
|
|
<baseAddress>0x43002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCC</name>
|
|
<value>129</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>Parallel Capture Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Data size</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCALE</name>
|
|
<description>Scale data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALWYS</name>
|
|
<description>Always Sampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALFS</name>
|
|
<description>Half Sampling</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSTS</name>
|
|
<description>First sample</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISIZE</name>
|
|
<description>Input Data Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CID</name>
|
|
<description>Clear If Disabled</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>Interrupt Disable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Ready Interrupt Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRE</name>
|
|
<description>Overrun Error Interrupt Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHR</name>
|
|
<description>Reception Holding Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Reception Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPMR</name>
|
|
<description>Write Protection Mode Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WPKEY</name>
|
|
<description>Write Protection Key</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPSR</name>
|
|
<description>Write Protection Status Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPVS</name>
|
|
<description>Write Protection Violation Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WPVSRC</name>
|
|
<description>Write Protection Violation Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PDEC</name>
|
|
<version>U22631.0.0</version>
|
|
<description>Quadrature Decodeur</description>
|
|
<groupName>PDEC</groupName>
|
|
<prependToName>PDEC_</prependToName>
|
|
<baseAddress>0x42001C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PDEC_OTHER</name>
|
|
<value>115</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PDEC_MC0</name>
|
|
<value>116</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PDEC_MC1</name>
|
|
<value>117</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operation Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>QDEC</name>
|
|
<description>QDEC operating mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALL</name>
|
|
<description>HALL operating mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER</name>
|
|
<description>COUNTER operating mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONF</name>
|
|
<description>PDEC Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CONFSelect</name>
|
|
<enumeratedValue>
|
|
<name>X4</name>
|
|
<description>Quadrature decoder direction</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4S</name>
|
|
<description>Secure Quadrature decoder direction</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X2</name>
|
|
<description>Decoder direction</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X2S</name>
|
|
<description>Secure decoder direction</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOC</name>
|
|
<description>Auto correction mode</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>PDEC Phase A and B Swap</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREN</name>
|
|
<description>Period Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINEN0</name>
|
|
<description>PDEC Input From Pin 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINEN1</name>
|
|
<description>PDEC Input From Pin 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINEN2</name>
|
|
<description>PDEC Input From Pin 2 Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINVEN0</name>
|
|
<description>IO Pin 0 Invert Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINVEN1</name>
|
|
<description>IO Pin 1 Invert Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINVEN2</name>
|
|
<description>IO Pin 2 Invert Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANGULAR</name>
|
|
<description>Angular Counter Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAXCMP</name>
|
|
<description>Maximum Consecutive Missing Pulses</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a counter restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double buffered registers</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start QDEC/HALL</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop QDEC/HALL</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a counter restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double buffered registers</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start QDEC/HALL</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop QDEC/HALL</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVINV</name>
|
|
<description>Inverted Event Input Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEI</name>
|
|
<description>Event Input Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow/Underflow Output Event Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERREO</name>
|
|
<description>Error Output Event Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIREO</name>
|
|
<description>Direction Output Event Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VLCEO</name>
|
|
<description>Velocity Output Event Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>Match Channel 0 Event Output Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>Match Channel 1 Event Output Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow/Underflow Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VLC</name>
|
|
<description>Velocity Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Channel 0 Compare Match Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Channel 1 Compare Match Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow/Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VLC</name>
|
|
<description>Velocity Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Channel 0 Compare Match Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Channel 1 Compare Match Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow/Underflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction Change</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VLC</name>
|
|
<description>Velocity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Channel 0 Compare Match</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Channel 1 Compare Match</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>QERR</name>
|
|
<description>Quadrature Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXERR</name>
|
|
<description>Index Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPERR</name>
|
|
<description>Missing Pulse Error flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINERR</name>
|
|
<description>Window Error Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HERR</name>
|
|
<description>Hall Error Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction Status Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCBUFV</name>
|
|
<description>Prescaler Buffer Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTERBUFV</name>
|
|
<description>Filter Buffer Valid</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare Channel 0 Buffer Valid</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare Channel 1 Buffer Valid</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Run Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>Control B Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>Status Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Filter Synchronization Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Synchronization Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0 Synchronization Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1 Synchronization Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Value</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>No division</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide by 4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide by 8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide by 16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide by 32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide by 64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide by 128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide by 256</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>Divide by 512</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Divide by 1024</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Filter Value</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Filter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESCBUF</name>
|
|
<description>Prescaler Buffer Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCBUF</name>
|
|
<description>Prescaler Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCBUFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>No division</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide by 4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide by 8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide by 16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide by 32</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide by 64</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide by 128</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide by 256</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>Divide by 512</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Divide by 1024</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERBUF</name>
|
|
<description>Filter Buffer Value</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FILTERBUF</name>
|
|
<description>Filter Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>Channel n Compare Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Channel Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>Channel Compare Buffer Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Channel Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PM</name>
|
|
<version>U24061.0.0</version>
|
|
<description>Power Manager</description>
|
|
<groupName>PM</groupName>
|
|
<prependToName>PM_</prependToName>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PM</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IORET</name>
|
|
<description>I/O Retention</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLEEPCFG</name>
|
|
<description>Sleep Configuration</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x02</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPMODE</name>
|
|
<description>Sleep Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>CPU, AHBx, and APBx clocks are OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>All Clocks are OFF</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIBERNATE</name>
|
|
<description>Backup domain is ON as well as some PDRAMs</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BACKUP</name>
|
|
<description>Only Backup domain is powered ON</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All power domains are powered OFF</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPRDY</name>
|
|
<description>Sleep Mode Entry Ready Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPRDY</name>
|
|
<description>Sleep Mode Entry Ready Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPRDY</name>
|
|
<description>Sleep Mode Entry Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STDBYCFG</name>
|
|
<description>Standby Configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAMCFG</name>
|
|
<description>Ram Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RAMCFGSelect</name>
|
|
<enumeratedValue>
|
|
<name>RET</name>
|
|
<description>All the system RAM is retained</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARTIAL</name>
|
|
<description>Only the first 32Kbytes of the system RAM is retained</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All the system RAM is turned OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FASTWKUP</name>
|
|
<description>Fast Wakeup</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FASTWKUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Fast Wakeup is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVM</name>
|
|
<description>Fast Wakeup is enabled on NVM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAINVREG</name>
|
|
<description>Fast Wakeup is enabled on the main voltage regulator (MAINVREG)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Fast Wakeup is enabled on both NVM and MAINVREG</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HIBCFG</name>
|
|
<description>Hibernate Configuration</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAMCFG</name>
|
|
<description>Ram Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RAMCFGSelect</name>
|
|
<enumeratedValue>
|
|
<name>RET</name>
|
|
<description>All the system RAM is retained</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARTIAL</name>
|
|
<description>Only the first 32Kbytes of the system RAM is retained</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All the system RAM is turned OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRAMCFG</name>
|
|
<description>Backup Ram Configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRAMCFGSelect</name>
|
|
<enumeratedValue>
|
|
<name>RET</name>
|
|
<description>All the backup RAM is retained</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARTIAL</name>
|
|
<description>Only the first 4Kbytes of the backup RAM is retained</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All the backup RAM is turned OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKUPCFG</name>
|
|
<description>Backup Configuration</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BRAMCFG</name>
|
|
<description>Ram Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRAMCFGSelect</name>
|
|
<enumeratedValue>
|
|
<name>RET</name>
|
|
<description>All the backup RAM is retained</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARTIAL</name>
|
|
<description>Only the first 4Kbytes of the backup RAM is retained</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>All the backup RAM is turned OFF</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWSAKDLY</name>
|
|
<description>Power Switch Acknowledge Delay</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYVAL</name>
|
|
<description>Delay Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>Ignore Acknowledge</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORT</name>
|
|
<version>U22102.2.0</version>
|
|
<description>Port Module</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORT_</prependToName>
|
|
<baseAddress>0x41008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x180</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<cluster>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x80</dimIncrement>
|
|
<name>GROUP[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x00</addressOffset>
|
|
<register>
|
|
<name>DIR</name>
|
|
<description>Data Direction</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRCLR</name>
|
|
<description>Data Direction Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRCLR</name>
|
|
<description>Port Data Direction Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRSET</name>
|
|
<description>Data Direction Set</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRSET</name>
|
|
<description>Port Data Direction Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRTGL</name>
|
|
<description>Data Direction Toggle</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIRTGL</name>
|
|
<description>Port Data Direction Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT</name>
|
|
<description>Data Output Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>PORT Data Output Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTCLR</name>
|
|
<description>Data Output Value Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTCLR</name>
|
|
<description>PORT Data Output Value Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTSET</name>
|
|
<description>Data Output Value Set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTSET</name>
|
|
<description>PORT Data Output Value Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTTGL</name>
|
|
<description>Data Output Value Toggle</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTTGL</name>
|
|
<description>PORT Data Output Value Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN</name>
|
|
<description>Data Input Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN</name>
|
|
<description>PORT Data Input Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLING</name>
|
|
<description>Input Sampling Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRCONFIG</name>
|
|
<description>Write Configuration</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PINMASK</name>
|
|
<description>Pin Mask for Multiple Pin Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUXEN</name>
|
|
<description>Peripheral Multiplexer Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PULLEN</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRVSTR</name>
|
|
<description>Output Driver Strength Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUX</name>
|
|
<description>Peripheral Multiplexing</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRPMUX</name>
|
|
<description>Write PMUX</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRPINCFG</name>
|
|
<description>Write PINCFG</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HWSEL</name>
|
|
<description>Half-Word Select</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Input Control</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PID0</name>
|
|
<description>PORT Event Pin Identifier 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT0</name>
|
|
<description>PORT Event Action 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACT0Select</name>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Event output to pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output register of pin on event</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLR</name>
|
|
<description>Clear output register of pin on event</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TGL</name>
|
|
<description>Toggle output register of pin on event</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI0</name>
|
|
<description>PORT Event Input Enable 0</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID1</name>
|
|
<description>PORT Event Pin Identifier 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT1</name>
|
|
<description>PORT Event Action 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI1</name>
|
|
<description>PORT Event Input Enable 1</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID2</name>
|
|
<description>PORT Event Pin Identifier 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT2</name>
|
|
<description>PORT Event Action 2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI2</name>
|
|
<description>PORT Event Input Enable 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PID3</name>
|
|
<description>PORT Event Pin Identifier 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVACT3</name>
|
|
<description>PORT Event Action 3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTEI3</name>
|
|
<description>PORT Event Input Enable 3</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>PMUX[%s]</name>
|
|
<description>Peripheral Multiplexing</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMUXE</name>
|
|
<description>Peripheral Multiplexing for Even-Numbered Pin</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUXO</name>
|
|
<description>Peripheral Multiplexing for Odd-Numbered Pin</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>PINCFG[%s]</name>
|
|
<description>Pin Configuration</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMUXEN</name>
|
|
<description>Peripheral Multiplexer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PULLEN</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRVSTR</name>
|
|
<description>Output Driver Strength Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>QSPI</name>
|
|
<version>U20081.6.3</version>
|
|
<description>Quad SPI interface</description>
|
|
<groupName>QSPI</groupName>
|
|
<prependToName>QSPI_</prependToName>
|
|
<baseAddress>0x42003400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>QSPI</name>
|
|
<value>134</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LASTXFER</name>
|
|
<description>Last Transfer</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Serial Memory Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>SPI operating mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMORY</name>
|
|
<description>Serial Memory operating mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPEN</name>
|
|
<description>Local Loopback Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDRBT</name>
|
|
<description>Wait Data Read Before Transfer</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMEMREG</name>
|
|
<description>Serial Memory reg</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSMODE</name>
|
|
<description>Chip Select Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CSMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>NORELOAD</name>
|
|
<description>The chip select is deasserted if TD has not been reloaded before the end of the current transfer.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LASTXFER</name>
|
|
<description>The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEMATICALLY</name>
|
|
<description>The chip select is deasserted systematically after each transfer.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATALEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATALENSelect</name>
|
|
<enumeratedValue>
|
|
<name>8BITS</name>
|
|
<description>8-bits transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9BITS</name>
|
|
<description>9 bits transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BITS</name>
|
|
<description>10-bits transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11BITS</name>
|
|
<description>11-bits transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12BITS</name>
|
|
<description>12-bits transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13BITS</name>
|
|
<description>13-bits transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14BITS</name>
|
|
<description>14-bits transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15BITS</name>
|
|
<description>15-bits transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BITS</name>
|
|
<description>16-bits transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYBCT</name>
|
|
<description>Delay Between Consecutive Transfers</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYCS</name>
|
|
<description>Minimum Inactive CS Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Serial Clock Baud Rate</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS</name>
|
|
<description>Delay Before SCK</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Receive Data</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Data Register Full Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Transmit Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmission Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Overrun Error Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSRISE</name>
|
|
<description>Chip Select Rise Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSTREND</name>
|
|
<description>Instruction End Interrupt Disable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Data Register Full Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Transmit Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmission Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Overrun Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSRISE</name>
|
|
<description>Chip Select Rise Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSTREND</name>
|
|
<description>Instruction End Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Data Register Full</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Transmit Data Register Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmission Complete</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Overrun Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSRISE</name>
|
|
<description>Chip Select Rise</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSTREND</name>
|
|
<description>Instruction End</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSSTATUS</name>
|
|
<description>Chip Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INSTRADDR</name>
|
|
<description>Instruction Address</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Instruction Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INSTRCTRL</name>
|
|
<description>Instruction Code</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INSTR</name>
|
|
<description>Instruction Code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTCODE</name>
|
|
<description>Option Code</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INSTRFRAME</name>
|
|
<description>Instruction Frame</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Instruction Code, Address, Option Code and Data Width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WIDTHSelect</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_BIT_SPI</name>
|
|
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUAL_OUTPUT</name>
|
|
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QUAD_OUTPUT</name>
|
|
<description>Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUAL_IO</name>
|
|
<description>Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QUAD_IO</name>
|
|
<description>Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUAL_CMD</name>
|
|
<description>Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QUAD_CMD</name>
|
|
<description>Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSTREN</name>
|
|
<description>Instruction Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDREN</name>
|
|
<description>Address Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTCODEEN</name>
|
|
<description>Option Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAEN</name>
|
|
<description>Data Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTCODELEN</name>
|
|
<description>Option Code Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>OPTCODELENSelect</name>
|
|
<enumeratedValue>
|
|
<name>1BIT</name>
|
|
<description>1-bit length option code</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2BITS</name>
|
|
<description>2-bits length option code</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BITS</name>
|
|
<description>4-bits length option code</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BITS</name>
|
|
<description>8-bits length option code</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRLEN</name>
|
|
<description>Address Length</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADDRLENSelect</name>
|
|
<enumeratedValue>
|
|
<name>24BITS</name>
|
|
<description>24-bits address length</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BITS</name>
|
|
<description>32-bits address length</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRTYPE</name>
|
|
<description>Data Transfer Type</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TFRTYPESelect</name>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READMEMORY</name>
|
|
<description>Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Write transfer into the serial memory.Scrambling is not performed.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITEMEMORY</name>
|
|
<description>Write data transfer into the serial memory.If enabled, scrambling is performed.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRMODE</name>
|
|
<description>Continuous Read Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDREN</name>
|
|
<description>Double Data Rate Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUMMYLEN</name>
|
|
<description>Dummy Cycles Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCRAMBCTRL</name>
|
|
<description>Scrambling Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Scrambling/Unscrambling Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RANDOMDIS</name>
|
|
<description>Scrambling/Unscrambling Random Value Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCRAMBKEY</name>
|
|
<description>Scrambling Key</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Scrambling User Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RAMECC</name>
|
|
<version>U22681.0.0</version>
|
|
<description>RAM ECC</description>
|
|
<groupName>RAMECC</groupName>
|
|
<prependToName>RAMECC_</prependToName>
|
|
<baseAddress>0x41020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RAMECC</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLEE</name>
|
|
<description>Single Bit ECC Error Interrupt Enable Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALE</name>
|
|
<description>Dual Bit ECC Error Interrupt Enable Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLEE</name>
|
|
<description>Single Bit ECC Error Interrupt Enable Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALE</name>
|
|
<description>Dual Bit ECC Error Interrupt Enable Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLEE</name>
|
|
<description>Single Bit ECC Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALE</name>
|
|
<description>Dual Bit ECC Error Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCDIS</name>
|
|
<description>ECC Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRADDR</name>
|
|
<description>Error Address</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERRADDR</name>
|
|
<description>Error Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCDIS</name>
|
|
<description>ECC Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCELOG</name>
|
|
<description>ECC Error Log</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RSTC</name>
|
|
<version>U22394.0.0</version>
|
|
<description>Reset Controller</description>
|
|
<groupName>RSTC</groupName>
|
|
<prependToName>RSTC_</prependToName>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RCAUSE</name>
|
|
<description>Reset Cause</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power On Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BODCORE</name>
|
|
<description>Brown Out CORE Detector Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BODVDD</name>
|
|
<description>Brown Out VDD Detector Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NVM</name>
|
|
<description>NVM Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Watchdog Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYST</name>
|
|
<description>System Reset Request</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BACKUP</name>
|
|
<description>Backup Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKUPEXIT</name>
|
|
<description>Backup Exit Source</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Real Timer Counter Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBPS</name>
|
|
<description>Battery Backup Power Switch</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HIB</name>
|
|
<description>Hibernate</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<version>U22502.1.0</version>
|
|
<description>Real-Time Counter</description>
|
|
<groupName>RTC</groupName>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x40002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>MODE0</name>
|
|
<description>32-bit Counter with Single 32-bit Compare</description>
|
|
<headerStructName>RtcMode0</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE0 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCHCLR</name>
|
|
<description>Clear on Match</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKTRST</name>
|
|
<description>BKUP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE0 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2EN</name>
|
|
<description>General Purpose 2 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Freqnuency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Freqnuency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE0 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO0</name>
|
|
<description>Compare 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO1</name>
|
|
<description>Compare 1 Event Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE0 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE0 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE0 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE0 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>COUNT Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>COMP 1 Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2</name>
|
|
<description>General Purpose 2 Register Busy</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP3</name>
|
|
<description>General Purpose 3 Register Busy</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>MODE0 Counter Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>COMP[%s]</name>
|
|
<description>MODE0 Compare n Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN4ACT</name>
|
|
<description>Tamper Input 4 Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN4ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN4 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL4</name>
|
|
<description>Tamper Level Select 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC4</name>
|
|
<description>Debouncer Enable 4</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE0 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID4</name>
|
|
<description>Tamper Input 4 Detected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>BKUP[%s]</name>
|
|
<description>Backup</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKUP</name>
|
|
<description>Backup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>MODE1</name>
|
|
<description>16-bit Counter with Two 16-bit Compares</description>
|
|
<alternateCluster>MODE0</alternateCluster>
|
|
<headerStructName>RtcMode1</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE1 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKTRST</name>
|
|
<description>BKUP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE1 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2EN</name>
|
|
<description>General Purpose 2 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Freqnuency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Freqnuency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE1 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO0</name>
|
|
<description>Compare 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO1</name>
|
|
<description>Compare 1 Event Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO2</name>
|
|
<description>Compare 2 Event Output Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPEO3</name>
|
|
<description>Compare 3 Event Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE1 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE1 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE1 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE1 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Bit Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>COUNT Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>COMP 1 Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>COMP 2 Register Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>COMP 3 Register Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTSYNC</name>
|
|
<description>Count Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2</name>
|
|
<description>General Purpose 2 Register Busy</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP3</name>
|
|
<description>General Purpose 3 Register Busy</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>MODE1 Counter Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>MODE1 Counter Period</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Counter Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>COMP[%s]</name>
|
|
<description>MODE1 Compare n Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN4ACT</name>
|
|
<description>Tamper Input 4 Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN4ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN4 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL4</name>
|
|
<description>Tamper Level Select 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC4</name>
|
|
<description>Debouncer Enable 4</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE1 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID4</name>
|
|
<description>Tamper Input 4 Detected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>BKUP[%s]</name>
|
|
<description>Backup</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKUP</name>
|
|
<description>Backup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>MODE2</name>
|
|
<description>Clock/Calendar with Alarm</description>
|
|
<alternateCluster>MODE0</alternateCluster>
|
|
<headerStructName>RtcMode2</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>MODE2 Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Mode 0: 32-bit Counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Mode 1: 16-bit Counter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK</name>
|
|
<description>Mode 2: Clock/Calendar</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKREP</name>
|
|
<description>Clock Representation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHCLR</name>
|
|
<description>Clear on Match</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/16</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/32</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/64</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/128</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/256</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/512</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>CLK_RTC_CNT = GCLK_RTC/1024</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKTRST</name>
|
|
<description>BKUP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>GP Registers Reset On Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCKSYNC</name>
|
|
<description>Clock Read Synchronization Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>MODE2 Control B</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP0EN</name>
|
|
<description>General Purpose 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2EN</name>
|
|
<description>General Purpose 2 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBMAJ</name>
|
|
<description>Debouncer Majority Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBASYNC</name>
|
|
<description>Debouncer Asynchronous Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCOUT</name>
|
|
<description>RTC Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBF</name>
|
|
<description>Debounce Freqnuency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DEBFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_DEB = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTF</name>
|
|
<description>Active Layer Freqnuency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTFSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>CLK_RTC_OUT = CLK_RTC/256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>MODE2 Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEREO0</name>
|
|
<description>Periodic Interval 0 Event Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO1</name>
|
|
<description>Periodic Interval 1 Event Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO2</name>
|
|
<description>Periodic Interval 2 Event Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO3</name>
|
|
<description>Periodic Interval 3 Event Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO4</name>
|
|
<description>Periodic Interval 4 Event Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO5</name>
|
|
<description>Periodic Interval 5 Event Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO6</name>
|
|
<description>Periodic Interval 6 Event Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEREO7</name>
|
|
<description>Periodic Interval 7 Event Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARMEO0</name>
|
|
<description>Alarm 0 Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARMEO1</name>
|
|
<description>Alarm 1 Event Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEREO</name>
|
|
<description>Tamper Event Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow Event Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVEI</name>
|
|
<description>Tamper Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>MODE2 Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM1</name>
|
|
<description>Alarm 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>MODE2 Interrupt Enable Set</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4 Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5 Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6 Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7 Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM1</name>
|
|
<description>Alarm 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>MODE2 Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER0</name>
|
|
<description>Periodic Interval 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER1</name>
|
|
<description>Periodic Interval 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER2</name>
|
|
<description>Periodic Interval 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER3</name>
|
|
<description>Periodic Interval 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER4</name>
|
|
<description>Periodic Interval 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER5</name>
|
|
<description>Periodic Interval 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER6</name>
|
|
<description>Periodic Interval 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER7</name>
|
|
<description>Periodic Interval 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>Alarm 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM1</name>
|
|
<description>Alarm 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPER</name>
|
|
<description>Tamper</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>MODE2 Synchronization Busy Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Bit Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Bit Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQCORR</name>
|
|
<description>FREQCORR Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCK</name>
|
|
<description>CLOCK Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>ALARM 0 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALARM1</name>
|
|
<description>ALARM 1 Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASK0</name>
|
|
<description>MASK 0 Register Busy</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASK1</name>
|
|
<description>MASK 1 Register Busy</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLOCKSYNC</name>
|
|
<description>Clock Synchronization Enable Bit Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP0</name>
|
|
<description>General Purpose 0 Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>General Purpose 1 Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP2</name>
|
|
<description>General Purpose 2 Register Busy</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GP3</name>
|
|
<description>General Purpose 3 Register Busy</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQCORR</name>
|
|
<description>Frequency Correction</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Correction Sign</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK</name>
|
|
<description>MODE2 Clock Value</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HOURSelect</name>
|
|
<enumeratedValue>
|
|
<name>AM</name>
|
|
<description>AM when CLKREP in 12-hour</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM</name>
|
|
<description>PM when CLKREP in 12-hour</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>GP[%s]</name>
|
|
<description>General Purpose</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General Purpose</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALARM0</name>
|
|
<description>MODE2_ALARM Alarm n Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HOURSelect</name>
|
|
<enumeratedValue>
|
|
<name>AM</name>
|
|
<description>Morning hour</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM</name>
|
|
<description>Afternoon hour</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK0</name>
|
|
<description>MODE2_ALARM Alarm n Mask</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Alarm Mask Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Alarm Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SS</name>
|
|
<description>Match seconds only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMSS</name>
|
|
<description>Match seconds and minutes only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HHMMSS</name>
|
|
<description>Match seconds, minutes, and hours only</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, and days only</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, and months only</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YYMMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, months, and years</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALARM1</name>
|
|
<description>MODE2_ALARM Alarm n Value</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HOURSelect</name>
|
|
<enumeratedValue>
|
|
<name>AM</name>
|
|
<description>Morning hour</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM</name>
|
|
<description>Afternoon hour</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK1</name>
|
|
<description>MODE2_ALARM Alarm n Mask</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Alarm Mask Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Alarm Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SS</name>
|
|
<description>Match seconds only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMSS</name>
|
|
<description>Match seconds and minutes only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HHMMSS</name>
|
|
<description>Match seconds, minutes, and hours only</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, and days only</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, and months only</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YYMMDDHHMMSS</name>
|
|
<description>Match seconds, minutes, hours, days, months, and years</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPCTRL</name>
|
|
<description>Tamper Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN0ACT</name>
|
|
<description>Tamper Input 0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN0ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN0 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1ACT</name>
|
|
<description>Tamper Input 1 Action</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN1ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN1 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2ACT</name>
|
|
<description>Tamper Input 2 Action</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN2ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN2 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3ACT</name>
|
|
<description>Tamper Input 3 Action</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN3ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN3 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN4ACT</name>
|
|
<description>Tamper Input 4 Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IN4ACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Off (Disabled)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE</name>
|
|
<description>Wake without timestamp</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture timestamp</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTL</name>
|
|
<description>Compare IN4 to OUT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL0</name>
|
|
<description>Tamper Level Select 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL1</name>
|
|
<description>Tamper Level Select 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL2</name>
|
|
<description>Tamper Level Select 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL3</name>
|
|
<description>Tamper Level Select 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMLVL4</name>
|
|
<description>Tamper Level Select 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC0</name>
|
|
<description>Debouncer Enable 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC1</name>
|
|
<description>Debouncer Enable 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC2</name>
|
|
<description>Debouncer Enable 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC3</name>
|
|
<description>Debouncer Enable 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBNC4</name>
|
|
<description>Debouncer Enable 4</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>MODE2 Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECOND</name>
|
|
<description>Second Timestamp Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINUTE</name>
|
|
<description>Minute Timestamp Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hour Timestamp Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HOURSelect</name>
|
|
<enumeratedValue>
|
|
<name>AM</name>
|
|
<description>AM when CLKREP in 12-hour</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM</name>
|
|
<description>PM when CLKREP in 12-hour</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>Day Timestamp Value</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month Timestamp Value</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year Timestamp Value</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMPID</name>
|
|
<description>Tamper ID</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPID0</name>
|
|
<description>Tamper Input 0 Detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID1</name>
|
|
<description>Tamper Input 1 Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID2</name>
|
|
<description>Tamper Input 2 Detected</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID3</name>
|
|
<description>Tamper Input 3 Detected</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPID4</name>
|
|
<description>Tamper Input 4 Detected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPEVT</name>
|
|
<description>Tamper Event Detected</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>BKUP[%s]</name>
|
|
<description>Backup</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKUP</name>
|
|
<description>Backup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SDHC0</name>
|
|
<version>U20111.8.3</version>
|
|
<description>SD/MMC Host Controller</description>
|
|
<groupName>SDHC</groupName>
|
|
<prependToName>SDHC_</prependToName>
|
|
<baseAddress>0x45000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x235</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SDHC0</name>
|
|
<value>135</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SSAR</name>
|
|
<description>SDMA System Address / Argument 2</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>SDMA System Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSAR_CMD23_MODE</name>
|
|
<description>SDMA System Address / Argument 2</description>
|
|
<alternateRegister>SSAR</alternateRegister>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARG2</name>
|
|
<description>Argument 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSR</name>
|
|
<description>Block Size</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLOCKSIZE</name>
|
|
<description>Transfer Block Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOUNDARY</name>
|
|
<description>SDMA Buffer Boundary</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BOUNDARYSelect</name>
|
|
<enumeratedValue>
|
|
<name>4K</name>
|
|
<description>4k bytes</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8K</name>
|
|
<description>8k bytes</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16K</name>
|
|
<description>16k bytes</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32K</name>
|
|
<description>32k bytes</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64K</name>
|
|
<description>64k bytes</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128K</name>
|
|
<description>128k bytes</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256K</name>
|
|
<description>256k bytes</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512K</name>
|
|
<description>512k bytes</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR</name>
|
|
<description>Block Count</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT</name>
|
|
<description>Blocks Count for Current Transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARG1R</name>
|
|
<description>Argument 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARG</name>
|
|
<description>Argument 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR</name>
|
|
<description>Transfer Mode</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No data transfer or Non DMA data transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>DMA data transfer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCEN</name>
|
|
<description>Block Count Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BCENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDEN</name>
|
|
<description>Auto Command Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Auto Command Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD12</name>
|
|
<description>Auto CMD12 Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD23</name>
|
|
<description>Auto CMD23 Enable</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTDSEL</name>
|
|
<description>Data Transfer Direction Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DTDSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Write (Host to Card)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read (Card to Host)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBSEL</name>
|
|
<description>Multi/Single Block Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MSBSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single Block</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIPLE</name>
|
|
<description>Multiple Block</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Command</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESPTYP</name>
|
|
<description>Response Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RESPTYPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No response</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>136_BIT</name>
|
|
<description>136-bit response</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>48_BIT</name>
|
|
<description>48-bit response</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>48_BIT_BUSY</name>
|
|
<description>48-bit response check busy after response</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCCEN</name>
|
|
<description>Command CRC Check Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCCENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDICEN</name>
|
|
<description>Command Index Check Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDICENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPSEL</name>
|
|
<description>Data Present Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DPSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO_DATA</name>
|
|
<description>No Data Present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data Present</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDTYP</name>
|
|
<description>Command Type</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTYPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Other commands</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>CMD52 for writing Bus Suspend in CCCR</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME</name>
|
|
<description>CMD52 for writing Function Select in CCCR</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ABORT</name>
|
|
<description>CMD12, CMD52 for writing I/O Abort in CCCR</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>RR[%s]</name>
|
|
<description>Response</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDRESP</name>
|
|
<description>Command Response</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDPR</name>
|
|
<description>Buffer Data Port</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUFDATA</name>
|
|
<description>Buffer Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>Present State</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00F80000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDINHC</name>
|
|
<description>Command Inhibit (CMD)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDINHCSelect</name>
|
|
<enumeratedValue>
|
|
<name>CAN</name>
|
|
<description>Can issue command using only CMD line</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CANNOT</name>
|
|
<description>Cannot issue command</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDINHD</name>
|
|
<description>Command Inhibit (DAT)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDINHDSelect</name>
|
|
<enumeratedValue>
|
|
<name>CAN</name>
|
|
<description>Can issue command which uses the DAT line</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CANNOT</name>
|
|
<description>Cannot issue command which uses the DAT line</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLACT</name>
|
|
<description>DAT Line Active</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DLACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>DAT Line Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>DAT Line Active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTREQ</name>
|
|
<description>Re-Tuning Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RTREQSelect</name>
|
|
<enumeratedValue>
|
|
<name>OK</name>
|
|
<description>Fixed or well-tuned sampling clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REQUIRED</name>
|
|
<description>Sampling clock needs re-tuning</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTACT</name>
|
|
<description>Write Transfer Active</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WTACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No valid data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Transferring data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTACT</name>
|
|
<description>Read Transfer Active</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RTACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No valid data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Transferring data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFWREN</name>
|
|
<description>Buffer Write Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BUFWRENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Write disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Write enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFRDEN</name>
|
|
<description>Buffer Read Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BUFRDENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Read disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Read enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CARDINS</name>
|
|
<description>Card Inserted</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CARDINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Reset or Debouncing or No Card</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Card inserted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CARDSS</name>
|
|
<description>Card State Stable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CARDSSSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Reset or Debouncing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>No Card or Insered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CARDDPL</name>
|
|
<description>Card Detect Pin Level</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CARDDPLSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No card present (SDCD#=1)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Card present (SDCD#=0)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRPPL</name>
|
|
<description>Write Protect Pin Level</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WRPPLSelect</name>
|
|
<enumeratedValue>
|
|
<name>PROTECTED</name>
|
|
<description>Write protected (SDWP#=0)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Write enabled (SDWP#=1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATLL</name>
|
|
<description>DAT[3:0] Line Level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDLL</name>
|
|
<description>CMD Line Level</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1R</name>
|
|
<description>Host Control 1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xE00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEDCTRL</name>
|
|
<description>LED Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LEDCTRLSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>LED off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>LED on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DW</name>
|
|
<description>Data Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DWSelect</name>
|
|
<enumeratedValue>
|
|
<name>1BIT</name>
|
|
<description>1-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BIT</name>
|
|
<description>4-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSEN</name>
|
|
<description>High Speed Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HSENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal Speed mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High Speed mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMASELSelect</name>
|
|
<enumeratedValue>
|
|
<name>SDMA</name>
|
|
<description>SDMA is selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT</name>
|
|
<description>32-bit Address ADMA2 is selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CARDDTL</name>
|
|
<description>Card Detect Test Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CARDDTLSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Card</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Card Inserted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CARDDSEL</name>
|
|
<description>Card Detect Signal Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CARDDSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>SDCD# is selected (for normal use)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEST</name>
|
|
<description>The Card Select Test Level is selected (for test purpose)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1R_EMMC_MODE</name>
|
|
<description>Host Control 1</description>
|
|
<alternateRegister>HC1R</alternateRegister>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xE00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DW</name>
|
|
<description>Data Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DWSelect</name>
|
|
<enumeratedValue>
|
|
<name>1BIT</name>
|
|
<description>1-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BIT</name>
|
|
<description>4-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSEN</name>
|
|
<description>High Speed Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HSENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal Speed mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High Speed mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMASELSelect</name>
|
|
<enumeratedValue>
|
|
<name>SDMA</name>
|
|
<description>SDMA is selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BIT</name>
|
|
<description>32-bit Address ADMA2 is selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR</name>
|
|
<description>Power Control</description>
|
|
<addressOffset>0x29</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0E</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDBPWR</name>
|
|
<description>SD Bus Power</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDBPWRSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Power off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>Power on</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDBVSEL</name>
|
|
<description>SD Bus Voltage Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDBVSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>1V8</name>
|
|
<description>1.8V (Typ.)</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3V0</name>
|
|
<description>3.0V (Typ.)</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3V3</name>
|
|
<description>3.3V (Typ.)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGCR</name>
|
|
<description>Block Gap Control</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPBGR</name>
|
|
<description>Stop at Block Gap Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STPBGRSelect</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONTR</name>
|
|
<description>Continue Request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CONTRSelect</name>
|
|
<enumeratedValue>
|
|
<name>GO_ON</name>
|
|
<description>Not affected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART</name>
|
|
<description>Restart</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWCTRL</name>
|
|
<description>Read Wait Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RWCTRLSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable Read Wait Control</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable Read Wait Control</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTBG</name>
|
|
<description>Interrupt at Block Gap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INTBGSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGCR_EMMC_MODE</name>
|
|
<description>Block Gap Control</description>
|
|
<alternateRegister>BGCR</alternateRegister>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPBGR</name>
|
|
<description>Stop at Block Gap Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STPBGRSelect</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONTR</name>
|
|
<description>Continue Request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CONTRSelect</name>
|
|
<enumeratedValue>
|
|
<name>GO_ON</name>
|
|
<description>Not affected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART</name>
|
|
<description>Restart</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WCR</name>
|
|
<description>Wakeup Control</description>
|
|
<addressOffset>0x2B</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WKENCINT</name>
|
|
<description>Wakeup Event Enable on Card Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WKENCINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKENCINS</name>
|
|
<description>Wakeup Event Enable on Card Insertion</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WKENCINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKENCREM</name>
|
|
<description>Wakeup Event Enable on Card Removal</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WKENCREMSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Control</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTCLKEN</name>
|
|
<description>Internal Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INTCLKENSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Stop</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>Oscillate</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTCLKS</name>
|
|
<description>Internal Clock Stable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INTCLKSSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOT_READY</name>
|
|
<description>Not Ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READY</name>
|
|
<description>Ready</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCLKEN</name>
|
|
<description>SD Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDCLKENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGSEL</name>
|
|
<description>Clock Generator Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKGSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Divided Clock Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROG</name>
|
|
<description>Programmable Clock Mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USDCLKFSEL</name>
|
|
<description>Upper Bits of SDCLK Frequency Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDCLKFSEL</name>
|
|
<description>SDCLK Frequency Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timeout Control</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTCVAL</name>
|
|
<description>Data Timeout Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRR</name>
|
|
<description>Software Reset</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRSTALL</name>
|
|
<description>Software Reset For All</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SWRSTALLSelect</name>
|
|
<enumeratedValue>
|
|
<name>WORK</name>
|
|
<description>Work</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCMD</name>
|
|
<description>Software Reset For CMD Line</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SWRSTCMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>WORK</name>
|
|
<description>Work</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTDAT</name>
|
|
<description>Software Reset For DAT Line</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SWRSTDATSelect</name>
|
|
<enumeratedValue>
|
|
<name>WORK</name>
|
|
<description>Work</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISTR</name>
|
|
<description>Normal Interrupt Status</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No command complete</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Command complete</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not complete</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Command execution is completed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Block Gap Event</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Transaction stopped at block gap</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No DMA Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>DMA Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not ready to write buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Ready to write buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not ready to read buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Ready to read buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINS</name>
|
|
<description>Card Insertion</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Card state stable or Debouncing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Card inserted</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CREM</name>
|
|
<description>Card Removal</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CREMSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Card state stable or Debouncing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Card Removed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Card Interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Card Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Generate Card Interrupt</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRINT</name>
|
|
<description>Error Interrupt</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ERRINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISTR_EMMC_MODE</name>
|
|
<description>Normal Interrupt Status</description>
|
|
<alternateRegister>NISTR</alternateRegister>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No command complete</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Command complete</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not complete</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Command execution is completed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Block Gap Event</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Transaction stopped at block gap</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No DMA Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>DMA Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not ready to write buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Ready to write buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not ready to read buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Ready to read buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAR</name>
|
|
<description>Boot Acknowledge Received</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRINT</name>
|
|
<description>Error Interrupt</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ERRINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISTR</name>
|
|
<description>Error Interrupt Status</description>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Timeout</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>CRC Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>End Bit Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Timeout</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Power Fail</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISTR_EMMC_MODE</name>
|
|
<description>Error Interrupt Status</description>
|
|
<alternateRegister>EISTR</alternateRegister>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Timeout</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>CRC Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>End Bit Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Timeout</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Power Fail</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAE</name>
|
|
<description>Boot Acknowledge Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BOOTAESelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO contains at least one byte</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO is empty</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISTER</name>
|
|
<description>Normal Interrupt Status Enable</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINS</name>
|
|
<description>Card Insertion Status Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CREM</name>
|
|
<description>Card Removal Status Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CREMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Card Interrupt Status Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISTER_EMMC_MODE</name>
|
|
<description>Normal Interrupt Status Enable</description>
|
|
<alternateRegister>NISTER</alternateRegister>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAR</name>
|
|
<description>Boot Acknowledge Received Status Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISTER</name>
|
|
<description>Error Interrupt Status Enable</description>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error Status Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error Status Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error Status Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error Status Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISTER_EMMC_MODE</name>
|
|
<description>Error Interrupt Status Enable</description>
|
|
<alternateRegister>EISTER</alternateRegister>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error Status Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error Status Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error Status Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error Status Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAE</name>
|
|
<description>Boot Acknowledge Error Status Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISIER</name>
|
|
<description>Normal Interrupt Signal Enable</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete Signal Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete Signal Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event Signal Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt Signal Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready Signal Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready Signal Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINS</name>
|
|
<description>Card Insertion Signal Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINSSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CREM</name>
|
|
<description>Card Removal Signal Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CREMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Card Interrupt Signal Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NISIER_EMMC_MODE</name>
|
|
<description>Normal Interrupt Signal Enable</description>
|
|
<alternateRegister>NISIER</alternateRegister>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDC</name>
|
|
<description>Command Complete Signal Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Transfer Complete Signal Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TRFCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLKGE</name>
|
|
<description>Block Gap Event Signal Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLKGESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>DMA Interrupt Signal Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DMAINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWRRDY</name>
|
|
<description>Buffer Write Ready Signal Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BWRRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDRDY</name>
|
|
<description>Buffer Read Ready Signal Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BRDRDYSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAR</name>
|
|
<description>Boot Acknowledge Received Signal Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISIER</name>
|
|
<description>Error Interrupt Signal Enable</description>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error Signal Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error Signal Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error Signal Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error Signal Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error Signal Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error Signal Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error Signal Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error Signal Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error Signal Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error Signal Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISIER_EMMC_MODE</name>
|
|
<description>Error Interrupt Signal Enable</description>
|
|
<alternateRegister>EISIER</alternateRegister>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Command Timeout Error Signal Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Command CRC Error Signal Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Command End Bit Error Signal Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command Index Error Signal Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Data Timeout Error Signal Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Data CRC Error Signal Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Data End Bit Error Signal Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Current Limit Error Signal Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Auto CMD Error Signal Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>ADMA Error Signal Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>MASKED</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAE</name>
|
|
<description>Boot Acknowledge Error Signal Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACESR</name>
|
|
<description>Auto CMD Error Status</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACMD12NE</name>
|
|
<description>Auto CMD12 Not Executed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMD12NESelect</name>
|
|
<enumeratedValue>
|
|
<name>EXEC</name>
|
|
<description>Executed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_EXEC</name>
|
|
<description>Not executed</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDTEO</name>
|
|
<description>Auto CMD Timeout Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Timeout</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDCRC</name>
|
|
<description>Auto CMD CRC Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>CRC Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDEND</name>
|
|
<description>Auto CMD End Bit Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>End Bit Error Generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDIDX</name>
|
|
<description>Auto CMD Index Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDNI</name>
|
|
<description>Command not Issued By Auto CMD12 Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDNISelect</name>
|
|
<enumeratedValue>
|
|
<name>OK</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_ISSUED</name>
|
|
<description>Not Issued</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2R</name>
|
|
<description>Host Control 2</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UHSMS</name>
|
|
<description>UHS Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>UHSMSSelect</name>
|
|
<enumeratedValue>
|
|
<name>SDR12</name>
|
|
<description>SDR12</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR25</name>
|
|
<description>SDR25</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR50</name>
|
|
<description>SDR50</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR104</name>
|
|
<description>SDR104</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DDR50</name>
|
|
<description>DDR50</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VS18EN</name>
|
|
<description>1.8V Signaling Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>VS18ENSelect</name>
|
|
<enumeratedValue>
|
|
<name>S33V</name>
|
|
<description>3.3V Signaling</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>S18V</name>
|
|
<description>1.8V Signaling</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVSEL</name>
|
|
<description>Driver Strength Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>B</name>
|
|
<description>Driver Type B is Selected (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A</name>
|
|
<description>Driver Type A is Selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C</name>
|
|
<description>Driver Type C is Selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>D</name>
|
|
<description>Driver Type D is Selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTUN</name>
|
|
<description>Execute Tuning</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EXTUNSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not Tuned or Tuning Completed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REQUESTED</name>
|
|
<description>Execute Tuning</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLCKSEL</name>
|
|
<description>Sampling Clock Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLCKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>FIXED</name>
|
|
<description>Fixed clock is used to sample data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TUNED</name>
|
|
<description>Tuned clock is used to sample data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASINTEN</name>
|
|
<description>Asynchronous Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ASINTENSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PVALEN</name>
|
|
<description>Preset Value Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PVALENSelect</name>
|
|
<enumeratedValue>
|
|
<name>HOST</name>
|
|
<description>SDCLK and Driver Strength are controlled by Host Controller</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO</name>
|
|
<description>Automatic Selection by Preset Value is Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2R_EMMC_MODE</name>
|
|
<description>Host Control 2</description>
|
|
<alternateRegister>HC2R</alternateRegister>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HS200EN</name>
|
|
<description>HS200 Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HS200ENSelect</name>
|
|
<enumeratedValue>
|
|
<name>SDR12</name>
|
|
<description>SDR12</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR25</name>
|
|
<description>SDR25</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR50</name>
|
|
<description>SDR50</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDR104</name>
|
|
<description>SDR104</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DDR50</name>
|
|
<description>DDR50</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVSEL</name>
|
|
<description>Driver Strength Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>B</name>
|
|
<description>Driver Type B is Selected (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A</name>
|
|
<description>Driver Type A is Selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C</name>
|
|
<description>Driver Type C is Selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>D</name>
|
|
<description>Driver Type D is Selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTUN</name>
|
|
<description>Execute Tuning</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EXTUNSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Not Tuned or Tuning Completed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REQUESTED</name>
|
|
<description>Execute Tuning</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLCKSEL</name>
|
|
<description>Sampling Clock Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLCKSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>FIXED</name>
|
|
<description>Fixed clock is used to sample data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TUNED</name>
|
|
<description>Tuned clock is used to sample data</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PVALEN</name>
|
|
<description>Preset Value Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PVALENSelect</name>
|
|
<enumeratedValue>
|
|
<name>HOST</name>
|
|
<description>SDCLK and Driver Strength are controlled by Host Controller</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO</name>
|
|
<description>Automatic Selection by Preset Value is Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CA0R</name>
|
|
<description>Capabilities 0</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x27E80080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEOCLKF</name>
|
|
<description>Timeout Clock Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TEOCLKFSelect</name>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information via another method</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEOCLKU</name>
|
|
<description>Timeout Clock Unit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TEOCLKUSelect</name>
|
|
<enumeratedValue>
|
|
<name>KHZ</name>
|
|
<description>KHz</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MHZ</name>
|
|
<description>MHz</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BASECLKF</name>
|
|
<description>Base Clock Frequency</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BASECLKFSelect</name>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information via another method</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAXBLKL</name>
|
|
<description>Max Block Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MAXBLKLSelect</name>
|
|
<enumeratedValue>
|
|
<name>512</name>
|
|
<description>512 bytes</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024</name>
|
|
<description>1024 bytes</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2048</name>
|
|
<description>2048 bytes</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ED8SUP</name>
|
|
<description>8-bit Support for Embedded Device</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ED8SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>8-bit Bus Width not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>8-bit Bus Width Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA2SUP</name>
|
|
<description>ADMA2 Support</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMA2SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>ADMA2 not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>ADMA2 Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSSUP</name>
|
|
<description>High Speed Support</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HSSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>High Speed not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>High Speed Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDMASUP</name>
|
|
<description>SDMA Support</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDMASUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>SDMA not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>SDMA Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRSUP</name>
|
|
<description>Suspend/Resume Support</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SRSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Suspend/Resume not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Suspend/Resume Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>V33VSUP</name>
|
|
<description>Voltage Support 3.3V</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>V33VSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>3.3V Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>3.3V Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>V30VSUP</name>
|
|
<description>Voltage Support 3.0V</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>V30VSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>3.0V Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>3.0V Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>V18VSUP</name>
|
|
<description>Voltage Support 1.8V</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>V18VSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>1.8V Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>1.8V Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SB64SUP</name>
|
|
<description>64-Bit System Bus Support</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SB64SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>32-bit Address Descriptors and System Bus</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>64-bit Address Descriptors and System Bus</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASINTSUP</name>
|
|
<description>Asynchronous Interrupt Support</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ASINTSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Asynchronous Interrupt not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Asynchronous Interrupt supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLTYPE</name>
|
|
<description>Slot Type</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLTYPESelect</name>
|
|
<enumeratedValue>
|
|
<name>REMOVABLE</name>
|
|
<description>Removable Card Slot</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMBEDDED</name>
|
|
<description>Embedded Slot for One Device</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CA1R</name>
|
|
<description>Capabilities 1</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000070</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDR50SUP</name>
|
|
<description>SDR50 Support</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDR50SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>SDR50 is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>SDR50 is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDR104SUP</name>
|
|
<description>SDR104 Support</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDR104SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>SDR104 is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>SDR104 is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDR50SUP</name>
|
|
<description>DDR50 Support</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DDR50SUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>DDR50 is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>DDR50 is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVASUP</name>
|
|
<description>Driver Type A Support</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVASUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Driver Type A is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Driver Type A is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVCSUP</name>
|
|
<description>Driver Type C Support</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVCSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Driver Type C is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Driver Type C is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVDSUP</name>
|
|
<description>Driver Type D Support</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVDSUPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Driver Type D is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Driver Type D is Supported</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCNTRT</name>
|
|
<description>Timer Count for Re-Tuning</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TCNTRTSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Re-Tuning Timer disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1S</name>
|
|
<description>1 second</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2S</name>
|
|
<description>2 seconds</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4S</name>
|
|
<description>4 seconds</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8S</name>
|
|
<description>8 seconds</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16S</name>
|
|
<description>16 seconds</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32S</name>
|
|
<description>32 seconds</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64S</name>
|
|
<description>64 seconds</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128S</name>
|
|
<description>128 seconds</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256S</name>
|
|
<description>256 seconds</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512S</name>
|
|
<description>512 seconds</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024S</name>
|
|
<description>1024 seconds</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information from other source</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSDR50</name>
|
|
<description>Use Tuning for SDR50</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TSDR50Select</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>SDR50 does not require tuning</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>SDR50 requires tuning</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKMULT</name>
|
|
<description>Clock Multiplier</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKMULTSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>Clock Multiplier is Not Supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCAR</name>
|
|
<description>Maximum Current Capabilities</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAXCUR33V</name>
|
|
<description>Maximum Current for 3.3V</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MAXCUR33VSelect</name>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information via another method</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4MA</name>
|
|
<description>4mA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8MA</name>
|
|
<description>8mA</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12MA</name>
|
|
<description>12mA</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAXCUR30V</name>
|
|
<description>Maximum Current for 3.0V</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MAXCUR30VSelect</name>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information via another method</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4MA</name>
|
|
<description>4mA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8MA</name>
|
|
<description>8mA</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12MA</name>
|
|
<description>12mA</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAXCUR18V</name>
|
|
<description>Maximum Current for 1.8V</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MAXCUR18VSelect</name>
|
|
<enumeratedValue>
|
|
<name>OTHER</name>
|
|
<description>Get information via another method</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4MA</name>
|
|
<description>4mA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8MA</name>
|
|
<description>8mA</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12MA</name>
|
|
<description>12mA</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FERACES</name>
|
|
<description>Force Event for Auto CMD Error Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACMD12NE</name>
|
|
<description>Force Event for Auto CMD12 Not Executed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMD12NESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDTEO</name>
|
|
<description>Force Event for Auto CMD Timeout Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDCRC</name>
|
|
<description>Force Event for Auto CMD CRC Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDEND</name>
|
|
<description>Force Event for Auto CMD End Bit Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMDIDX</name>
|
|
<description>Force Event for Auto CMD Index Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDNI</name>
|
|
<description>Force Event for Command Not Issued By Auto CMD12 Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDNISelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEREIS</name>
|
|
<description>Force Event for Error Interrupt Status</description>
|
|
<addressOffset>0x52</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTEO</name>
|
|
<description>Force Event for Command Timeout Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDCRC</name>
|
|
<description>Force Event for Command CRC Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEND</name>
|
|
<description>Force Event for Command End Bit Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Force Event for Command Index Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDIDXSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATTEO</name>
|
|
<description>Force Event for Data Timeout Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATTEOSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATCRC</name>
|
|
<description>Force Event for Data CRC Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATCRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATEND</name>
|
|
<description>Force Event for Data End Bit Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURLIM</name>
|
|
<description>Force Event for Current Limit Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CURLIMSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Force Event for Auto CMD Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMA</name>
|
|
<description>Force Event for ADMA Error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ADMASelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTAE</name>
|
|
<description>Force Event for Boot Acknowledge Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BOOTAESelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Interrupt is generated</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AESR</name>
|
|
<description>ADMA Error Status</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERRST</name>
|
|
<description>ADMA Error State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ERRSTSelect</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>ST_STOP (Stop DMA)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FDS</name>
|
|
<description>ST_FDS (Fetch Descriptor)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TFR</name>
|
|
<description>ST_TFR (Transfer Data)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMIS</name>
|
|
<description>ADMA Length Mismatch Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LMISSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No Error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>YES</name>
|
|
<description>Error</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ASAR[%s]</name>
|
|
<description>ADMA System Address n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADMASA</name>
|
|
<description>ADMA System Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>PVR[%s]</name>
|
|
<description>Preset Value n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDCLKFSEL</name>
|
|
<description>SDCLK Frequency Select Value for Initialization</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKGSEL</name>
|
|
<description>Clock Generator Select Value for Initialization</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKGSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV</name>
|
|
<description>Host Controller Ver2.00 Compatible Clock Generator (Divider)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROG</name>
|
|
<description>Programmable Clock Generator</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRVSEL</name>
|
|
<description>Driver Strength Select Value for Initialization</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DRVSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>B</name>
|
|
<description>Driver Type B is Selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A</name>
|
|
<description>Driver Type A is Selected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C</name>
|
|
<description>Driver Type C is Selected</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>D</name>
|
|
<description>Driver Type D is Selected</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SISR</name>
|
|
<description>Slot Interrupt Status</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x20000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTSSL</name>
|
|
<description>Interrupt Signal for Each Slot</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCVR</name>
|
|
<description>Host Controller Version</description>
|
|
<addressOffset>0xFE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1802</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SVER</name>
|
|
<description>Spec Version</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VVER</name>
|
|
<description>Vendor Version</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MC1R</name>
|
|
<description>MMC Control 1</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDTYP</name>
|
|
<description>e.MMC Command Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDTYPSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Not a MMC specific command</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITIRQ</name>
|
|
<description>Wait IRQ Command</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STREAM</name>
|
|
<description>Stream Command</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOOT</name>
|
|
<description>Boot Command</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDR</name>
|
|
<description>e.MMC HSDDR Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPD</name>
|
|
<description>e.MMC Open Drain Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOOTA</name>
|
|
<description>e.MMC Boot Acknowledge Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTN</name>
|
|
<description>e.MMC Reset Signal</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCD</name>
|
|
<description>e.MMC Force Card Detect</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MC2R</name>
|
|
<description>MMC Control 2</description>
|
|
<addressOffset>0x205</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRESP</name>
|
|
<description>e.MMC Abort Wait IRQ</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABOOT</name>
|
|
<description>e.MMC Abort Boot</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>AHB Control</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMAX</name>
|
|
<description>AHB Maximum Burst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BMAXSelect</name>
|
|
<enumeratedValue>
|
|
<name>INCR16</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR8</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR4</name>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2R</name>
|
|
<description>Clock Control 2</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSDCLKD</name>
|
|
<description>Force SDCK Disabled</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSDCLKDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACR</name>
|
|
<description>Capabilities Control</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CAPWREN</name>
|
|
<description>Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key (0x46)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGR</name>
|
|
<description>Debug</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NIDBG</name>
|
|
<description>Non-intrusive debug enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NIDBGSelect</name>
|
|
<enumeratedValue>
|
|
<name>IDBG</name>
|
|
<description>Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NIDBG</name>
|
|
<description>Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SDHC0">
|
|
<name>SDHC1</name>
|
|
<baseAddress>0x46000000</baseAddress>
|
|
<interrupt>
|
|
<name>SDHC1</name>
|
|
<value>136</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SERCOM0</name>
|
|
<version>U22015.0.0</version>
|
|
<description>Serial Communication Interface</description>
|
|
<groupName>SERCOM</groupName>
|
|
<prependToName>SERCOM_</prependToName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x31</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SERCOM0_0</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_1</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_2</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM0_OTHER</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>I2CM</name>
|
|
<description>I2C Master Mode</description>
|
|
<headerStructName>SercomI2cm</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>I2CM Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINOUT</name>
|
|
<description>Pin Usage</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDAHOLD</name>
|
|
<description>SDA Hold Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDAHOLDSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>75NS</name>
|
|
<description>50-100ns hold time</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>450NS</name>
|
|
<description>300-600ns hold time</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>600NS</name>
|
|
<description>400-800ns hold time</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEXTTOEN</name>
|
|
<description>Master SCL Low Extend Timeout</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOEN</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Transfer Speed</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPEEDSelect</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_AND_FAST_MODE</name>
|
|
<description>Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz </description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FASTPLUS_MODE</name>
|
|
<description>Fast-mode Plus Upto 1MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED_MODE</name>
|
|
<description>High-speed mode Upto 3.4MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLSM</name>
|
|
<description>SCL Clock Stretch Mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INACTOUT</name>
|
|
<description>Inactive Time-Out</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>INACTOUTSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>55US</name>
|
|
<description>5-6 SCL Time-Out(50-60us)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>105US</name>
|
|
<description>10-11 SCL Time-Out(100-110us)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>205US</name>
|
|
<description>20-21 SCL Time-Out(200-210us)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUTEN</name>
|
|
<description>SCL Low Timeout Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>I2CM Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEN</name>
|
|
<description>Smart Mode Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QCEN</name>
|
|
<description>Quick Command Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKACT</name>
|
|
<description>Acknowledge Action</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>I2CM Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_8BIT</name>
|
|
<description>Data transaction from/to DATA register are 8-bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_32BIT</name>
|
|
<description>Data transaction from/to DATA register are 32-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>I2CM Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BAUDLOW</name>
|
|
<description>Baud Rate Value Low</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSBAUD</name>
|
|
<description>High Speed Baud Rate Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSBAUDLOW</name>
|
|
<description>High Speed Baud Rate Value Low</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>I2CM Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>I2CM Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>I2CM Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Master On Bus Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Slave On Bus Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>I2CM Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNACK</name>
|
|
<description>Received Not Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSSTATE</name>
|
|
<description>Bus State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUT</name>
|
|
<description>SCL Low Timeout</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEXTTOUT</name>
|
|
<description>Master SCL Low Extend Timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOUT</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENERR</name>
|
|
<description>Length Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>I2CM Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSOP</name>
|
|
<description>System Operation Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>Length Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>I2CM Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Length Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>High Speed Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TENBITEN</name>
|
|
<description>Ten Bit Addressing Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Length</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>I2CM Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>I2CM Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>I2CS</name>
|
|
<description>I2C Slave Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomI2cs</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>I2CS Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINOUT</name>
|
|
<description>Pin Usage</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDAHOLD</name>
|
|
<description>SDA Hold Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SDAHOLDSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>75NS</name>
|
|
<description>50-100ns hold time</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>450NS</name>
|
|
<description>300-600ns hold time</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>600NS</name>
|
|
<description>400-800ns hold time</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOEN</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Transfer Speed</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPEEDSelect</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_AND_FAST_MODE</name>
|
|
<description>Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz </description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FASTPLUS_MODE</name>
|
|
<description>Fast-mode Plus Upto 1MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED_MODE</name>
|
|
<description>High-speed mode Upto 3.4MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLSM</name>
|
|
<description>SCL Clock Stretch Mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUTEN</name>
|
|
<description>SCL Low Timeout Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>I2CS Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMEN</name>
|
|
<description>Smart Mode Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCMD</name>
|
|
<description>PMBus Group Command</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AACKEN</name>
|
|
<description>Automatic Address Acknowledge</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMODE</name>
|
|
<description>Address Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKACT</name>
|
|
<description>Acknowledge Action</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>I2CS Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDASETUP</name>
|
|
<description>SDA Setup Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_8BIT</name>
|
|
<description>Data transaction from/to DATA register are 8-bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_32BIT</name>
|
|
<description>Data transaction from/to DATA register are 32-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>I2CS Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>I2CS Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>I2CS Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREC</name>
|
|
<description>Stop Received Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMATCH</name>
|
|
<description>Address Match Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>I2CS Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLL</name>
|
|
<description>Transmit Collision</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNACK</name>
|
|
<description>Received Not Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Read/Write Direction</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Repeated Start</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOWTOUT</name>
|
|
<description>SCL Low Timeout</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEXTTOUT</name>
|
|
<description>Slave SCL Low Extend Timeout</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>High Speed</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENERR</name>
|
|
<description>Transaction Length Error</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>I2CS Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>Length Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>I2CS Length</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Data Length Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>I2CS Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GENCEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TENBITEN</name>
|
|
<description>Ten Bit Addressing Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRMASK</name>
|
|
<description>Address Mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>I2CS Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>SPIS</name>
|
|
<description>SPI Slave Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomSpis</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>SPIS Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOPO</name>
|
|
<description>Data Out Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DOPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>DO on PAD[0], SCK on PAD[1] and SS on PAD[2]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>DO on PAD[3], SCK on PAD[1] and SS on PAD[2]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIPO</name>
|
|
<description>Data In Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used as data input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD1</name>
|
|
<description>SERCOM PAD[1] is used as data input</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>SERCOM PAD[2] is used as data input</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM PAD[3] is used as data input</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FORMSelect</name>
|
|
<enumeratedValue>
|
|
<name>SPI_FRAME</name>
|
|
<description>SPI Frame</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_FRAME_WITH_ADDR</name>
|
|
<description>SPI Frame with Addr</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPHASelect</name>
|
|
<enumeratedValue>
|
|
<name>LEADING_EDGE</name>
|
|
<description>The data is sampled on a leading SCK edge and changed on a trailing SCK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRAILING_EDGE</name>
|
|
<description>The data is sampled on a trailing SCK edge and changed on a leading SCK edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPOLSelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>SCK is low when idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>SCK is high when idle</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DORDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSB</name>
|
|
<description>MSB is transferred first</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB</name>
|
|
<description>LSB is transferred first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>SPIS Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT</name>
|
|
<description>9 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLOADEN</name>
|
|
<description>Data Preload Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSDE</name>
|
|
<description>Slave Select Low Detect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSSEN</name>
|
|
<description>Master Slave Select Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMODE</name>
|
|
<description>Address Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>AMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>SPI Address mask </description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_ADDRESSES</name>
|
|
<description>Two unique Addressess</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE</name>
|
|
<description>Address Range</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>SPIS Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ICSPACE</name>
|
|
<description>Inter-Character Spacing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_8BIT</name>
|
|
<description>Transaction from and to DATA register are 8-bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_32BIT</name>
|
|
<description>Transaction from and to DATA register are 32-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>SPIS Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>SPIS Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>SPIS Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>SPIS Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>SPIS Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENERR</name>
|
|
<description>Transaction Length Error</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>SPIS Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>LENGTH Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>SPIS Length</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Data Length Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>SPIS Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRMASK</name>
|
|
<description>Address Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>SPIS Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>SPIS Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>SPIM</name>
|
|
<description>SPI Master Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomSpim</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>SPIM Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOPO</name>
|
|
<description>Data Out Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DOPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>DO on PAD[0], SCK on PAD[1] and SS on PAD[2]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>DO on PAD[3], SCK on PAD[1] and SS on PAD[2]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIPO</name>
|
|
<description>Data In Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DIPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used as data input</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD1</name>
|
|
<description>SERCOM PAD[1] is used as data input</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>SERCOM PAD[2] is used as data input</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM PAD[3] is used as data input</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FORMSelect</name>
|
|
<enumeratedValue>
|
|
<name>SPI_FRAME</name>
|
|
<description>SPI Frame</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_FRAME_WITH_ADDR</name>
|
|
<description>SPI Frame with Addr</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPHASelect</name>
|
|
<enumeratedValue>
|
|
<name>LEADING_EDGE</name>
|
|
<description>The data is sampled on a leading SCK edge and changed on a trailing SCK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRAILING_EDGE</name>
|
|
<description>The data is sampled on a trailing SCK edge and changed on a leading SCK edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPOLSelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>SCK is low when idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>SCK is high when idle</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DORDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSB</name>
|
|
<description>MSB is transferred first</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB</name>
|
|
<description>LSB is transferred first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>SPIM Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT</name>
|
|
<description>9 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLOADEN</name>
|
|
<description>Data Preload Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSDE</name>
|
|
<description>Slave Select Low Detect Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSSEN</name>
|
|
<description>Master Slave Select Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AMODE</name>
|
|
<description>Address Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>AMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>SPI Address mask </description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_ADDRESSES</name>
|
|
<description>Two unique Addressess</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE</name>
|
|
<description>Address Range</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>SPIM Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ICSPACE</name>
|
|
<description>Inter-Character Spacing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_8BIT</name>
|
|
<description>Transaction from and to DATA register are 8-bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_TRANS_32BIT</name>
|
|
<description>Transaction from and to DATA register are 32-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>SPIM Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>SPIM Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>SPIM Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>SPIM Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSL</name>
|
|
<description>Slave Select Low Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>SPIM Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENERR</name>
|
|
<description>Transaction Length Error</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>SPIM Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>LENGTH Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>SPIM Length</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Data Length Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>SPIM Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRMASK</name>
|
|
<description>Address Mask</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>SPIM Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>SPIM Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>USART_EXT</name>
|
|
<description>USART EXTERNAL CLOCK Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomUsart_ext</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>USART_EXT Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Invert</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Invert</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPR</name>
|
|
<description>Sample</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SAMPRSelect</name>
|
|
<enumeratedValue>
|
|
<name>16X_ARITHMETIC</name>
|
|
<description>16x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16X_FRACTIONAL</name>
|
|
<description>16x over-sampling using fractional baudrate generation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X_ARITHMETIC</name>
|
|
<description>8x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X_FRACTIONAL</name>
|
|
<description>8x over-sampling using fractional baudrate generation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3X_ARITHMETIC</name>
|
|
<description>3x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXPO</name>
|
|
<description>Transmit Data Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TXPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used for data transmission</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM_PAD[0] is used for data transmission</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPO</name>
|
|
<description>Receive Data Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RXPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used for data reception</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD1</name>
|
|
<description>SERCOM PAD[1] is used for data reception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>SERCOM PAD[2] is used for data reception</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM PAD[3] is used for data reception</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPA</name>
|
|
<description>Sample Adjustment</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FORMSelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_NO_PARITY</name>
|
|
<description>USART frame</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_WITH_PARITY</name>
|
|
<description>USART frame with parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_LIN_MASTER_MODE</name>
|
|
<description>LIN Master - Break and sync generation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_AUTO_BAUD_NO_PARITY</name>
|
|
<description>Auto-baud - break detection and auto-baud</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_AUTO_BAUD_WITH_PARITY</name>
|
|
<description>Auto-baud - break detection and auto-baud with parity</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_ISO_7816</name>
|
|
<description>ISO 7816</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMODE</name>
|
|
<description>Communication Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous Communication</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Communication</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPOLSelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DORDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSB</name>
|
|
<description>MSB is transmitted first</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB</name>
|
|
<description>LSB is transmitted first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>USART_EXT Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 Bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT</name>
|
|
<description>9 Bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT</name>
|
|
<description>5 Bits</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT</name>
|
|
<description>6 Bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT</name>
|
|
<description>7 Bits</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBMODE</name>
|
|
<description>Stop Bit Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SBMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>1_BIT</name>
|
|
<description>One Stop Bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BIT</name>
|
|
<description>Two Stop Bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COLDEN</name>
|
|
<description>Collision Detection Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFDE</name>
|
|
<description>Start of Frame Detection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENC</name>
|
|
<description>Encoding Format</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Parity Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINCMD</name>
|
|
<description>LIN Command</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>USART_EXT Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GTIME</name>
|
|
<description>Guard Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKLEN</name>
|
|
<description>LIN Master Break Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDRDLY</name>
|
|
<description>LIN Master Header Delay</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INACK</name>
|
|
<description>Inhibit Not Acknowledge</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSNACK</name>
|
|
<description>Disable Successive NACK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAXITER</name>
|
|
<description>Maximum Iterations</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_WRITE_CHSIZE</name>
|
|
<description>Data reads and writes according CTRLB.CHSIZE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_CHSIZE_WRITE_32BIT</name>
|
|
<description>Data reads according CTRLB.CHSIZE and writes according 32-bit extension</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_32BIT_WRITE_CHSIZE</name>
|
|
<description>Data reads according 32-bit extension and writes according CTRLB.CHSIZE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_WRITE_32BIT</name>
|
|
<description>Data reads and writes according 32-bit extension</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>USART_EXT Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRAC_MODE</name>
|
|
<description>USART_EXT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRACFP_MODE</name>
|
|
<description>USART_EXT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_USARTFP_MODE</name>
|
|
<description>USART_EXT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPL</name>
|
|
<description>USART_EXT Receive Pulse Length</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPL</name>
|
|
<description>Receive Pulse Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>USART_EXT Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>USART_EXT Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>USART_EXT Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART_EXT Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Frame Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Inconsistent Sync Field</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLL</name>
|
|
<description>Collision Detected</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmitter Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Maximum Number of Repetitions Reached</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>USART_EXT Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXERRCNT</name>
|
|
<description>RXERRCNT Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>LENGTH Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXERRCNT</name>
|
|
<description>USART_EXT Receive Error Count</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>USART_EXT Length</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Data Length Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>USART_EXT Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>USART_EXT Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>USART_INT</name>
|
|
<description>USART INTERNAL CLOCK Mode</description>
|
|
<alternateCluster>I2CM</alternateCluster>
|
|
<headerStructName>SercomUsart_int</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>USART_INT Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_EXT_CLK</name>
|
|
<description>USART with external clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_INT_CLK</name>
|
|
<description>USART with internal clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_SLAVE</name>
|
|
<description>SPI in slave operation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI_MASTER</name>
|
|
<description>SPI in master operation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SLAVE</name>
|
|
<description>I2C slave operation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MASTER</name>
|
|
<description>I2C master operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBON</name>
|
|
<description>Immediate Buffer Overflow Notification</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Invert</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Invert</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAMPR</name>
|
|
<description>Sample</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SAMPRSelect</name>
|
|
<enumeratedValue>
|
|
<name>16X_ARITHMETIC</name>
|
|
<description>16x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16X_FRACTIONAL</name>
|
|
<description>16x over-sampling using fractional baudrate generation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X_ARITHMETIC</name>
|
|
<description>8x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X_FRACTIONAL</name>
|
|
<description>8x over-sampling using fractional baudrate generation</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3X_ARITHMETIC</name>
|
|
<description>3x over-sampling using arithmetic baudrate generation</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXPO</name>
|
|
<description>Transmit Data Pinout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TXPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used for data transmission</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM_PAD[0] is used for data transmission</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPO</name>
|
|
<description>Receive Data Pinout</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RXPOSelect</name>
|
|
<enumeratedValue>
|
|
<name>PAD0</name>
|
|
<description>SERCOM PAD[0] is used for data reception</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD1</name>
|
|
<description>SERCOM PAD[1] is used for data reception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD2</name>
|
|
<description>SERCOM PAD[2] is used for data reception</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAD3</name>
|
|
<description>SERCOM PAD[3] is used for data reception</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPA</name>
|
|
<description>Sample Adjustment</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORM</name>
|
|
<description>Frame Format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FORMSelect</name>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_NO_PARITY</name>
|
|
<description>USART frame</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_WITH_PARITY</name>
|
|
<description>USART frame with parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_LIN_MASTER_MODE</name>
|
|
<description>LIN Master - Break and sync generation</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_AUTO_BAUD_NO_PARITY</name>
|
|
<description>Auto-baud - break detection and auto-baud</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_AUTO_BAUD_WITH_PARITY</name>
|
|
<description>Auto-baud - break detection and auto-baud with parity</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART_FRAME_ISO_7816</name>
|
|
<description>ISO 7816</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMODE</name>
|
|
<description>Communication Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous Communication</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Communication</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CPOLSelect</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DORD</name>
|
|
<description>Data Order</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DORDSelect</name>
|
|
<enumeratedValue>
|
|
<name>MSB</name>
|
|
<description>MSB is transmitted first</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB</name>
|
|
<description>LSB is transmitted first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>USART_INT Control B</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHSIZE</name>
|
|
<description>Character Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSIZESelect</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 Bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT</name>
|
|
<description>9 Bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT</name>
|
|
<description>5 Bits</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT</name>
|
|
<description>6 Bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT</name>
|
|
<description>7 Bits</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBMODE</name>
|
|
<description>Stop Bit Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SBMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>1_BIT</name>
|
|
<description>One Stop Bit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BIT</name>
|
|
<description>Two Stop Bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COLDEN</name>
|
|
<description>Collision Detection Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFDE</name>
|
|
<description>Start of Frame Detection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENC</name>
|
|
<description>Encoding Format</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Parity Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINCMD</name>
|
|
<description>LIN Command</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLC</name>
|
|
<description>USART_INT Control C</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GTIME</name>
|
|
<description>Guard Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKLEN</name>
|
|
<description>LIN Master Break Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDRDLY</name>
|
|
<description>LIN Master Header Delay</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INACK</name>
|
|
<description>Inhibit Not Acknowledge</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSNACK</name>
|
|
<description>Disable Successive NACK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAXITER</name>
|
|
<description>Maximum Iterations</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATA32B</name>
|
|
<description>Data 32 Bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>DATA32BSelect</name>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_WRITE_CHSIZE</name>
|
|
<description>Data reads and writes according CTRLB.CHSIZE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_CHSIZE_WRITE_32BIT</name>
|
|
<description>Data reads according CTRLB.CHSIZE and writes according 32-bit extension</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_32BIT_WRITE_CHSIZE</name>
|
|
<description>Data reads according 32-bit extension and writes according CTRLB.CHSIZE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_READ_WRITE_32BIT</name>
|
|
<description>Data reads and writes according 32-bit extension</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>USART_INT Baud Rate</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRAC_MODE</name>
|
|
<description>USART_INT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_FRACFP_MODE</name>
|
|
<description>USART_INT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP</name>
|
|
<description>Fractional Part</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD_USARTFP_MODE</name>
|
|
<description>USART_INT Baud Rate</description>
|
|
<alternateRegister>BAUD</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BAUD</name>
|
|
<description>Baud Rate Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPL</name>
|
|
<description>USART_INT Receive Pulse Length</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPL</name>
|
|
<description>Receive Pulse Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>USART_INT Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>USART_INT Interrupt Enable Set</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>USART_INT Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRE</name>
|
|
<description>Data Register Empty Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transmit Complete Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXC</name>
|
|
<description>Receive Complete Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Receive Start Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIC</name>
|
|
<description>Clear To Send Input Change Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Break Received Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Combined Error Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART_INT Status</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Frame Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUFOVF</name>
|
|
<description>Buffer Overflow</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Inconsistent Sync Field</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COLL</name>
|
|
<description>Collision Detected</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmitter Empty</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITER</name>
|
|
<description>Maximum Number of Repetitions Reached</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>USART_INT Synchronization Busy</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SERCOM Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXERRCNT</name>
|
|
<description>RXERRCNT Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>LENGTH Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXERRCNT</name>
|
|
<description>USART_INT Receive Error Count</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>USART_INT Length</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Data Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LENEN</name>
|
|
<description>Data Length Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>USART_INT Data</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>USART_INT Debug Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM1</name>
|
|
<baseAddress>0x40003400</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM1_0</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_1</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_2</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM1_OTHER</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM2</name>
|
|
<baseAddress>0x41012000</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM2_0</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM2_1</name>
|
|
<value>55</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM2_2</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM2_OTHER</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM3</name>
|
|
<baseAddress>0x41014000</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM3_0</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM3_1</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM3_2</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM3_OTHER</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM4</name>
|
|
<baseAddress>0x43000000</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM4_0</name>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM4_1</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM4_2</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM4_OTHER</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM5</name>
|
|
<baseAddress>0x43000400</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM5_0</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM5_1</name>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM5_2</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM5_OTHER</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM6</name>
|
|
<baseAddress>0x43000800</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM6_0</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM6_1</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM6_2</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM6_OTHER</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SERCOM0">
|
|
<name>SERCOM7</name>
|
|
<baseAddress>0x43000C00</baseAddress>
|
|
<interrupt>
|
|
<name>SERCOM7_0</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM7_1</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM7_2</name>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SERCOM7_OTHER</name>
|
|
<value>77</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SUPC</name>
|
|
<version>U24071.1.0</version>
|
|
<description>Supply Controller</description>
|
|
<groupName>SUPC</groupName>
|
|
<prependToName>SUPC_</prependToName>
|
|
<baseAddress>0x40001800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SUPC_OTHER</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SUPC_BODDET</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Power and Clocks Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD33RDY</name>
|
|
<description>BOD33 Ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOD33DET</name>
|
|
<description>BOD33 Detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B33SRDY</name>
|
|
<description>BOD33 Synchronization Ready</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREGRDY</name>
|
|
<description>Voltage Regulator Ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCORERDY</name>
|
|
<description>VDDCORE Ready</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOD33</name>
|
|
<description>BOD33 Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACTION</name>
|
|
<description>Action when Threshold Crossed</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ACTIONSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>The BOD33 generates a reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>The BOD33 generates an interrupt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BKUP</name>
|
|
<description>The BOD33 puts the device in backup sleep mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDBYCFG</name>
|
|
<description>Configuration in Standby mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNHIB</name>
|
|
<description>Run in Hibernate mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNBKUP</name>
|
|
<description>Run in Backup mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Hysteresis value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Prescaler Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>NODIV</name>
|
|
<description>Not divided</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide clock by 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide clock by 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide clock by 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Divide clock by 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide clock by 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Divide clock by 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide clock by 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Threshold Level for VDD</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBATLEVEL</name>
|
|
<description>Threshold Level in battery backup sleep mode for VBAT</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREG</name>
|
|
<description>VREG Control</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Voltage Regulator Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>LDO</name>
|
|
<description>LDO selection</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUCK</name>
|
|
<description>Buck selection</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNBKUP</name>
|
|
<description>Run in Backup mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSEN</name>
|
|
<description>Voltage Scaling Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSPER</name>
|
|
<description>Voltage Scaling Period</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREF</name>
|
|
<description>VREF Control</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Temperature Sensor Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREFOE</name>
|
|
<description>Voltage Reference Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSSEL</name>
|
|
<description>Temperature Sensor Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>On Demand Contrl</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SELSelect</name>
|
|
<enumeratedValue>
|
|
<name>1V0</name>
|
|
<description>1.0V voltage reference typical value</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V1</name>
|
|
<description>1.1V voltage reference typical value</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V2</name>
|
|
<description>1.2V voltage reference typical value</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>1.25V voltage reference typical value</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V0</name>
|
|
<description>2.0V voltage reference typical value</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V2</name>
|
|
<description>2.2V voltage reference typical value</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V4</name>
|
|
<description>2.4V voltage reference typical value</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>2.5V voltage reference typical value</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BBPS</name>
|
|
<description>Battery Backup Power Switch</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CONF</name>
|
|
<description>Battery Backup Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CONFSelect</name>
|
|
<enumeratedValue>
|
|
<name>BOD33</name>
|
|
<description>The power switch is handled by the BOD33</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED</name>
|
|
<description>In Backup Domain, the backup domain is always supplied by battery backup power</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEEN</name>
|
|
<description>Wake Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKOUT</name>
|
|
<description>Backup Output Control</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENOUT0</name>
|
|
<description>Enable OUT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENOUT1</name>
|
|
<description>Enable OUT1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLROUT0</name>
|
|
<description>Clear OUT0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLROUT1</name>
|
|
<description>Clear OUT1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETOUT0</name>
|
|
<description>Set OUT0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETOUT1</name>
|
|
<description>Set OUT1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCTGLOUT0</name>
|
|
<description>RTC Toggle OUT0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCTGLOUT1</name>
|
|
<description>RTC Toggle OUT1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKIN</name>
|
|
<description>Backup Input Control</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKIN0</name>
|
|
<description>Backup Input 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKIN1</name>
|
|
<description>Backup Input 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TC0</name>
|
|
<version>U22493.0.0</version>
|
|
<description>Basic Timer Counter</description>
|
|
<groupName>TC</groupName>
|
|
<prependToName>TC_</prependToName>
|
|
<baseAddress>0x40003800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TC0</name>
|
|
<value>107</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>COUNT8</name>
|
|
<description>8-bit Counter Mode</description>
|
|
<headerStructName>TcCount8</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT8 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>COUNT8 Period</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT8 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF</name>
|
|
<description>COUNT8 Period Buffer</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT8 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>COUNT16</name>
|
|
<description>16-bit Counter Mode</description>
|
|
<alternateCluster>COUNT8</alternateCluster>
|
|
<headerStructName>TcCount16</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT16 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT16 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>2</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT16 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
<cluster>
|
|
<name>COUNT32</name>
|
|
<description>32-bit Counter Mode</description>
|
|
<alternateCluster>COUNT8</alternateCluster>
|
|
<headerStructName>TcCount32</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Counter Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>COUNT16</name>
|
|
<description>Counter in 16-bit mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT8</name>
|
|
<description>Counter in 8-bit mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT32</name>
|
|
<description>Counter in 32-bit mode</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset the counter on next generic clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset the counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset the counter on next generic clock and reset the prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run during Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONDEMAND</name>
|
|
<description>Clock On Demand</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Prescaler: GCLK_TC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaler: GCLK_TC/2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaler: GCLK_TC/4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaler: GCLK_TC/8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaler: GCLK_TC/16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaler: GCLK_TC/64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Prescaler: GCLK_TC/256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Prescaler: GCLK_TC/1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN0</name>
|
|
<description>Capture On Pin 0 Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COPEN1</name>
|
|
<description>Capture On Pin 1 Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE0</name>
|
|
<description>Capture Mode Channel 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE0Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTMODE1</name>
|
|
<description>Capture mode Channel 1</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTMODE1Select</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot on Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Force a start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force a stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update of double-buffered register</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force a read synchronization of COUNT</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT</name>
|
|
<description>Event Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACTSelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or retrigger TC on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start TC on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Time stamp capture</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period catured in CC0, pulse width in CC1</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period catured in CC1, pulse width in CC0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PW</name>
|
|
<description>Pulse width capture</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCINV</name>
|
|
<description>TC Event Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI</name>
|
|
<description>TC Event Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Event Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>MC Event Output Enable 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>MC Event Output Enable 1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Disable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Disable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Enable 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Enable 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>OVF Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>MC Interrupt Flag 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>MC Interrupt Flag 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave Status Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Synchronization Busy Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare channel buffer 0 valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare channel buffer 1 valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Generation Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MPWM</name>
|
|
<description>Match PWM</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Control C</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform Invert Enable 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform Invert Enable 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Run During Debug</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>swrst</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>CTRLB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>COUNT32 Count</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>COUNT32 Compare and Capture</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Counter/Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>COUNT32 Compare and Capture Buffer</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Counter/Compare Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC1</name>
|
|
<baseAddress>0x40003C00</baseAddress>
|
|
<interrupt>
|
|
<name>TC1</name>
|
|
<value>108</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC2</name>
|
|
<baseAddress>0x4101A000</baseAddress>
|
|
<interrupt>
|
|
<name>TC2</name>
|
|
<value>109</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC3</name>
|
|
<baseAddress>0x4101C000</baseAddress>
|
|
<interrupt>
|
|
<name>TC3</name>
|
|
<value>110</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC4</name>
|
|
<baseAddress>0x42001400</baseAddress>
|
|
<interrupt>
|
|
<name>TC4</name>
|
|
<value>111</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC5</name>
|
|
<baseAddress>0x42001800</baseAddress>
|
|
<interrupt>
|
|
<name>TC5</name>
|
|
<value>112</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC6</name>
|
|
<baseAddress>0x43001400</baseAddress>
|
|
<interrupt>
|
|
<name>TC6</name>
|
|
<value>113</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TC0">
|
|
<name>TC7</name>
|
|
<baseAddress>0x43001800</baseAddress>
|
|
<interrupt>
|
|
<name>TC7</name>
|
|
<value>114</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TCC0</name>
|
|
<version>U22133.1.0</version>
|
|
<description>Timer Counter Control</description>
|
|
<groupName>TCC</groupName>
|
|
<prependToName>TCC_</prependToName>
|
|
<baseAddress>0x41016000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TCC0_OTHER</name>
|
|
<value>85</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC0</name>
|
|
<value>86</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC1</name>
|
|
<value>87</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC2</name>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC3</name>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC4</name>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC0_MC5</name>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESOLUTION</name>
|
|
<description>Enhanced Resolution</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RESOLUTIONSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Dithering is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DITH4</name>
|
|
<description>Dithering is done every 16 PWM frames</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DITH5</name>
|
|
<description>Dithering is done every 32 PWM frames</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DITH6</name>
|
|
<description>Dithering is done every 64 PWM frames</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCALERSelect</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>No division</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Divide by 2</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Divide by 4</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Divide by 8</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Divide by 16</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Divide by 64</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>Divide by 256</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>Divide by 1024</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESCSYNC</name>
|
|
<description>Prescaler and Counter Synchronization Selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PRESCSYNCSelect</name>
|
|
<enumeratedValue>
|
|
<name>GCLK</name>
|
|
<description>Reload or reset counter on next GCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESC</name>
|
|
<description>Reload or reset counter on next prescaler clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNC</name>
|
|
<description>Reload or reset counter on next GCLK and reset prescaler counter</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALOCK</name>
|
|
<description>Auto Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSYNC</name>
|
|
<description>Master Synchronization (only for TCC Slave Instance)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAOS</name>
|
|
<description>DMA One-shot Trigger Mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN0</name>
|
|
<description>Capture Channel 0 Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN1</name>
|
|
<description>Capture Channel 1 Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN2</name>
|
|
<description>Capture Channel 2 Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN3</name>
|
|
<description>Capture Channel 3 Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN4</name>
|
|
<description>Capture Channel 4 Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPTEN5</name>
|
|
<description>Capture Channel 5 Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBCLR</name>
|
|
<description>Control B Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXCMD</name>
|
|
<description>Ramp Index Command</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IDXCMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Command disabled: Index toggles between cycles A and B</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set index: cycle B will be forced in the next cycle</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear index: cycle A will be forced in the next cycle</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOLD</name>
|
|
<description>Hold index: the next cycle will be the same as the current cycle</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>TCC Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Clear start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update or double buffered registers</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force COUNT read synchronization</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBSET</name>
|
|
<description>Control B Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LUPD</name>
|
|
<description>Lock Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXCMD</name>
|
|
<description>Ramp Index Command</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>IDXCMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Command disabled: Index toggles between cycles A and B</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set index: cycle B will be forced in the next cycle</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear index: cycle A will be forced in the next cycle</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOLD</name>
|
|
<description>Hold index: the next cycle will be the same as the current cycle</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>TCC Command</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CMDSelect</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Clear start, restart or retrigger</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Force stop</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Force update or double buffered registers</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSYNC</name>
|
|
<description>Force COUNT read synchronization</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAOS</name>
|
|
<description>One-shot DMA trigger</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Swrst Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRLB</name>
|
|
<description>Ctrlb Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>Status Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Count Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PATT</name>
|
|
<description>Pattern Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Wave Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>Compare Channel 0 Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>Compare Channel 1 Busy</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>Compare Channel 2 Busy</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3</name>
|
|
<description>Compare Channel 3 Busy</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4</name>
|
|
<description>Compare Channel 4 Busy</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5</name>
|
|
<description>Compare Channel 5 Busy</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTRLA</name>
|
|
<description>Recoverable Fault A Configuration</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRC</name>
|
|
<description>Fault A Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Fault input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>MCEx (x=0,1) event input</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Inverted MCEx (x=0,1) event input</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTFAULT</name>
|
|
<description>Alternate fault (A or B) state at the end of the previous period</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEEP</name>
|
|
<description>Fault A Keeper</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUAL</name>
|
|
<description>Fault A Qualification</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLANK</name>
|
|
<description>Fault A Blanking Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLANKSelect</name>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Blanking applied from start of the ramp</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Blanking applied from rising edge of the output waveform</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Blanking applied from falling edge of the output waveform</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Blanking applied from each toggle of the output waveform</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESTART</name>
|
|
<description>Fault A Restart</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Fault A Halt Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HALTSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Halt action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW</name>
|
|
<description>Hardware halt action</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SW</name>
|
|
<description>Software halt action</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NR</name>
|
|
<description>Non-recoverable fault</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL</name>
|
|
<description>Fault A Capture Channel</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Capture value stored in channel 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Capture value stored in channel 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Capture value stored in channel 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Capture value stored in channel 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE</name>
|
|
<description>Fault A Capture Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTURESelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPT</name>
|
|
<description>Capture on fault</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCMIN</name>
|
|
<description>Minimum local detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCMAX</name>
|
|
<description>Maximum local detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DERIV0</name>
|
|
<description>Minimum and maximum local detection</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMARK</name>
|
|
<description>Capture with ramp index as MSB value</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLANKPRESC</name>
|
|
<description>Fault A Blanking Prescaler</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLANKVAL</name>
|
|
<description>Fault A Blanking Time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTERVAL</name>
|
|
<description>Fault A Filter Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTRLB</name>
|
|
<description>Recoverable Fault B Configuration</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRC</name>
|
|
<description>Fault B Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SRCSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Fault input disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>MCEx (x=0,1) event input</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Inverted MCEx (x=0,1) event input</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTFAULT</name>
|
|
<description>Alternate fault (A or B) state at the end of the previous period</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEEP</name>
|
|
<description>Fault B Keeper</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUAL</name>
|
|
<description>Fault B Qualification</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLANK</name>
|
|
<description>Fault B Blanking Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>BLANKSelect</name>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Blanking applied from start of the ramp</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Blanking applied from rising edge of the output waveform</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Blanking applied from falling edge of the output waveform</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Blanking applied from each toggle of the output waveform</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESTART</name>
|
|
<description>Fault B Restart</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Fault B Halt Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>HALTSelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Halt action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW</name>
|
|
<description>Hardware halt action</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SW</name>
|
|
<description>Software halt action</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NR</name>
|
|
<description>Non-recoverable fault</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHSEL</name>
|
|
<description>Fault B Capture Channel</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CHSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Capture value stored in channel 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Capture value stored in channel 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Capture value stored in channel 2</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Capture value stored in channel 3</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTURE</name>
|
|
<description>Fault B Capture Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CAPTURESelect</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No capture</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPT</name>
|
|
<description>Capture on fault</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMIN</name>
|
|
<description>Minimum capture</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMAX</name>
|
|
<description>Maximum capture</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCMIN</name>
|
|
<description>Minimum local detection</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCMAX</name>
|
|
<description>Maximum local detection</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DERIV0</name>
|
|
<description>Minimum and maximum local detection</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTMARK</name>
|
|
<description>Capture with ramp index as MSB value</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLANKPRESC</name>
|
|
<description>Fault B Blanking Prescaler</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLANKVAL</name>
|
|
<description>Fault B Blanking Time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTERVAL</name>
|
|
<description>Fault B Filter Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WEXCTRL</name>
|
|
<description>Waveform Extension Configuration</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OTMX</name>
|
|
<description>Output Matrix</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTIEN0</name>
|
|
<description>Dead-time Insertion Generator 0 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTIEN1</name>
|
|
<description>Dead-time Insertion Generator 1 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTIEN2</name>
|
|
<description>Dead-time Insertion Generator 2 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTIEN3</name>
|
|
<description>Dead-time Insertion Generator 3 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTLS</name>
|
|
<description>Dead-time Low Side Outputs Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTHS</name>
|
|
<description>Dead-time High Side Outputs Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRVCTRL</name>
|
|
<description>Driver Control</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NRE0</name>
|
|
<description>Non-Recoverable State 0 Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE1</name>
|
|
<description>Non-Recoverable State 1 Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE2</name>
|
|
<description>Non-Recoverable State 2 Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE3</name>
|
|
<description>Non-Recoverable State 3 Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE4</name>
|
|
<description>Non-Recoverable State 4 Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE5</name>
|
|
<description>Non-Recoverable State 5 Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE6</name>
|
|
<description>Non-Recoverable State 6 Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRE7</name>
|
|
<description>Non-Recoverable State 7 Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV0</name>
|
|
<description>Non-Recoverable State 0 Output Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV1</name>
|
|
<description>Non-Recoverable State 1 Output Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV2</name>
|
|
<description>Non-Recoverable State 2 Output Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV3</name>
|
|
<description>Non-Recoverable State 3 Output Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV4</name>
|
|
<description>Non-Recoverable State 4 Output Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV5</name>
|
|
<description>Non-Recoverable State 5 Output Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV6</name>
|
|
<description>Non-Recoverable State 6 Output Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRV7</name>
|
|
<description>Non-Recoverable State 7 Output Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN0</name>
|
|
<description>Output Waveform 0 Inversion</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN1</name>
|
|
<description>Output Waveform 1 Inversion</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN2</name>
|
|
<description>Output Waveform 2 Inversion</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN3</name>
|
|
<description>Output Waveform 3 Inversion</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN4</name>
|
|
<description>Output Waveform 4 Inversion</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN5</name>
|
|
<description>Output Waveform 5 Inversion</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN6</name>
|
|
<description>Output Waveform 6 Inversion</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVEN7</name>
|
|
<description>Output Waveform 7 Inversion</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTERVAL0</name>
|
|
<description>Non-Recoverable Fault Input 0 Filter Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FILTERVAL1</name>
|
|
<description>Non-Recoverable Fault Input 1 Filter Value</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCTRL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBGRUN</name>
|
|
<description>Debug Running Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FDDBD</name>
|
|
<description>Fault Detection on Debug Break Detection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVACT0</name>
|
|
<description>Timer/counter Input Event0 Action</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACT0Select</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Start, restart or re-trigger counter on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTEV</name>
|
|
<description>Count on event</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INC</name>
|
|
<description>Increment counter on event</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNT</name>
|
|
<description>Count on active state of asynchronous event</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STAMP</name>
|
|
<description>Stamp capture</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAULT</name>
|
|
<description>Non-recoverable fault</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVACT1</name>
|
|
<description>Timer/counter Input Event1 Action</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EVACT1Select</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Event action disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRIGGER</name>
|
|
<description>Re-trigger counter on event</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIR</name>
|
|
<description>Direction control</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter on event</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEC</name>
|
|
<description>Decrement counter on event</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PPW</name>
|
|
<description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWP</name>
|
|
<description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAULT</name>
|
|
<description>Non-recoverable fault</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTSEL</name>
|
|
<description>Timer/counter Output Event Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CNTSELSelect</name>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>An interrupt/event is generated when a new counter cycle starts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>An interrupt/event is generated when a counter cycle ends</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BETWEEN</name>
|
|
<description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOUNDARY</name>
|
|
<description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFEO</name>
|
|
<description>Overflow/Underflow Output Event Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGEO</name>
|
|
<description>Retrigger Output Event Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTEO</name>
|
|
<description>Timer/counter Output Event Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCINV0</name>
|
|
<description>Inverted Event 0 Input Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCINV1</name>
|
|
<description>Inverted Event 1 Input Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI0</name>
|
|
<description>Timer/counter Event 0 Input Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEI1</name>
|
|
<description>Timer/counter Event 1 Input Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI0</name>
|
|
<description>Match or Capture Channel 0 Event Input Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI1</name>
|
|
<description>Match or Capture Channel 1 Event Input Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI2</name>
|
|
<description>Match or Capture Channel 2 Event Input Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI3</name>
|
|
<description>Match or Capture Channel 3 Event Input Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI4</name>
|
|
<description>Match or Capture Channel 4 Event Input Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEI5</name>
|
|
<description>Match or Capture Channel 5 Event Input Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO0</name>
|
|
<description>Match or Capture Channel 0 Event Output Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO1</name>
|
|
<description>Match or Capture Channel 1 Event Output Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO2</name>
|
|
<description>Match or Capture Channel 2 Event Output Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO3</name>
|
|
<description>Match or Capture Channel 3 Event Output Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO4</name>
|
|
<description>Match or Capture Channel 4 Event Output Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEO5</name>
|
|
<description>Match or Capture Channel 5 Event Output Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRG</name>
|
|
<description>Retrigger Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UFS</name>
|
|
<description>Non-Recoverable Update Fault Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Non-Recoverable Debug Fault Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTA</name>
|
|
<description>Recoverable Fault A Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTB</name>
|
|
<description>Recoverable Fault B Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT0</name>
|
|
<description>Non-Recoverable Fault 0 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Non-Recoverable Fault 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Match or Capture Channel 0 Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Match or Capture Channel 1 Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC2</name>
|
|
<description>Match or Capture Channel 2 Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC3</name>
|
|
<description>Match or Capture Channel 3 Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC4</name>
|
|
<description>Match or Capture Channel 4 Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC5</name>
|
|
<description>Match or Capture Channel 5 Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRG</name>
|
|
<description>Retrigger Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UFS</name>
|
|
<description>Non-Recoverable Update Fault Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Non-Recoverable Debug Fault Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTA</name>
|
|
<description>Recoverable Fault A Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTB</name>
|
|
<description>Recoverable Fault B Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT0</name>
|
|
<description>Non-Recoverable Fault 0 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Non-Recoverable Fault 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Match or Capture Channel 0 Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Match or Capture Channel 1 Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC2</name>
|
|
<description>Match or Capture Channel 2 Interrupt Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC3</name>
|
|
<description>Match or Capture Channel 3 Interrupt Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC4</name>
|
|
<description>Match or Capture Channel 4 Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC5</name>
|
|
<description>Match or Capture Channel 5 Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRG</name>
|
|
<description>Retrigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UFS</name>
|
|
<description>Non-Recoverable Update Fault</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Non-Recoverable Debug Fault</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTA</name>
|
|
<description>Recoverable Fault A</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTB</name>
|
|
<description>Recoverable Fault B</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT0</name>
|
|
<description>Non-Recoverable Fault 0</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Non-Recoverable Fault 1</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC0</name>
|
|
<description>Match or Capture 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC1</name>
|
|
<description>Match or Capture 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC2</name>
|
|
<description>Match or Capture 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC3</name>
|
|
<description>Match or Capture 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC4</name>
|
|
<description>Match or Capture 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MC5</name>
|
|
<description>Match or Capture 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDX</name>
|
|
<description>Ramp</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UFS</name>
|
|
<description>Non-recoverable Update Fault State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Non-Recoverable Debug Fault State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Slave</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PATTBUFV</name>
|
|
<description>Pattern Buffer Valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUFV</name>
|
|
<description>Period Buffer Valid</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTAIN</name>
|
|
<description>Recoverable Fault A Input</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTBIN</name>
|
|
<description>Recoverable Fault B Input</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT0IN</name>
|
|
<description>Non-Recoverable Fault0 Input</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1IN</name>
|
|
<description>Non-Recoverable Fault1 Input</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTA</name>
|
|
<description>Recoverable Fault A State</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULTB</name>
|
|
<description>Recoverable Fault B State</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT0</name>
|
|
<description>Non-Recoverable Fault 0 State</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Non-Recoverable Fault 1 State</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV0</name>
|
|
<description>Compare Channel 0 Buffer Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV1</name>
|
|
<description>Compare Channel 1 Buffer Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV2</name>
|
|
<description>Compare Channel 2 Buffer Valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV3</name>
|
|
<description>Compare Channel 3 Buffer Valid</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV4</name>
|
|
<description>Compare Channel 4 Buffer Valid</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUFV5</name>
|
|
<description>Compare Channel 5 Buffer Valid</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP0</name>
|
|
<description>Compare Channel 0 Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare Channel 1 Value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare Channel 2 Value</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare Channel 3 Value</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare Channel 4 Value</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP5</name>
|
|
<description>Compare Channel 5 Value</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Count</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT_DITH4_MODE</name>
|
|
<description>Count</description>
|
|
<alternateRegister>COUNT</alternateRegister>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT_DITH5_MODE</name>
|
|
<description>Count</description>
|
|
<alternateRegister>COUNT</alternateRegister>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT_DITH6_MODE</name>
|
|
<description>Count</description>
|
|
<alternateRegister>COUNT</alternateRegister>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PATT</name>
|
|
<description>Pattern</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PGE0</name>
|
|
<description>Pattern Generator 0 Output Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE1</name>
|
|
<description>Pattern Generator 1 Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE2</name>
|
|
<description>Pattern Generator 2 Output Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE3</name>
|
|
<description>Pattern Generator 3 Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE4</name>
|
|
<description>Pattern Generator 4 Output Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE5</name>
|
|
<description>Pattern Generator 5 Output Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE6</name>
|
|
<description>Pattern Generator 6 Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGE7</name>
|
|
<description>Pattern Generator 7 Output Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV0</name>
|
|
<description>Pattern Generator 0 Output Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV1</name>
|
|
<description>Pattern Generator 1 Output Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV2</name>
|
|
<description>Pattern Generator 2 Output Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV3</name>
|
|
<description>Pattern Generator 3 Output Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV4</name>
|
|
<description>Pattern Generator 4 Output Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV5</name>
|
|
<description>Pattern Generator 5 Output Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV6</name>
|
|
<description>Pattern Generator 6 Output Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGV7</name>
|
|
<description>Pattern Generator 7 Output Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAVE</name>
|
|
<description>Waveform Control</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WAVEGEN</name>
|
|
<description>Waveform Generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WAVEGENSelect</name>
|
|
<enumeratedValue>
|
|
<name>NFRQ</name>
|
|
<description>Normal frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MFRQ</name>
|
|
<description>Match frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NPWM</name>
|
|
<description>Normal PWM</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSCRITICAL</name>
|
|
<description>Dual-slope critical</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSBOTTOM</name>
|
|
<description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSBOTH</name>
|
|
<description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSTOP</name>
|
|
<description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMP</name>
|
|
<description>Ramp Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RAMPSelect</name>
|
|
<enumeratedValue>
|
|
<name>RAMP1</name>
|
|
<description>RAMP1 operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP2A</name>
|
|
<description>Alternative RAMP2 operation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP2</name>
|
|
<description>RAMP2 operation</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP2C</name>
|
|
<description>Critical RAMP2 operation</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIPEREN</name>
|
|
<description>Circular period Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CICCEN0</name>
|
|
<description>Circular Channel 0 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CICCEN1</name>
|
|
<description>Circular Channel 1 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CICCEN2</name>
|
|
<description>Circular Channel 2 Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CICCEN3</name>
|
|
<description>Circular Channel 3 Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP0</name>
|
|
<description>Swap DTI Output Pair 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP1</name>
|
|
<description>Swap DTI Output Pair 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP2</name>
|
|
<description>Swap DTI Output Pair 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP3</name>
|
|
<description>Swap DTI Output Pair 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER</name>
|
|
<description>Period</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER_DITH4_MODE</name>
|
|
<description>Period</description>
|
|
<alternateRegister>PER</alternateRegister>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER_DITH5_MODE</name>
|
|
<description>Period</description>
|
|
<alternateRegister>PER</alternateRegister>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PER_DITH6_MODE</name>
|
|
<description>Period</description>
|
|
<alternateRegister>PER</alternateRegister>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Period Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC[%s]</name>
|
|
<description>Compare and Capture</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Channel Compare/Capture Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC_DITH4_MODE[%s]</name>
|
|
<description>Compare and Capture</description>
|
|
<alternateRegister>CC[%s]</alternateRegister>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Channel Compare/Capture Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC_DITH5_MODE[%s]</name>
|
|
<description>Compare and Capture</description>
|
|
<alternateRegister>CC[%s]</alternateRegister>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Channel Compare/Capture Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CC_DITH6_MODE[%s]</name>
|
|
<description>Compare and Capture</description>
|
|
<alternateRegister>CC[%s]</alternateRegister>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>Dithering Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Channel Compare/Capture Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PATTBUF</name>
|
|
<description>Pattern Buffer</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PGEB0</name>
|
|
<description>Pattern Generator 0 Output Enable Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB1</name>
|
|
<description>Pattern Generator 1 Output Enable Buffer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB2</name>
|
|
<description>Pattern Generator 2 Output Enable Buffer</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB3</name>
|
|
<description>Pattern Generator 3 Output Enable Buffer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB4</name>
|
|
<description>Pattern Generator 4 Output Enable Buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB5</name>
|
|
<description>Pattern Generator 5 Output Enable Buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB6</name>
|
|
<description>Pattern Generator 6 Output Enable Buffer</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEB7</name>
|
|
<description>Pattern Generator 7 Output Enable Buffer</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB0</name>
|
|
<description>Pattern Generator 0 Output Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB1</name>
|
|
<description>Pattern Generator 1 Output Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB2</name>
|
|
<description>Pattern Generator 2 Output Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB3</name>
|
|
<description>Pattern Generator 3 Output Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB4</name>
|
|
<description>Pattern Generator 4 Output Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB5</name>
|
|
<description>Pattern Generator 5 Output Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB6</name>
|
|
<description>Pattern Generator 6 Output Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGVB7</name>
|
|
<description>Pattern Generator 7 Output Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF_DITH4_MODE</name>
|
|
<description>Period Buffer</description>
|
|
<alternateRegister>PERBUF</alternateRegister>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF_DITH5_MODE</name>
|
|
<description>Period Buffer</description>
|
|
<alternateRegister>PERBUF</alternateRegister>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBUF_DITH6_MODE</name>
|
|
<description>Period Buffer</description>
|
|
<alternateRegister>PERBUF</alternateRegister>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERBUF</name>
|
|
<description>Period Buffer Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF[%s]</name>
|
|
<description>Compare and Capture Buffer</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Channel Compare/Capture Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF_DITH4_MODE[%s]</name>
|
|
<description>Compare and Capture Buffer</description>
|
|
<alternateRegister>CCBUF[%s]</alternateRegister>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Channel Compare/Capture Buffer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF_DITH5_MODE[%s]</name>
|
|
<description>Compare and Capture Buffer</description>
|
|
<alternateRegister>CCBUF[%s]</alternateRegister>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Channel Compare/Capture Buffer Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>CCBUF_DITH6_MODE[%s]</name>
|
|
<description>Compare and Capture Buffer</description>
|
|
<alternateRegister>CCBUF[%s]</alternateRegister>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHERBUF</name>
|
|
<description>Dithering Buffer Cycle Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCBUF</name>
|
|
<description>Channel Compare/Capture Buffer Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TCC0">
|
|
<name>TCC1</name>
|
|
<baseAddress>0x41018000</baseAddress>
|
|
<interrupt>
|
|
<name>TCC1_OTHER</name>
|
|
<value>92</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC1_MC0</name>
|
|
<value>93</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC1_MC1</name>
|
|
<value>94</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC1_MC2</name>
|
|
<value>95</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC1_MC3</name>
|
|
<value>96</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TCC0">
|
|
<name>TCC2</name>
|
|
<baseAddress>0x42000C00</baseAddress>
|
|
<interrupt>
|
|
<name>TCC2_OTHER</name>
|
|
<value>97</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC2_MC0</name>
|
|
<value>98</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC2_MC1</name>
|
|
<value>99</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC2_MC2</name>
|
|
<value>100</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TCC0">
|
|
<name>TCC3</name>
|
|
<baseAddress>0x42001000</baseAddress>
|
|
<interrupt>
|
|
<name>TCC3_OTHER</name>
|
|
<value>101</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC3_MC0</name>
|
|
<value>102</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC3_MC1</name>
|
|
<value>103</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TCC0">
|
|
<name>TCC4</name>
|
|
<baseAddress>0x43001000</baseAddress>
|
|
<interrupt>
|
|
<name>TCC4_OTHER</name>
|
|
<value>104</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC4_MC0</name>
|
|
<value>105</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TCC4_MC1</name>
|
|
<value>106</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<version>U22421.1.0</version>
|
|
<description>True Random Generator</description>
|
|
<groupName>TRNG</groupName>
|
|
<prependToName>TRNG_</prependToName>
|
|
<baseAddress>0x42002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>131</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVCTRL</name>
|
|
<description>Event Control</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDYEO</name>
|
|
<description>Data Ready Event Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATARDY</name>
|
|
<description>Data Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<version>U22221.2.0</version>
|
|
<description>Universal Serial Bus</description>
|
|
<groupName>USB</groupName>
|
|
<prependToName>USB_</prependToName>
|
|
<baseAddress>0x41000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB_OTHER</name>
|
|
<value>80</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_SOF_HSOF</name>
|
|
<value>81</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_TRCPT0</name>
|
|
<value>82</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_TRCPT1</name>
|
|
<value>83</value>
|
|
</interrupt>
|
|
<registers>
|
|
<cluster>
|
|
<name>DEVICE</name>
|
|
<description>USB is Device</description>
|
|
<headerStructName>UsbDevice</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DEVICE</name>
|
|
<description>Device Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST</name>
|
|
<description>Host Mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QOSCTRL</name>
|
|
<description>USB Quality Of Service</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CQOS</name>
|
|
<description>Configuration Quality of Service</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DQOS</name>
|
|
<description>Data Quality of Service</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>DEVICE Control B</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DETACH</name>
|
|
<description>Detach</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPDCONF</name>
|
|
<description>Speed Configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPDCONFSelect</name>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>FS : Full Speed</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS</name>
|
|
<description>LS : Low Speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HS</name>
|
|
<description>HS : High Speed capable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSTM</name>
|
|
<description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NREPLY</name>
|
|
<description>No Reply</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSTJ</name>
|
|
<description>Test mode J</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSTK</name>
|
|
<description>Test mode K</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSTPCKT</name>
|
|
<description>Test packet mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPMODE2</name>
|
|
<description>Specific Operational Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNAK</name>
|
|
<description>Global NAK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMHDSK</name>
|
|
<description>Link Power Management Handshake</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LPMHDSKSelect</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No handshake. LPM is not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACK</name>
|
|
<description>ACK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STALL</name>
|
|
<description>STALL</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DADD</name>
|
|
<description>DEVICE Device Address</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DADD</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDEN</name>
|
|
<description>Device Address Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>DEVICE Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x40</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPEEDSelect</name>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>Full-speed mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS</name>
|
|
<description>Low-speed mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HS</name>
|
|
<description>High-speed mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LINESTATE</name>
|
|
<description>USB Line State Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>LINESTATESelect</name>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SE0/RESET</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FS-J or LS-K State</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>FS-K or LS-J State</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSMSTATUS</name>
|
|
<description>Finite State Machine Status</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSMSTATE</name>
|
|
<description>Fine State Machine Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSMSTATESelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>ON (L0). It corresponds to the Idle and Active states</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>SUSPEND (L2)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEP</name>
|
|
<description>SLEEP (L1)</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DNRESUME</name>
|
|
<description>DNRESUME. Down Stream Resume.</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPRESUME</name>
|
|
<description>UPRESUME. Up Stream Resume.</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>RESET. USB lines Reset.</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FNUM</name>
|
|
<description>DEVICE Device Frame Number</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MFNUM</name>
|
|
<description>Micro Frame Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FNUM</name>
|
|
<description>Frame Number</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FNCERR</name>
|
|
<description>Frame Number CRC Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>DEVICE Device Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>Suspend Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSOF</name>
|
|
<description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORST</name>
|
|
<description>End of Reset Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORSM</name>
|
|
<description>End Of Resume Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMNYET</name>
|
|
<description>Link Power Management Not Yet Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMSUSP</name>
|
|
<description>Link Power Management Suspend Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>DEVICE Device Interrupt Enable Set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>Suspend Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSOF</name>
|
|
<description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORST</name>
|
|
<description>End of Reset Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORSM</name>
|
|
<description>End Of Resume Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMNYET</name>
|
|
<description>Link Power Management Not Yet Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMSUSP</name>
|
|
<description>Link Power Management Suspend Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>DEVICE Device Interrupt Flag</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>Suspend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSOF</name>
|
|
<description>Micro Start of Frame in High Speed Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORST</name>
|
|
<description>End of Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EORSM</name>
|
|
<description>End Of Resume</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMNYET</name>
|
|
<description>Link Power Management Not Yet</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMSUSP</name>
|
|
<description>Link Power Management Suspend</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTSMRY</name>
|
|
<description>DEVICE End Point Interrupt Summary</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPINT0</name>
|
|
<description>End Point 0 Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT1</name>
|
|
<description>End Point 1 Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT2</name>
|
|
<description>End Point 2 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT3</name>
|
|
<description>End Point 3 Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT4</name>
|
|
<description>End Point 4 Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT5</name>
|
|
<description>End Point 5 Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT6</name>
|
|
<description>End Point 6 Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT7</name>
|
|
<description>End Point 7 Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DESCADD</name>
|
|
<description>Descriptor Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DESCADD</name>
|
|
<description>Descriptor Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADCAL</name>
|
|
<description>USB PAD Calibration</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRANSP</name>
|
|
<description>USB Pad Transp calibration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRANSN</name>
|
|
<description>USB Pad Transn calibration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>USB Pad Trim calibration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<name>DEVICE_ENDPOINT[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x100</addressOffset>
|
|
<register>
|
|
<name>EPCFG</name>
|
|
<description>DEVICE_ENDPOINT End Point Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPTYPE0</name>
|
|
<description>End Point Type0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE1</name>
|
|
<description>End Point Type1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETDIS</name>
|
|
<description>NYET Token Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPSTATUSCLR</name>
|
|
<description>DEVICE_ENDPOINT End Point Pipe Status Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGLOUT</name>
|
|
<description>Data Toggle OUT Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTGLIN</name>
|
|
<description>Data Toggle IN Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Current Bank Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ0</name>
|
|
<description>Stall 0 Request Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ1</name>
|
|
<description>Stall 1 Request Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 Ready Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 Ready Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPSTATUSSET</name>
|
|
<description>DEVICE_ENDPOINT End Point Pipe Status Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGLOUT</name>
|
|
<description>Data Toggle OUT Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTGLIN</name>
|
|
<description>Data Toggle IN Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Current Bank Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ0</name>
|
|
<description>Stall 0 Request Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ1</name>
|
|
<description>Stall 1 Request Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 Ready Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 Ready Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPSTATUS</name>
|
|
<description>DEVICE_ENDPOINT End Point Pipe Status</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGLOUT</name>
|
|
<description>Data Toggle Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTGLIN</name>
|
|
<description>Data Toggle In</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Current Bank</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ0</name>
|
|
<description>Stall 0 Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLRQ1</name>
|
|
<description>Stall 1 Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 ready</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 ready</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTFLAG</name>
|
|
<description>DEVICE_ENDPOINT End Point Interrupt Flag</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL0</name>
|
|
<description>Error Flow 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL1</name>
|
|
<description>Error Flow 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXSTP</name>
|
|
<description>Received Setup</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL0</name>
|
|
<description>Stall 0 In/out</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL1</name>
|
|
<description>Stall 1 In/out</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTENCLR</name>
|
|
<description>DEVICE_ENDPOINT End Point Interrupt Clear Flag</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0 Interrupt Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1 Interrupt Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL0</name>
|
|
<description>Error Flow 0 Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL1</name>
|
|
<description>Error Flow 1 Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXSTP</name>
|
|
<description>Received Setup Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL0</name>
|
|
<description>Stall 0 In/Out Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL1</name>
|
|
<description>Stall 1 In/Out Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTENSET</name>
|
|
<description>DEVICE_ENDPOINT End Point Interrupt Set Flag</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL0</name>
|
|
<description>Error Flow 0 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL1</name>
|
|
<description>Error Flow 1 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXSTP</name>
|
|
<description>Received Setup Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL0</name>
|
|
<description>Stall 0 In/out Interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL1</name>
|
|
<description>Stall 1 In/out Interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</cluster>
|
|
<cluster>
|
|
<name>HOST</name>
|
|
<description>USB is Host</description>
|
|
<alternateCluster>DEVICE</alternateCluster>
|
|
<headerStructName>UsbHost</headerStructName>
|
|
<addressOffset>0x0</addressOffset>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control A</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUNSTDBY</name>
|
|
<description>Run in Standby Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>MODESelect</name>
|
|
<enumeratedValue>
|
|
<name>DEVICE</name>
|
|
<description>Device Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST</name>
|
|
<description>Host Mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset Synchronization Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QOSCTRL</name>
|
|
<description>USB Quality Of Service</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CQOS</name>
|
|
<description>Configuration Quality of Service</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DQOS</name>
|
|
<description>Data Quality of Service</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLB</name>
|
|
<description>HOST Control B</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>Send USB Resume</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPDCONF</name>
|
|
<description>Speed Configuration for Host</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SPDCONFSelect</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESUME</name>
|
|
<description>Auto Resume Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSTJ</name>
|
|
<description>Test mode J</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSTK</name>
|
|
<description>Test mode K</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOFE</name>
|
|
<description>Start of Frame Generation Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSRESET</name>
|
|
<description>Send USB Reset</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSOK</name>
|
|
<description>VBUS is OK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L1RESUME</name>
|
|
<description>Send L1 Resume</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSOFC</name>
|
|
<description>HOST Host Start Of Frame Control</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLENC</name>
|
|
<description>Frame Length Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLENCE</name>
|
|
<description>Frame Length Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>HOST Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINESTATE</name>
|
|
<description>USB Line State Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSMSTATUS</name>
|
|
<description>Finite State Machine Status</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSMSTATE</name>
|
|
<description>Fine State Machine Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<enumeratedValues>
|
|
<name>FSMSTATESelect</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>ON (L0). It corresponds to the Idle and Active states</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUSPEND</name>
|
|
<description>SUSPEND (L2)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEP</name>
|
|
<description>SLEEP (L1)</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DNRESUME</name>
|
|
<description>DNRESUME. Down Stream Resume.</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPRESUME</name>
|
|
<description>UPRESUME. Up Stream Resume.</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>RESET. USB lines Reset.</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FNUM</name>
|
|
<description>HOST Host Frame Number</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MFNUM</name>
|
|
<description>Micro Frame Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FNUM</name>
|
|
<description>Frame Number</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLENHIGH</name>
|
|
<description>HOST Host Frame Length</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLENHIGH</name>
|
|
<description>Frame Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>HOST Host Interrupt Enable Clear</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSOF</name>
|
|
<description>Host Start Of Frame Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>BUS Reset Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DNRSM</name>
|
|
<description>DownStream to Device Interrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume from Device Interrupt Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access Interrupt Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCONN</name>
|
|
<description>Device Connection Interrupt Disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDISC</name>
|
|
<description>Device Disconnection Interrupt Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>HOST Host Interrupt Enable Set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSOF</name>
|
|
<description>Host Start Of Frame Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Bus Reset Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DNRSM</name>
|
|
<description>DownStream to the Device Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume fromthe device Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCONN</name>
|
|
<description>Link Power Management Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDISC</name>
|
|
<description>Device Disconnection Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>HOST Host Interrupt Flag</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSOF</name>
|
|
<description>Host Start Of Frame</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Bus Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake Up</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DNRSM</name>
|
|
<description>Downstream</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPRSM</name>
|
|
<description>Upstream Resume from the Device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMACER</name>
|
|
<description>Ram Access</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCONN</name>
|
|
<description>Device Connection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDISC</name>
|
|
<description>Device Disconnection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTSMRY</name>
|
|
<description>HOST Pipe Interrupt Summary</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPINT0</name>
|
|
<description>Pipe 0 Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT1</name>
|
|
<description>Pipe 1 Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT2</name>
|
|
<description>Pipe 2 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT3</name>
|
|
<description>Pipe 3 Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT4</name>
|
|
<description>Pipe 4 Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT5</name>
|
|
<description>Pipe 5 Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT6</name>
|
|
<description>Pipe 6 Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPINT7</name>
|
|
<description>Pipe 7 Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DESCADD</name>
|
|
<description>Descriptor Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DESCADD</name>
|
|
<description>Descriptor Address Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PADCAL</name>
|
|
<description>USB PAD Calibration</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRANSP</name>
|
|
<description>USB Pad Transp calibration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRANSN</name>
|
|
<description>USB Pad Transn calibration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>USB Pad Trim calibration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<name>HOST_PIPE[%s]</name>
|
|
<description/>
|
|
<addressOffset>0x100</addressOffset>
|
|
<register>
|
|
<name>PCFG</name>
|
|
<description>HOST_PIPE End Point Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PTOKEN</name>
|
|
<description>Pipe Token</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK</name>
|
|
<description>Pipe Bank</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTYPE</name>
|
|
<description>Pipe Type</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BINTERVAL</name>
|
|
<description>HOST_PIPE Bus Access Period of Pipe</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BITINTERVAL</name>
|
|
<description>Bit Interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSTATUSCLR</name>
|
|
<description>HOST_PIPE End Point Pipe Status Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGL</name>
|
|
<description>Data Toggle clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Curren Bank clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFREEZE</name>
|
|
<description>Pipe Freeze Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 Ready Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 Ready Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSTATUSSET</name>
|
|
<description>HOST_PIPE End Point Pipe Status Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGL</name>
|
|
<description>Data Toggle Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Current Bank Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFREEZE</name>
|
|
<description>Pipe Freeze Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 Ready Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 Ready Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSTATUS</name>
|
|
<description>HOST_PIPE End Point Pipe Status</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGL</name>
|
|
<description>Data Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CURBK</name>
|
|
<description>Current Bank</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFREEZE</name>
|
|
<description>Pipe Freeze</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK0RDY</name>
|
|
<description>Bank 0 ready</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK1RDY</name>
|
|
<description>Bank 1 ready</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTFLAG</name>
|
|
<description>HOST_PIPE Pipe Interrupt Flag</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL</name>
|
|
<description>Error Flow Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Pipe Error Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSTP</name>
|
|
<description>Transmit Setup Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTENCLR</name>
|
|
<description>HOST_PIPE Pipe Interrupt Flag Clear</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0 Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1 Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL</name>
|
|
<description>Error Flow Interrupt Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Pipe Error Interrupt Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSTP</name>
|
|
<description>Transmit Setup Interrupt Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Inetrrupt Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTENSET</name>
|
|
<description>HOST_PIPE Pipe Interrupt Flag Set</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRCPT0</name>
|
|
<description>Transfer Complete 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCPT1</name>
|
|
<description>Transfer Complete 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRFAIL</name>
|
|
<description>Error Flow Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Pipe Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSTP</name>
|
|
<description>Transmit Setup Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<version>U22511.1.0</version>
|
|
<description>Watchdog Timer</description>
|
|
<groupName>WDT</groupName>
|
|
<prependToName>WDT_</prependToName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xD</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDT</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRLA</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WEN</name>
|
|
<description>Watchdog Timer Window Mode Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALWAYSON</name>
|
|
<description>Always-On</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0xBB</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Time-Out Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PERSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Window Mode Time-Out Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>WINDOWSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EWCTRL</name>
|
|
<description>Early Warning Interrupt Control</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x0B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWOFFSET</name>
|
|
<description>Early Warning Interrupt Time Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<name>EWOFFSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>CYC8</name>
|
|
<description>8 clock cycles</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16</name>
|
|
<description>16 clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC32</name>
|
|
<description>32 clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC64</name>
|
|
<description>64 clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC128</name>
|
|
<description>128 clock cycles</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC256</name>
|
|
<description>256 clock cycles</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC512</name>
|
|
<description>512 clock cycles</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC1024</name>
|
|
<description>1024 clock cycles</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC2048</name>
|
|
<description>2048 clock cycles</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC4096</name>
|
|
<description>4096 clock cycles</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC8192</name>
|
|
<description>8192 clock cycles</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CYC16384</name>
|
|
<description>16384 clock cycles</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt Flag Status and Clear</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Early Warning</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Synchronization Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WEN</name>
|
|
<description>Window Enable Synchronization Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALWAYSON</name>
|
|
<description>Always-On Synchronization Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Clear Synchronization Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR</name>
|
|
<description>Clear</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Watchdog Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLEARSelect</name>
|
|
<enumeratedValue>
|
|
<name>KEY</name>
|
|
<description>Clear Key</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CoreDebug</name>
|
|
<description>Core Debug Register</description>
|
|
<groupName>CoreDebug</groupName>
|
|
<prependToName>CoreDebug_</prependToName>
|
|
<baseAddress>0xE000EDF0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DHCSR</name>
|
|
<description>Debug Halting Control and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>C_DEBUGEN</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_HALT</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_STEP</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_MASKINTS</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C_SNAPSTALL</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S_REGRDY</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_HALT</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_SLEEP</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_LOCKUP</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_RETIRE_ST</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S_RESET_ST</name>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGKEY</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRSR</name>
|
|
<description>Debug Core Register Selector Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>REGSEL</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REGWnR</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRDR</name>
|
|
<description>Debug Core Register Data Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>DEMCR</name>
|
|
<description>Debug Exception and Monitor Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VC_CORERESET</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_MMERR</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_NOCPERR</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_CHKERR</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_STATERR</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_BUSERR</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_INTERR</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VC_HARDERR</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_EN</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_PEND</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_STEP</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON_REQ</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRCENA</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DWT</name>
|
|
<description>Data Watchpoint and Trace Register</description>
|
|
<groupName>DWT</groupName>
|
|
<prependToName>DWT_</prependToName>
|
|
<baseAddress>0xE0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CYCCNTENA</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POSTPRESET</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POSTINIT</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCTAP</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCTAP</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCSAMPLENA</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXCTRCENA</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPIEVTENA</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXCEVTENA</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPEVTENA</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSUEVTENA</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FOLDEVTENA</name>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCEVTENA</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOPRFCNT</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOCYCCNT</name>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOEXTTRIG</name>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOTRCPKT</name>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NUMCOMP</name>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CYCCNT</name>
|
|
<description>Cycle Count Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>CPICNT</name>
|
|
<description>CPI Count Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CPICNT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXCCNT</name>
|
|
<description>Exception Overhead Count Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>EXCCNT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLEEPCNT</name>
|
|
<description>Sleep Count Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPCNT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSUCNT</name>
|
|
<description>LSU Count Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>LSUCNT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOLDCNT</name>
|
|
<description>Folded-instruction Count Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>FOLDCNT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSR</name>
|
|
<description>Program Counter Sample Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>COMP0</name>
|
|
<description>Comparator Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>MASK0</name>
|
|
<description>Mask Register 0</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUNCTION0</name>
|
|
<description>Function Register 0</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCMATCH</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP1</name>
|
|
<description>Comparator Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>MASK1</name>
|
|
<description>Mask Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUNCTION1</name>
|
|
<description>Function Register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCMATCH</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP2</name>
|
|
<description>Comparator Register 2</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>MASK2</name>
|
|
<description>Mask Register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUNCTION2</name>
|
|
<description>Function Register 2</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCMATCH</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP3</name>
|
|
<description>Comparator Register 3</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>MASK3</name>
|
|
<description>Mask Register 3</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUNCTION3</name>
|
|
<description>Function Register 3</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMITRANGE</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CYCMATCH</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LNK1ENA</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR1</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ETM</name>
|
|
<description>Embedded Trace Macrocell</description>
|
|
<groupName>ETM</groupName>
|
|
<prependToName>ETM_</prependToName>
|
|
<baseAddress>0xE0041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>ETM Main Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000411</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETMPD</name>
|
|
<description>ETM Power Down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTSIZE</name>
|
|
<description>Port Size bits 2:0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Processor</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BROUT</name>
|
|
<description>Branch Output</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGRQ</name>
|
|
<description>Debug Request Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROG</name>
|
|
<description>ETM Programming</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL</name>
|
|
<description>ETM Port Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTMODE2</name>
|
|
<description>Port Mode bit 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTMODE</name>
|
|
<description>Port Mode bits 1:0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PORTSIZE3</name>
|
|
<description>Port Size bit 3</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>TimeStamp Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>ETM Configuration Code Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x8C802000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>TRIGGER</name>
|
|
<description>ETM Trigger Event Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>ETM Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>ETM System Configuration Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00020D09</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>TEEVR</name>
|
|
<description>ETM TraceEnable Event Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>TECR1</name>
|
|
<description>ETM TraceEnable Control 1 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>FFLR</name>
|
|
<description>ETM FIFO Full Level Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>CNTRLDVR1</name>
|
|
<description>ETM Free-running Counter Reload Value</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>SYNCFR</name>
|
|
<description>ETM Synchronization Frequency Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000400</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<description>ETM ID Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4114F250</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>ETM Configuration Code Extension Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x18541800</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>TESSEICR</name>
|
|
<description>ETM TraceEnable Start/Stop EmbeddedICE Control Register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>TSEVT</name>
|
|
<description>ETM TimeStamp Event Register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>TRACEIDR</name>
|
|
<description>ETM CoreSight Trace ID Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IDR2</name>
|
|
<description>ETM ID Register 2</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PDSR</name>
|
|
<description>ETM Device Power-Down Status Register</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ITMISCIN</name>
|
|
<description>ETM Integration Test Miscellaneous Inputs</description>
|
|
<addressOffset>0xEE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>ITTRIGOUT</name>
|
|
<description>ETM Integration Test Trigger Out</description>
|
|
<addressOffset>0xEE8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
</register>
|
|
<register>
|
|
<name>ITATBCTR2</name>
|
|
<description>ETM Integration Test ATB Control 2</description>
|
|
<addressOffset>0xEF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>ITATBCTR0</name>
|
|
<description>ETM Integration Test ATB Control 0</description>
|
|
<addressOffset>0xEF8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
</register>
|
|
<register>
|
|
<name>ITCTRL</name>
|
|
<description>ETM Integration Mode Control Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTEGRATION</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLAIMSET</name>
|
|
<description>ETM Claim Tag Set Register</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>CLAIMCLR</name>
|
|
<description>ETM Claim Tag Clear Register</description>
|
|
<addressOffset>0xFA4</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>LAR</name>
|
|
<description>ETM Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>ETM Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>Present</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Access</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ByteAcc</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTHSTATUS</name>
|
|
<description>ETM Authentication Status Register</description>
|
|
<addressOffset>0xFB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>DEVTYPE</name>
|
|
<description>ETM CoreSight Device Type Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000013</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR4</name>
|
|
<description>ETM Peripheral Identification Register #4</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR5</name>
|
|
<description>ETM Peripheral Identification Register #5</description>
|
|
<addressOffset>0xFD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR6</name>
|
|
<description>ETM Peripheral Identification Register #6</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR7</name>
|
|
<description>ETM Peripheral Identification Register #7</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR0</name>
|
|
<description>ETM Peripheral Identification Register #0</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000025</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR1</name>
|
|
<description>ETM Peripheral Identification Register #1</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B9</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR2</name>
|
|
<description>ETM Peripheral Identification Register #2</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000B</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PIDR3</name>
|
|
<description>ETM Peripheral Identification Register #3</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CIDR0</name>
|
|
<description>ETM Component Identification Register #0</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CIDR1</name>
|
|
<description>ETM Component Identification Register #1</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CIDR2</name>
|
|
<description>ETM Component Identification Register #2</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CIDR3</name>
|
|
<description>ETM Component Identification Register #3</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FPU</name>
|
|
<description>Floating Point Unit</description>
|
|
<groupName>FPU</groupName>
|
|
<prependToName>FPU_</prependToName>
|
|
<baseAddress>0xE000EF30</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FPCCR</name>
|
|
<description>Floating-Point Context Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSPACT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>THREAD</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFRDY</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMRDY</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFRDY</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONRDY</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSPEN</name>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASPEN</name>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPCAR</name>
|
|
<description>Floating-Point Context Address Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address for FP registers in exception stack frame</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPDSCR</name>
|
|
<description>Floating-Point Default Status Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RMODE</name>
|
|
<description>Default value for FPSCR.RMODE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>RMODESelect</name>
|
|
<enumeratedValue>
|
|
<name>RN</name>
|
|
<description>Round to Nearest</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RP</name>
|
|
<description>Round towards Positive Infinity</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RM</name>
|
|
<description>Round towards Negative Infinity</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RZ</name>
|
|
<description>Round towards Zero</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FZ</name>
|
|
<description>Default value for FPSCR.FZ</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DN</name>
|
|
<description>Default value for FPSCR.DN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHP</name>
|
|
<description>Default value for FPSCR.AHP</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MVFR0</name>
|
|
<description>Media and FP Feature Register 0</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>A_SIMD_registers</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Single_precision</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Double_precision</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP_excep_trapping</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Divide</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Square_root</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Short_vectors</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP_rounding_modes</name>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MVFR1</name>
|
|
<description>Media and FP Feature Register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>FtZ_mode</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>D_NaN_mode</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP_HPFP</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FP_fused_MAC</name>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ITM</name>
|
|
<description>Instrumentation Trace Macrocell</description>
|
|
<groupName>ITM</groupName>
|
|
<prependToName>ITM_</prependToName>
|
|
<baseAddress>0xE0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xF00</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PORT_WORD_MODE[%s]</name>
|
|
<description>ITM Stimulus Port Registers</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PORT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PORT_BYTE_MODE[%s]</name>
|
|
<description>ITM Stimulus Port Registers</description>
|
|
<alternateRegister>PORT_WORD_MODE[%s]</alternateRegister>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PORT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PORT_HWORD_MODE[%s]</name>
|
|
<description>ITM Stimulus Port Registers</description>
|
|
<alternateRegister>PORT_WORD_MODE[%s]</alternateRegister>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PORT</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>ITM Trace Enable Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>ITM Trace Privilege Register</description>
|
|
<addressOffset>0xE40</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRIVMASK</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>ITM Trace Control Register</description>
|
|
<addressOffset>0xE80</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ITMENA</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSENA</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCENA</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWTENA</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWOENA</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLENA</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSPrescale</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTSFREQ</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TraceBusID</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IWR</name>
|
|
<description>ITM Integration Write Register</description>
|
|
<addressOffset>0xEF8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ATVALIDM</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRR</name>
|
|
<description>ITM Integration Read Register</description>
|
|
<addressOffset>0xEFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ATREADYM</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MPU</name>
|
|
<description>Memory Protection Unit</description>
|
|
<groupName>MPU</groupName>
|
|
<prependToName>MPU_</prependToName>
|
|
<baseAddress>0xE000ED90</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TYPE</name>
|
|
<description>MPU Type Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SEPARATE</name>
|
|
<description>Separate instruction and Data Memory MapsRegions</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DREGION</name>
|
|
<description>Number of Data Regions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREGION</name>
|
|
<description>Number of Instruction Regions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>MPU Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>MPU Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFNMIENA</name>
|
|
<description>Enable Hard Fault and NMI handlers</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIVDEFENA</name>
|
|
<description>Enables privileged software access to default memory map</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNR</name>
|
|
<description>MPU Region Number Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region referenced by RBAR and RASR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBAR</name>
|
|
<description>MPU Region Base Address Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>Region number valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RASR</name>
|
|
<description>MPU Region Attribute and Size Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Region Size</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Sub-region disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Bufferable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Cacheable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>TEX bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access Permission</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Execute Never Attribute</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBAR_A1</name>
|
|
<description>MPU Alias 1 Region Base Address Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>Region number valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RASR_A1</name>
|
|
<description>MPU Alias 1 Region Attribute and Size Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Region Size</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Sub-region disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Bufferable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Cacheable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>TEX bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access Permission</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Execute Never Attribute</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBAR_A2</name>
|
|
<description>MPU Alias 2 Region Base Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>Region number valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RASR_A2</name>
|
|
<description>MPU Alias 2 Region Attribute and Size Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Region Size</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Sub-region disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Bufferable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Cacheable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>TEX bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access Permission</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Execute Never Attribute</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBAR_A3</name>
|
|
<description>MPU Alias 3 Region Base Address Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>Region number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>Region number valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RASR_A3</name>
|
|
<description>MPU Alias 3 Region Attribute and Size Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Region Size</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Sub-region disable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Bufferable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Cacheable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>TEX bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access Permission</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Execute Never Attribute</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<prependToName>NVIC_</prependToName>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ISER[%s]</name>
|
|
<description>Interrupt Set Enable Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ICER[%s]</name>
|
|
<description>Interrupt Clear Enable Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ISPR[%s]</name>
|
|
<description>Interrupt Set Pending Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ICPR[%s]</name>
|
|
<description>Interrupt Clear Pending Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>IABR[%s]</name>
|
|
<description>Interrupt Active Bit Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>35</dim>
|
|
<dimIncrement>1</dimIncrement>
|
|
<name>IP[%s]</name>
|
|
<description>Interrupt Priority Register n</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>8</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI0</name>
|
|
<description>Priority of interrupt n</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STIR</name>
|
|
<description>Software Trigger Interrupt Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt ID to trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SysTick</name>
|
|
<description>System timer</description>
|
|
<groupName>SysTick</groupName>
|
|
<prependToName>SysTick_</prependToName>
|
|
<baseAddress>0xE000E010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SysTick Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ENABLESelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Counter disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Counter enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<description>SysTick Exception Request Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>TICKINTSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Counting down to 0 does not assert the SysTick exception request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Counting down to 0 asserts the SysTick exception request</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>Clock Source 0=external, 1=processor</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CLKSOURCESelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>External clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Processor clock</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>Timer counted to 0 since last read of register</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RVR</name>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Value to load into the SysTick Current Value Register when the counter reaches 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CVR</name>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current value at the time the register is accessed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>SysTick Calibration Value Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Reload value to use for 10ms timing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>TENMS is rounded from non-integer ratio</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SKEWSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>10ms calibration value is exact</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>10ms calibration value is inexact, because of the clock frequency</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>No Separate Reference Clock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NOREFSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>The reference clock is provided</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>The reference clock is not provided</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SystemControl</name>
|
|
<description>System Control Registers</description>
|
|
<groupName>SystemControl</groupName>
|
|
<prependToName>SystemControl_</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xD8C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ICTR</name>
|
|
<description>Interrupt Controller Type Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>INTLINESNUM</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<description>Auxiliary Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>DISMCYCINT</name>
|
|
<description>Disable interruption of LDM/STM instructions</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISDEFWBUF</name>
|
|
<description>Disable wruite buffer use during default memory map accesses</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISFOLD</name>
|
|
<description>Disable IT folding</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISFPCA</name>
|
|
<description>Disable automatic update of CONTROL.FPCA</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISOOFP</name>
|
|
<description>Disable out-of-order FP instructions</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPUID Base Register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410FC240</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Processor revision number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PARTNO</name>
|
|
<description>Process Part Number, 0xC24=Cortex-M4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONSTANT</name>
|
|
<description>Constant</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VARIANT</name>
|
|
<description>Variant number</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTER</name>
|
|
<description>Implementer code, 0x41=ARM</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<description>Interrupt Control and State Register</description>
|
|
<addressOffset>0xD04</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Active exception number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>No preempted active exceptions to execute</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Exception number of the highest priority pending enabled exception</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>Interrupt pending flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISRPREEMPT</name>
|
|
<description>Debug only</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>SysTick clear-pending bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSTCLRSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Removes the pending state from the SysTick exception</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>SysTick set-pending bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSTSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: SysTick exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>PendSV clear-pending bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSVCLRSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Removes the pending state from the PendSV exception</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>PendSV set-pending bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>PENDSVSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: PendSV exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>NMI set-pending bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>NMIPENDSETSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Write: no effect; read: NMI exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Write: changes NMI exception state to pending; read: NMI exception is pending</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0xD08</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<description>Application Interrupt and Reset Control Register</description>
|
|
<addressOffset>0xD0C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0xFA050000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTRESET</name>
|
|
<description>Must write 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>Must write 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>System Reset Request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SYSRESETREQSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>No system reset request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Asserts a signal to the outer system that requests a reset</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRIGROUP</name>
|
|
<description>Interrupt priority grouping</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANNESS</name>
|
|
<description>Data endianness, 0=little, 1=big</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>ENDIANNESSSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Little-endian</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Big-endian</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0xD10</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>Sleep-on-exit on handler return</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPONEXITSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Do not sleep when returning to Thread mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Enter sleep, or deep sleep, on return from an ISR</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>Deep Sleep used as low power mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SLEEPDEEPSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Sleep</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Deep sleep</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>Send Event on Pending bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>SEVONPENDSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Configuration and Control Register</description>
|
|
<addressOffset>0xD14</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NONBASETHRDENA</name>
|
|
<description>Indicates how processor enters Thread mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>Enables unprivileged software access to STIR register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Enables unaligned access traps</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>UNALIGN_TRPSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>Do not trap unaligned halfword and word accesses</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>Trap unaligned halfword and word accesses</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>Enables divide by 0 trap</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>Ignore LDM/STM BusFault for -1/-2 priority handlers</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>Indicates stack alignment on exception entry</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<name>STKALIGNSelect</name>
|
|
<enumeratedValue>
|
|
<name>VALUE_0</name>
|
|
<description>4-byte aligned</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALUE_1</name>
|
|
<description>8-byte aligned</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR1</name>
|
|
<description>System Handler Priority Register 1</description>
|
|
<addressOffset>0xD18</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of system handler 4, MemManage</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of system handler 5, BusFault</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of system handler 6, UsageFault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<description>System Handler Priority Register 2</description>
|
|
<addressOffset>0xD1C</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11, SVCall</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<description>System Handler Priority Register 3</description>
|
|
<addressOffset>0xD20</addressOffset>
|
|
<size>32</size>
|
|
<resetValue>0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14, PendSV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15, SysTick exception</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0xD24</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>MEMFAULTACT</name>
|
|
<description>MemManage exception active bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTACT</name>
|
|
<description>BusFault exception active bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTACT</name>
|
|
<description>UsageFault exception active bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>SVCall active bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONITORACT</name>
|
|
<description>DebugMonitor exception active bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>PendSV exception active bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>SysTick exception active bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTPENDED</name>
|
|
<description>UsageFault exception pending bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTPENDED</name>
|
|
<description>MemManage exception pending bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTPENDED</name>
|
|
<description>BusFault exception pending bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>SVCall pending bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTENA</name>
|
|
<description>MemManage enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTENA</name>
|
|
<description>BusFault enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTENA</name>
|
|
<description>UsageFault enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFSR</name>
|
|
<description>Configurable Fault Status Register</description>
|
|
<addressOffset>0xD28</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>IACCVIOL</name>
|
|
<description>Instruction access violation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACCVIOL</name>
|
|
<description>Data access violation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUNSTKERR</name>
|
|
<description>MemManage Fault on unstacking for exception return</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTKERR</name>
|
|
<description>MemManage Fault on stacking for exception entry</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MLSPERR</name>
|
|
<description>MemManager Fault occured during FP lazy state preservation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMARVALID</name>
|
|
<description>MemManage Fault Address Register valid</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBUSERR</name>
|
|
<description>Instruction bus error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRECISERR</name>
|
|
<description>Precise data bus error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IMPRECISERR</name>
|
|
<description>Imprecise data bus error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNSTKERR</name>
|
|
<description>BusFault on unstacking for exception return</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STKERR</name>
|
|
<description>BusFault on stacking for exception entry</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSPERR</name>
|
|
<description>BusFault occured during FP lazy state preservation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFARVALID</name>
|
|
<description>BusFault Address Register valid</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNDEFINSTR</name>
|
|
<description>Undefined instruction UsageFault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVSTATE</name>
|
|
<description>Invalid state UsageFault</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVPC</name>
|
|
<description>Invalid PC load UsageFault</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOCP</name>
|
|
<description>No coprocessor UsageFault</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGNED</name>
|
|
<description>Unaligned access UsageFault</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIVBYZERO</name>
|
|
<description>Divide by zero UsageFault</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFSR</name>
|
|
<description>HardFault Status Register</description>
|
|
<addressOffset>0xD2C</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>VECTTBL</name>
|
|
<description>BusFault on a Vector Table read during exception processing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCED</name>
|
|
<description>Forced Hard Fault</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGEVT</name>
|
|
<description>Debug: always write 0</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0xD30</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFAR</name>
|
|
<description>MemManage Fault Address Register</description>
|
|
<addressOffset>0xD34</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address that generated the MemManage fault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFAR</name>
|
|
<description>BusFault Address Register</description>
|
|
<addressOffset>0xD38</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address that generated the BusFault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<description>Auxiliary Fault Status Register</description>
|
|
<addressOffset>0xD3C</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>IMPDEF</name>
|
|
<description>AUXFAULT input signals</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>PFR[%s]</name>
|
|
<description>Processor Feature Register</description>
|
|
<addressOffset>0xD40</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>DFR</name>
|
|
<description>Debug Feature Register</description>
|
|
<addressOffset>0xD48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>ADR</name>
|
|
<description>Auxiliary Feature Register</description>
|
|
<addressOffset>0xD4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>MMFR[%s]</name>
|
|
<description>Memory Model Feature Register</description>
|
|
<addressOffset>0xD50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<name>ISAR[%s]</name>
|
|
<description>Instruction Set Attributes Register</description>
|
|
<addressOffset>0xD60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>CPACR</name>
|
|
<description>Coprocessor Access Control Register</description>
|
|
<addressOffset>0xD88</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>CP10</name>
|
|
<description>Access privileges for coprocessor 10</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CP10Select</name>
|
|
<enumeratedValue>
|
|
<name>DENIED</name>
|
|
<description>Access denied</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRIV</name>
|
|
<description>Privileged access only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>Full access</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP11</name>
|
|
<description>Access privileges for coprocessor 11</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<name>CP11Select</name>
|
|
<enumeratedValue>
|
|
<name>DENIED</name>
|
|
<description>Access denied</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRIV</name>
|
|
<description>Privileged access only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>Full access</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TPI</name>
|
|
<description>Trace Port Interface Register</description>
|
|
<groupName>TPI</groupName>
|
|
<prependToName>TPI_</prependToName>
|
|
<baseAddress>0xE0040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFD0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SSPSR</name>
|
|
<description>Supported Parallel Port Size Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>CSPSR</name>
|
|
<description>Current Parallel Port Size Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>ACPR</name>
|
|
<description>Asynchronous Clock Prescaler Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPPR</name>
|
|
<description>Selected Pin Protocol Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>TXMODE</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FFSR</name>
|
|
<description>Formatter and Flush Status Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>FlInProg</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FtStopped</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCPresent</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FtNonStop</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FFCR</name>
|
|
<description>Formatter and Flush Control Register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>EnFCont</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TrigIn</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSCR</name>
|
|
<description>Formatter Synchronization Counter Register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>TRIGGER</name>
|
|
<description>TRIGGER</description>
|
|
<addressOffset>0xEE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TRIGGER</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO0</name>
|
|
<description>Integration ETM Data</description>
|
|
<addressOffset>0xEEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ETM0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM1</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM2</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM_bytecount</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM_ATVALID</name>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM_bytecount</name>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM_ATVALID</name>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITATBCTR2</name>
|
|
<description>ITATBCTR2</description>
|
|
<addressOffset>0xEF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ATREADY</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITATBCTR0</name>
|
|
<description>ITATBCTR0</description>
|
|
<addressOffset>0xEF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ATREADY</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO1</name>
|
|
<description>Integration ITM Data</description>
|
|
<addressOffset>0xEFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ITM0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM1</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM2</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM_bytecount</name>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETM_ATVALID</name>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM_bytecount</name>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITM_ATVALID</name>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITCTRL</name>
|
|
<description>Integration Mode Control</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<name>Mode</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLAIMSET</name>
|
|
<description>Claim tag set</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>CLAIMCLR</name>
|
|
<description>Claim tag clear</description>
|
|
<addressOffset>0xFA4</addressOffset>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<name>DEVID</name>
|
|
<description>TPIU_DEVID</description>
|
|
<addressOffset>0xFC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>NrTraceInput</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AsynClkIn</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MinBufSz</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTINVALID</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MANCVALID</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRZVALID</name>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVTYPE</name>
|
|
<description>TPIU_DEVTYPE</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SubType</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MajorType</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|